static int dpi_display_enable(struct omap_dss_device *dssdev) { int r; r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err0; } if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { DSSERR("display already enabled\n"); r = -EINVAL; goto err1; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); r = dpi_basic_init(dssdev); if (r) goto err2; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_clk_enable(DSS_CLK_FCK2); enable_vpll2_power(1); r = dsi_pll_init(1, 1); if (r) goto err3; #endif r = dpi_set_mode(dssdev); if (r) goto err4; mdelay(2); dispc_enable_lcd_out(1); r = dssdev->driver->enable(dssdev); if (r) goto err5; dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; err5: dispc_enable_lcd_out(0); err4: #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dsi_pll_uninit(); err3: dss_clk_disable(DSS_CLK_FCK2); #endif err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); err1: omap_dss_stop_device(dssdev); err0: return r; }
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) { int r; r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err0; } if (cpu_is_omap34xx()) { r = regulator_enable(dpi.vdds_dsi_reg); if (r) goto err1; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); r = dpi_basic_init(dssdev); if (r) goto err2; if (dpi_use_dsi_pll(dssdev)) { dss_clk_enable(DSS_CLK_SYSCK); r = dsi_pll_init(dpi.dsidev, 0, 1); if (r) goto err3; } r = dpi_set_mode(dssdev); if (r) goto err4; mdelay(2); dssdev->manager->enable(dssdev->manager); return 0; err4: if (dpi_use_dsi_pll(dssdev)) dsi_pll_uninit(dpi.dsidev, true); err3: if (dpi_use_dsi_pll(dssdev)) dss_clk_disable(DSS_CLK_SYSCK); err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); if (cpu_is_omap34xx()) regulator_disable(dpi.vdds_dsi_reg); err1: omap_dss_stop_device(dssdev); err0: return r; }
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) { int r; r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err0; } if (cpu_is_omap34xx()) { r = regulator_enable(dpi.vdds_dsi_reg); if (r) goto err1; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); r = dpi_basic_init(dssdev); if (r) goto err2; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_clk_enable(DSS_CLK_SYSCK); r = dsi_pll_init(dssdev, 0, 1); if (r) goto err3; #endif r = dpi_set_mode(dssdev); if (r) goto err4; mdelay(2); dssdev->manager->enable(dssdev->manager); return 0; err4: #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dsi_pll_uninit(); err3: dss_clk_disable(DSS_CLK_SYSCK); #endif err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); if (cpu_is_omap34xx()) regulator_disable(dpi.vdds_dsi_reg); err1: omap_dss_stop_device(dssdev); err0: return r; }
static int dpi_display_enable(struct omap_display *display) { struct omap_panel *panel = display->panel; int r; if (display->state != OMAP_DSS_DISPLAY_DISABLED) { DSSERR("display already enabled\n"); return -EINVAL; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); r = dpi_basic_init(display); if (r) goto err0; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_clk_enable(DSS_CLK_FCK2); r = dsi_pll_init(0, 1); if (r) goto err1; #endif r = dpi_set_mode(display); if (r) goto err2; mdelay(2); dispc_enable_lcd_out(1); r = panel->enable(display); if (r) goto err3; display->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; err3: dispc_enable_lcd_out(0); err2: #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dsi_pll_uninit(); err1: dss_clk_disable(DSS_CLK_FCK2); #endif err0: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
static int dpi_display_resume(struct omap_dss_device *dssdev) { int r = 0; if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_clk_enable(DSS_CLK_FCK2); enable_vpll2_power(1); r = dsi_pll_init(1, 1); if (r) goto err0; r = dpi_set_mode(dssdev); if (r) goto err0; #endif dispc_enable_lcd_out(1); if (dssdev->driver->resume) { r = dssdev->driver->resume(dssdev); if (r) goto err1; } dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; err1: dispc_enable_lcd_out(0); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL err0: DSSERR("<%s!!> err0: failed to init DSI_PLL = %d\n", __func__, r); dss_select_clk_source(0, 0); dsi_pll_uninit(); dss_clk_disable(DSS_CLK_FCK2); enable_vpll2_power(0); #endif dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
static int sdi_display_resume(struct omap_dss_device *dssdev) { int r; if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); r = dss_sdi_enable(); if (r) goto err; mdelay(2); /* TODO: change here if LCD2 support is needed */ dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 1); if (dssdev->driver->resume) dssdev->driver->resume(dssdev); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; err: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
static void rfbi_enable_clocks(bool enable) { if (enable) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); else dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); }
static int sdi_display_resume(struct omap_display *display) { int r; if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; twl4030_enable_regulator(RES_VAUX1); sdi_pad_config(display, 1); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); r = dss_sdi_enable(); if (r) goto err; mdelay(2); dispc_enable_lcd_out(1); if (display->panel->resume) display->panel->resume(display); display->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; err: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); sdi_pad_config(display, 0); twl4030_disable_regulator(RES_VAUX1); return r; }
void dss_dump_clocks(struct seq_file *s) { unsigned long dpll4_ck_rate; unsigned long dpll4_m4_ck_rate; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); seq_printf(s, "- DSS -\n"); seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); if (cpu_is_omap3630()) seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, dss_clk_get_rate(DSS_CLK_FCK1)); else seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", dpll4_ck_rate, dpll4_ck_rate / dpll4_m4_ck_rate, dss_clk_get_rate(DSS_CLK_FCK1)); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); }
static int omap_dss_set_manager(struct omap_overlay *ovl, struct omap_overlay_manager *mgr) { if (!mgr) return -EINVAL; if (ovl->manager) { DSSERR("overlay '%s' already has a manager '%s'\n", ovl->name, ovl->manager->name); return -EINVAL; } if (ovl->info.enabled) { DSSERR("overlay has to be disabled to change the manager\n"); return -EINVAL; } ovl->manager = mgr; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); /* XXX: on manual update display, in auto update mode, a bug happens * here. When an overlay is first enabled on LCD, then it's disabled, * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT * errors. Waiting before changing the channel_out fixes it. I'm * guessing that the overlay is still somehow being used for the LCD, * but I don't understand how or why. */ msleep(40); dispc_set_channel_out(ovl->id, mgr->id); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return 0; }
static int dpi_display_resume(struct omap_dss_device *dssdev) { int r = 0; if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dss_clk_enable(DSS_CLK_FCK2); r = dsi_pll_init(dssdev, 1, 1); if (r) { DSSERR("failed in dsi_pll_init\n"); goto err1; } r = dpi_set_mode(dssdev); if (r) { DSSERR("failed in dpi_set_mode\n"); goto err2; } mdelay(2); #endif dispc_enable_lcd_out(1); if (dssdev->driver->resume) dssdev->driver->resume(dssdev); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return r; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL err2: dsi_pll_uninit(); dss_clk_disable(DSS_CLK_FCK2); err1: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; #endif }
int sdi_init(bool skip_init) { /* we store this for first display enable, then clear it */ sdi.skip_init = skip_init; /* * Enable clocks already here, otherwise there would be a toggle * of them until sdi_display_enable is called. */ if (skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); return 0; }
void dss_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); DUMPREG(DSS_REVISION); DUMPREG(DSS_SYSCONFIG); DUMPREG(DSS_SYSSTATUS); DUMPREG(DSS_CONTROL); DUMPREG(DSS_SDI_CONTROL); DUMPREG(DSS_PLL_CONTROL); DUMPREG(DSS_SDI_STATUS); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); #undef DUMPREG }
static int dpi_display_resume(struct omap_display *display) { if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); dispc_enable_lcd_out(1); if (display->panel->resume) display->panel->resume(display); display->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; }
static int dpi_display_resume(struct omap_dss_device *dssdev) { if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); dispc_enable_lcd_out(1); if (dssdev->driver->resume) dssdev->driver->resume(dssdev); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; }
int sdi_init(bool skip_init) { /* we store this for first display enable, then clear it */ sdi.skip_init = skip_init; sdi.vdds_sdi_reg = dss_get_vdds_sdi(); if (IS_ERR(sdi.vdds_sdi_reg)) { DSSERR("can't get VDDS_SDI regulator\n"); return PTR_ERR(sdi.vdds_sdi_reg); } /* * Enable clocks already here, otherwise there would be a toggle * of them until sdi_display_enable is called. */ if (skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); return 0; }
static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) { u32 irqstatus; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); irqstatus = dss_read_reg(DSS_IRQSTATUS); if (irqstatus & (1<<0)) /* DISPC_IRQ */ dispc_irq_handler(); #ifdef CONFIG_OMAP2_DSS_DSI if (irqstatus & (1<<1)) /* DSI_IRQ */ dsi_irq_handler(); #endif dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return IRQ_HANDLED; }
static int dpi_set_mode(struct omap_dss_device *dssdev) { struct omap_video_timings *t = &dssdev->panel.timings; int lck_div, pck_div; unsigned long fck; unsigned long pck; bool is_tft; int r = 0; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck, &lck_div, &pck_div); #else r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck, &lck_div, &pck_div); #endif if (r) goto err0; pck = fck / lck_div / pck_div / 1000; if (pck != t->pixel_clock) { DSSWARN("Could not find exact pixel clock. " "Requested %d kHz, got %lu kHz\n", t->pixel_clock, pck); t->pixel_clock = pck; } dispc_set_lcd_timings(dssdev->manager->id, t); err0: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); return r; }
static int dpi_set_mode(struct omap_display *display) { struct omap_panel *panel = display->panel; int lck_div, pck_div; unsigned long fck; unsigned long pck; bool is_tft; int r = 0; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); dispc_set_pol_freq(panel); is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0; #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000, &fck, &lck_div, &pck_div); #else r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000, &fck, &lck_div, &pck_div); #endif if (r) goto err0; pck = fck / lck_div / pck_div / 1000; if (pck != panel->timings.pixel_clock) { DSSWARN("Could not find exact pixel clock. " "Requested %d kHz, got %lu kHz\n", panel->timings.pixel_clock, pck); panel->timings.pixel_clock = pck; } dispc_set_lcd_timings(&panel->timings); err0: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
void dss_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); DUMPREG(DSS_REVISION); DUMPREG(DSS_SYSCONFIG); DUMPREG(DSS_SYSSTATUS); if (!cpu_is_omap44xx()) DUMPREG(DSS_IRQSTATUS); DUMPREG(DSS_CONTROL); #ifdef CONFIG_OMAP2_DSS_SDI DUMPREG(DSS_SDI_CONTROL); DUMPREG(DSS_PLL_CONTROL); #endif DUMPREG(DSS_SDI_STATUS); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); #undef DUMPREG }
static int dpi_display_resume(struct omap_dss_device *dssdev) { if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); #ifndef CONFIG_ARCH_OMAP4 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); #endif /* TODO: change here if LCD2 support is needed */ dispc_enable_lcd_out(dssdev->channel, 1); if (dssdev->driver->resume) dssdev->driver->resume(dssdev); dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; return 0; }
void rfbi_dump_regs(struct seq_file *s) { #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); DUMPREG(RFBI_REVISION); DUMPREG(RFBI_SYSCONFIG); DUMPREG(RFBI_SYSSTATUS); DUMPREG(RFBI_CONTROL); DUMPREG(RFBI_PIXEL_CNT); DUMPREG(RFBI_LINE_NUMBER); DUMPREG(RFBI_CMD); DUMPREG(RFBI_PARAM); DUMPREG(RFBI_DATA); DUMPREG(RFBI_READ); DUMPREG(RFBI_STATUS); DUMPREG(RFBI_CONFIG(0)); DUMPREG(RFBI_ONOFF_TIME(0)); DUMPREG(RFBI_CYCLE_TIME(0)); DUMPREG(RFBI_DATA_CYCLE1(0)); DUMPREG(RFBI_DATA_CYCLE2(0)); DUMPREG(RFBI_DATA_CYCLE3(0)); DUMPREG(RFBI_CONFIG(1)); DUMPREG(RFBI_ONOFF_TIME(1)); DUMPREG(RFBI_CYCLE_TIME(1)); DUMPREG(RFBI_DATA_CYCLE1(1)); DUMPREG(RFBI_DATA_CYCLE2(1)); DUMPREG(RFBI_DATA_CYCLE3(1)); DUMPREG(RFBI_VSYNC_WIDTH); DUMPREG(RFBI_HSYNC_WIDTH); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); #undef DUMPREG }
static int dpi_display_resume(struct omap_dss_device *dssdev) { int r = 0; int lcd_channel_ix = 1; int use_dsi_for_hdmi = 0; if (strncmp("hdmi", dssdev->name, 4) == 0) use_dsi_for_hdmi = 1; if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) { DSSINFO("Lcd channel index 1"); dpi2_base = ioremap(DPI2_BASE, 2000); lcd_channel_ix = 1; } else lcd_channel_ix = 0; if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) return -EINVAL; DSSDBG("dpi_display_resume\n"); dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); if (use_dsi_for_hdmi) { dss_clk_enable(DSS_CLK_FCK2); enable_vpll2_power(1); if (cpu_is_omap3630()) r = dsi_pll_init(lcd_channel_ix, dssdev, 1, 1); else r = dsi_pll_init(lcd_channel_ix, dssdev, 0, 1); if (r) goto err0; r = dpi_set_mode(dssdev); if (r) goto err1; } if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 1); else dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 1); if (dssdev->driver->resume) { r = dssdev->driver->resume(dssdev); if (r) goto err2; } dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; /* This is done specifically for HDMI panel * Default HDMI panel timings may not work for all monitors * Reset HDMI panel timings after enabling HDMI. */ if (use_dsi_for_hdmi) dpi_set_timings(dssdev, &dssdev->panel.timings); return 0; err2: if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 0); else dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0); if (use_dsi_for_hdmi) { err1: DSSERR("<%s!!> err0: failed to init DSI_PLL = %d\n", __func__, r); dss_select_clk_source(0, 0); dispc_go(OMAP_DSS_CHANNEL_LCD); while (dispc_go_busy(OMAP_DSS_CHANNEL_LCD)) ; dsi_pll_uninit(dsi1); enable_vpll2_power(0); err0: dss_clk_disable(DSS_CLK_FCK2); } dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
/* PLATFORM DEVICE */ static int omap_dss_probe(struct platform_device *pdev) { struct omap_dss_board_info *pdata = pdev->dev.platform_data; int r; int i; core.pdev = pdev; dss_features_init(); dss_init_overlay_managers(pdev); dss_init_overlays(pdev); r = dss_init_platform_driver(); if (r) { DSSERR("Failed to initialize DSS platform driver\n"); goto err_dss; } /* keep clocks enabled to prevent context saves/restores during init */ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); r = rfbi_init_platform_driver(); if (r) { DSSERR("Failed to initialize rfbi platform driver\n"); goto err_rfbi; } r = dispc_init_platform_driver(); if (r) { DSSERR("Failed to initialize dispc platform driver\n"); goto err_dispc; } r = venc_init_platform_driver(); if (r) { DSSERR("Failed to initialize venc platform driver\n"); goto err_venc; } r = dsi_init_platform_driver(); if (r) { DSSERR("Failed to initialize DSI platform driver\n"); goto err_dsi; } r = hdmi_init_platform_driver(); if (r) { DSSERR("Failed to initialize hdmi\n"); goto err_hdmi; } r = dss_initialize_debugfs(); if (r) goto err_debugfs; for (i = 0; i < pdata->num_devices; ++i) { struct omap_dss_device *dssdev = pdata->devices[i]; r = omap_dss_register_device(dssdev); if (r) { DSSERR("device %d %s register failed %d\n", i, dssdev->name ?: "unnamed", r); while (--i >= 0) omap_dss_unregister_device(pdata->devices[i]); goto err_register; } if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0) pdata->default_device = dssdev; } dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); return 0; err_register: dss_uninitialize_debugfs(); err_debugfs: hdmi_uninit_platform_driver(); err_hdmi: dsi_uninit_platform_driver(); err_dsi: venc_uninit_platform_driver(); err_venc: dispc_uninit_platform_driver(); err_dispc: rfbi_uninit_platform_driver(); err_rfbi: dss_uninit_platform_driver(); err_dss: return r; }
int omapdss_dpi_display_enable(struct omap_dss_device *dssdev) { int r; if (cpu_is_omap44xx() && dssdev->channel != OMAP_DSS_CHANNEL_LCD2) { /* Only LCD2 channel is connected to DPI on OMAP4 */ return -EINVAL; } r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); return r; } if (cpu_is_omap34xx() && !cpu_is_omap3630()) { r = regulator_enable(dpi.vdds_dsi_reg); if (r) goto err0; } /* turn on clock(s) */ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; if (!cpu_is_omap44xx()) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL /*Should need only FCK2 (38.4MHz)*/ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2); #endif dss_mainclk_state_enable(); dpi_basic_init(dssdev); #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL if (!cpu_is_omap44xx()) r = dsi_pll_init(dssdev, 0, 1); else { r = dsi_pll_init(dssdev, 1, 1); } if (r) goto err1; #endif /* CONFIG_OMAP2_DSS_USE_DSI_PLL */ r = dpi_set_mode(dssdev); if (r) goto err2; mdelay(2); if (dssdev->manager) { if (cpu_is_omap44xx()) dpi_start_auto_update(dssdev); dssdev->manager->enable(dssdev->manager); } return 0; err2: #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL dsi_pll_uninit(dssdev->channel == OMAP_DSS_CHANNEL_LCD ? DSI1 : DSI2); err1: #endif dssdev->state = OMAP_DSS_DISPLAY_DISABLED; if (!cpu_is_omap44xx()) dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); dss_mainclk_state_disable(true); if (cpu_is_omap34xx() && !cpu_is_omap3630()) regulator_disable(dpi.vdds_dsi_reg); err0: omap_dss_stop_device(dssdev); return r; }
static int dpi_set_mode(struct omap_dss_device *dssdev) { struct omap_video_timings *t = &dssdev->panel.timings; int lck_div = 0, pck_div = 0; unsigned long fck = 0; unsigned long pck = 0; bool is_tft; int r = 0, lcd_channel_ix = 0; int use_dsi_for_hdmi = 0; if (strncmp("hdmi", dssdev->name, 4) == 0) use_dsi_for_hdmi = 1; if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) lcd_channel_ix = 1; dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD2, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); else dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD, dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; if (use_dsi_for_hdmi) r = dpi_set_dsi_clk(lcd_channel_ix, is_tft, t->pixel_clock * 1000, &fck, &lck_div, &pck_div); else r = dpi_set_dispc_clk(lcd_channel_ix, is_tft, t->pixel_clock * 1000, &fck, &lck_div, &pck_div); if (r) goto err0; if (!cpu_is_omap44xx()) pck = fck / lck_div / pck_div / 1000; else pck = 0; if (pck != t->pixel_clock) { DSSWARN("Could not find exact pixel clock. " "Requested %d kHz, got %lu kHz\n", t->pixel_clock, pck); t->pixel_clock = pck; } if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD2, t); else dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD, t); err0: if (cpu_is_omap44xx() && use_dsi_for_hdmi) { dss_select_clk_source_dsi(lcd_channel_ix, false, false); dsi_pll_uninit(lcd_channel_ix); } dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); return r; }
static int dpi_display_enable(struct omap_dss_device *dssdev) { int r; int lcd_channel_ix = 1; int use_dsi_for_hdmi = 0; if (strncmp("hdmi", dssdev->name, 4) == 0) use_dsi_for_hdmi = 1; if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) { DSSINFO("Lcd channel index 1"); dpi2_base = ioremap(DPI2_BASE, 2000); lcd_channel_ix = 1; } else lcd_channel_ix = 0; r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err0; } if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { DSSERR("display already enabled\n"); r = -EINVAL; goto err1; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); r = dpi_basic_init(dssdev); if (r) goto err2; if (use_dsi_for_hdmi) { dss_clk_enable(DSS_CLK_FCK2); enable_vpll2_power(1); if (cpu_is_omap3630()) r = dsi_pll_init(lcd_channel_ix, dssdev, 1, 1); else /*check param 2*/ r = dsi_pll_init(lcd_channel_ix, dssdev, 0, 1); if (r) goto err3; } r = dpi_set_mode(dssdev); if (r) goto err4; mdelay(2); if (cpu_is_omap44xx()) dpi_start_auto_update(dssdev); if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 1); else dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 1); r = dssdev->driver->enable(dssdev); if (r) goto err5; dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; /* This is done specifically for HDMI panel * Default HDMI panel timings may not work for all monitors * Reset HDMI panel timings after enabling HDMI. */ if (use_dsi_for_hdmi) dpi_set_timings(dssdev, &dssdev->panel.timings); return 0; err5: if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 0); else dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0); err4: if (use_dsi_for_hdmi) { dsi_pll_uninit(lcd_channel_ix); enable_vpll2_power(0); err3: dss_clk_disable(DSS_CLK_FCK2); } err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); err1: omap_dss_stop_device(dssdev); err0: return r; }
int dss_init(struct platform_device *pdev) { int r = 0, dss_irq; u32 rev; struct resource *dss_mem; bool skip_init = false; dss.pdata = pdev->dev.platform_data; dss.pdev = pdev; if (cpu_is_omap44xx()) dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); else dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!dss_mem) { WARN_ON(1); r = -ENODEV; goto fail0; } dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M | DSS_CLK_96M); dss_mainclk_enable(); #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT /* DISPC_CONTROL */ if (omap_readl(0x48050440) & 1) /* LCD enabled? */ skip_init = true; #endif if (!skip_init) { /* disable LCD and DIGIT output. This seems to fix the synclost * problem that we get, if the bootloader starts the DSS and * the kernel resets it */ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); /* We need to wait here a bit, otherwise we sometimes start to * get synclost errors, and after that only power cycle will * restore DSS functionality. I have no idea why this happens. * And we have to wait _before_ resetting the DSS, but after * enabling clocks. */ msleep(50); } /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); #ifdef CONFIG_OMAP2_DSS_VENC REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif if (!cpu_is_omap44xx()) r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); else { dss_irq = platform_get_irq(pdev, 0); r = request_irq(dss_irq, dss_irq_handler_omap2, 0, "OMAP DSS", NULL); } if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } if (cpu_is_omap34xx()) { dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); if (IS_ERR(dss.dpll4_m4_ck)) { DSSERR("Failed to get dpll4_m4_ck\n"); r = PTR_ERR(dss.dpll4_m4_ck); goto fail2; } } dss.dsi1_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.dsi2_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.lcd1_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.lcd2_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M | DSS_CLK_96M); return 0; fail2: if (!cpu_is_omap44xx()) free_irq(INT_24XX_DSS_IRQ, NULL); fail1: iounmap(dss.base); fail0: return r; }
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) { struct omap_video_timings *t = &dssdev->panel.timings; struct dss_clock_info dss_cinfo; struct dispc_clock_info dispc_cinfo; u16 lck_div, pck_div; unsigned long fck; unsigned long pck; int r; r = omap_dss_start_device(dssdev); if (r) { DSSERR("failed to start device\n"); goto err0; } r = regulator_enable(sdi.vdds_sdi_reg); if (r) goto err1; /* In case of skip_init sdi_init has already enabled the clocks */ if (!sdi.skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); sdi_basic_init(); /* 15.5.9.1.2 */ dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi, dssdev->panel.acb); if (!sdi.skip_init) { r = dss_calc_clock_div(1, t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo); } else { r = dss_get_clock_div(&dss_cinfo); r = dispc_get_clock_div(&dispc_cinfo); } if (r) goto err2; fck = dss_cinfo.fck; lck_div = dispc_cinfo.lck_div; pck_div = dispc_cinfo.pck_div; pck = fck / lck_div / pck_div / 1000; if (pck != t->pixel_clock) { DSSWARN("Could not find exact pixel clock. Requested %d kHz, " "got %lu kHz\n", t->pixel_clock, pck); t->pixel_clock = pck; } dispc_set_lcd_timings(t); r = dss_set_clock_div(&dss_cinfo); if (r) goto err2; r = dispc_set_clock_div(&dispc_cinfo); if (r) goto err2; if (!sdi.skip_init) { dss_sdi_init(dssdev->phy.sdi.datapairs); r = dss_sdi_enable(); if (r) goto err1; mdelay(2); } dssdev->manager->enable(dssdev->manager); sdi.skip_init = 0; return 0; err2: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); regulator_disable(sdi.vdds_sdi_reg); err1: omap_dss_stop_device(dssdev); err0: return r; }
static int sdi_display_enable(struct omap_display *display) { struct dispc_clock_info cinfo; u16 lck_div, pck_div; unsigned long fck; struct omap_panel *panel = display->panel; unsigned long pck; int r; if (display->state != OMAP_DSS_DISPLAY_DISABLED) { DSSERR("display already enabled\n"); return -EINVAL; } twl4030_enable_regulator(RES_VAUX1); sdi_pad_config(display, 1); /* In case of skip_init sdi_init has already enabled the clocks */ if (!sdi.skip_init) dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); sdi_basic_init(); /* 15.5.9.1.2 */ panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; dispc_set_pol_freq(panel); if (!sdi.skip_init) r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000, &cinfo); else r = dispc_get_clock_div(&cinfo); if (r) goto err0; fck = cinfo.fck; lck_div = cinfo.lck_div; pck_div = cinfo.pck_div; pck = fck / lck_div / pck_div / 1000; if (pck != panel->timings.pixel_clock) { DSSWARN("Could not find exact pixel clock. Requested %d kHz, " "got %lu kHz\n", panel->timings.pixel_clock, pck); panel->timings.pixel_clock = pck; } dispc_set_lcd_timings(&panel->timings); r = dispc_set_clock_div(&cinfo); if (r) goto err1; if (!sdi.skip_init) { dss_sdi_init(display->hw_config.u.sdi.datapairs); r = dss_sdi_enable(); if (r) goto err1; mdelay(2); } dispc_enable_lcd_out(1); r = panel->enable(display); if (r) goto err2; display->state = OMAP_DSS_DISPLAY_ACTIVE; sdi.skip_init = 0; return 0; err2: dispc_enable_lcd_out(0); err1: err0: dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); twl4030_disable_regulator(RES_VAUX1); return r; }