static int s5p_ehci_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
clk_enable(s5p_ehci->clk);
pm_runtime_resume(&pdev->dev);
s5p_ehci_phy_init(pdev);
/* if EHCI was off, hcd was removed */
if (!s5p_ehci->power_on) {
dev_info(dev, "Nothing to do for the device (power off)\n");
return 0;
}
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
/* Mark hardware accessible again as we are out of D3 state by now */
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
int mask = INTR_MASK;
if (!hcd->self.root_hub->do_remote_wakeup)
mask &= ~STS_PCD;
ehci_writel(ehci, mask, &ehci->regs->intr_enable);
ehci_readl(ehci, &ehci->regs->intr_enable);
return 0;
}
ehci_dbg(ehci, "lost power, restarting\n");
usb_root_hub_lost_power(hcd->self.root_hub);
(void) ehci_halt(ehci);
(void) ehci_reset(ehci);
/* emptying the schedule aborts any urbs */
spin_lock_irq(&ehci->lock);
if (ehci->reclaim)
end_unlink_async(ehci);
ehci_work(ehci);
spin_unlock_irq(&ehci->lock);
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
/* here we "know" root ports should always stay powered */
ehci_port_power(ehci, 1);
hcd->state = HC_STATE_SUSPENDED;
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
s5p_wait_for_cp_resume(pdev, hcd);
#endif
#ifdef CONFIG_MDM_HSIC_PM
set_host_stat(hsic_pm_dev, POWER_ON);
wait_dev_pwr_stat(hsic_pm_dev, POWER_ON);
#endif
return 0;
}
static int ehci_mxc_drv_probe(struct platform_device *pdev)
{
struct mxc_usbh_platform_data *pdata = pdev->dev.platform_data;
struct usb_hcd *hcd;
struct resource *res;
int irq, ret;
unsigned int flags;
struct ehci_mxc_priv *priv;
struct device *dev = &pdev->dev;
struct ehci_hcd *ehci;
dev_info(&pdev->dev, "initializing i.MX USB Controller\n");
if (!pdata) {
dev_err(dev, "No platform data given, bailing out.\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
hcd = usb_create_hcd(&ehci_mxc_hc_driver, dev, dev_name(dev));
if (!hcd)
return -ENOMEM;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err_alloc;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "Found HC with no register addr. Check setup!\n");
ret = -ENODEV;
goto err_get_resource;
}
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
dev_dbg(dev, "controller already in use\n");
ret = -EBUSY;
goto err_request_mem;
}
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
if (!hcd->regs) {
dev_err(dev, "error mapping memory\n");
ret = -EFAULT;
goto err_ioremap;
}
/* enable clocks */
priv->usbclk = clk_get(dev, "usb");
if (IS_ERR(priv->usbclk)) {
ret = PTR_ERR(priv->usbclk);
goto err_clk;
}
clk_enable(priv->usbclk);
if (!cpu_is_mx35() && !cpu_is_mx25()) {
priv->ahbclk = clk_get(dev, "usb_ahb");
if (IS_ERR(priv->ahbclk)) {
ret = PTR_ERR(priv->ahbclk);
goto err_clk_ahb;
}
clk_enable(priv->ahbclk);
}
/* "dr" device has its own clock on i.MX51 */
if (cpu_is_mx51() && (pdev->id == 0)) {
priv->phy1clk = clk_get(dev, "usb_phy1");
if (IS_ERR(priv->phy1clk)) {
ret = PTR_ERR(priv->phy1clk);
goto err_clk_phy;
}
clk_enable(priv->phy1clk);
}
/* call platform specific init function */
if (pdata->init) {
ret = pdata->init(pdev);
if (ret) {
dev_err(dev, "platform init failed\n");
goto err_init;
}
/* platforms need some time to settle changed IO settings */
mdelay(10);
}
ehci = hcd_to_ehci(hcd);
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
/* set up the PORTSCx register */
ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
/* is this really needed? */
msleep(10);
/* Initialize the transceiver */
if (pdata->otg) {
pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET;
ret = otg_init(pdata->otg);
if (ret) {
dev_err(dev, "unable to init transceiver, probably missing\n");
ret = -ENODEV;
goto err_add;
}
ret = otg_set_vbus(pdata->otg, 1);
if (ret) {
dev_err(dev, "unable to enable vbus on transceiver\n");
goto err_add;
}
}
priv->hcd = hcd;
platform_set_drvdata(pdev, priv);
ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
if (ret)
goto err_add;
if (pdata->otg) {
/*
* efikamx and efikasb have some hardware bug which is
* preventing usb to work unless CHRGVBUS is set.
* It's in violation of USB specs
*/
if (machine_is_mx51_efikamx() || machine_is_mx51_efikasb()) {
flags = otg_io_read(pdata->otg, ULPI_OTG_CTRL);
flags |= ULPI_OTG_CTRL_CHRGVBUS;
ret = otg_io_write(pdata->otg, flags, ULPI_OTG_CTRL);
if (ret) {
dev_err(dev, "unable to set CHRVBUS\n");
goto err_add;
}
}
}
return 0;
err_add:
if (pdata && pdata->exit)
pdata->exit(pdev);
err_init:
if (priv->phy1clk) {
clk_disable(priv->phy1clk);
clk_put(priv->phy1clk);
}
err_clk_phy:
if (priv->ahbclk) {
clk_disable(priv->ahbclk);
clk_put(priv->ahbclk);
}
err_clk_ahb:
clk_disable(priv->usbclk);
clk_put(priv->usbclk);
err_clk:
iounmap(hcd->regs);
err_ioremap:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err_request_mem:
err_get_resource:
kfree(priv);
err_alloc:
usb_put_hcd(hcd);
return ret;
}
static int tegra_ehci_internal_port_reset(
struct ehci_hcd *ehci,
u32 __iomem *portsc_reg
)
{
u32 temp;
unsigned long flags;
int retval = 0;
int i, tries;
u32 saved_usbintr;
spin_lock_irqsave(&ehci->lock, flags);
saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
/* disable USB interrupt */
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
spin_unlock_irqrestore(&ehci->lock, flags);
/*
* Here we have to do Port Reset at most twice for
* Port Enable bit to be set.
*/
for (i = 0; i < 2; i++) {
temp = ehci_readl(ehci, portsc_reg);
temp |= PORT_RESET;
ehci_writel(ehci, temp, portsc_reg);
mdelay(10);
temp &= ~PORT_RESET;
ehci_writel(ehci, temp, portsc_reg);
mdelay(1);
tries = 100;
do {
mdelay(1);
/*
* Up to this point, Port Enable bit is
* expected to be set after 2 ms waiting.
* USB1 usually takes extra 45 ms, for safety,
* we take 100 ms as timeout.
*/
temp = ehci_readl(ehci, portsc_reg);
} while (!(temp & PORT_PE) && tries--);
if (temp & PORT_PE)
break;
}
if (i == 2)
retval = -ETIMEDOUT;
/*
* Clear Connect Status Change bit if it's set.
* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
*/
if (temp & PORT_CSC)
ehci_writel(ehci, PORT_CSC, portsc_reg);
/*
* Write to clear any interrupt status bits that might be set
* during port reset.
*/
temp = ehci_readl(ehci, &ehci->regs->status);
ehci_writel(ehci, temp, &ehci->regs->status);
/* restore original interrupt enable bits */
ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
return retval;
}
static int tegra_ehci_hub_control(
struct usb_hcd *hcd,
u16 typeReq,
u16 wValue,
u16 wIndex,
char *buf,
u16 wLength
)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
u32 __iomem *status_reg;
u32 temp;
unsigned long flags;
int retval = 0;
status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
spin_lock_irqsave(&ehci->lock, flags);
if (typeReq == GetPortStatus) {
temp = ehci_readl(ehci, status_reg);
if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
/* Resume completed, re-enable disconnect detection */
tegra->port_resuming = 0;
tegra_usb_phy_postresume(tegra->phy);
}
}
else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
temp = ehci_readl(ehci, status_reg);
if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
retval = -EPIPE;
goto done;
}
temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
temp |= PORT_WKDISC_E | PORT_WKOC_E;
ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
/*
* If a transaction is in progress, there may be a delay in
* suspending the port. Poll until the port is suspended.
*/
if (handshake(ehci, status_reg, PORT_SUSPEND,
PORT_SUSPEND, 5000))
pr_err("%s: timeout waiting for SUSPEND\n", __func__);
set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
goto done;
}
/* For USB1 port we need to issue Port Reset twice internally */
if (tegra->phy->instance == 0 &&
(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
spin_unlock_irqrestore(&ehci->lock, flags);
return tegra_ehci_internal_port_reset(ehci, status_reg);
}
/*
* Tegra host controller will time the resume operation to clear the bit
* when the port control state switches to HS or FS Idle. This behavior
* is different from EHCI where the host controller driver is required
* to set this bit to a zero after the resume duration is timed in the
* driver.
*/
else if (typeReq == ClearPortFeature &&
wValue == USB_PORT_FEAT_SUSPEND) {
temp = ehci_readl(ehci, status_reg);
if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
retval = -EPIPE;
goto done;
}
if (!(temp & PORT_SUSPEND))
goto done;
/* Disable disconnect detection during port resume */
tegra_usb_phy_preresume(tegra->phy);
ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
/* start resume signalling */
ehci_writel(ehci, temp | PORT_RESUME, status_reg);
set_bit(wIndex-1, &ehci->resuming_ports);
spin_unlock_irqrestore(&ehci->lock, flags);
msleep(20);
spin_lock_irqsave(&ehci->lock, flags);
/* Poll until the controller clears RESUME and SUSPEND */
if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
pr_err("%s: timeout waiting for RESUME\n", __func__);
if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
pr_err("%s: timeout waiting for SUSPEND\n", __func__);
ehci->reset_done[wIndex-1] = 0;
clear_bit(wIndex-1, &ehci->resuming_ports);
tegra->port_resuming = 1;
goto done;
}
spin_unlock_irqrestore(&ehci->lock, flags);
/* Handle the hub control events here */
return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
done:
spin_unlock_irqrestore(&ehci->lock, flags);
return retval;
}
static int msm_hsic_resume_thread(void *data)
{
struct msm_hsic_hcd *mehci = data;
struct usb_hcd *hcd = hsic_to_hcd(mehci);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
u32 temp;
unsigned long resume_needed = 0;
int retry_cnt = 0;
int tight_resume = 0;
dbg_log_event(NULL, "Resume RH", 0);
/* keep delay between bus states */
if (time_before(jiffies, ehci->next_statechange))
usleep_range(5000, 5000);
spin_lock_irq(&ehci->lock);
if (!HCD_HW_ACCESSIBLE(hcd)) {
spin_unlock_irq(&ehci->lock);
mehci->resume_status = -ESHUTDOWN;
complete(&mehci->rt_completion);
return 0;
}
if (unlikely(ehci->debug)) {
if (!dbgp_reset_prep())
ehci->debug = NULL;
else
dbgp_external_startup();
}
/* at least some APM implementations will try to deliver
* IRQs right away, so delay them until we're ready.
*/
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
/* re-init operational registers */
ehci_writel(ehci, 0, &ehci->regs->segment);
ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
ehci_writel(ehci, (u32) ehci->async->qh_dma, &ehci->regs->async_next);
/*CMD_RUN will be set after, PORT_RESUME gets cleared*/
if (ehci->resume_sof_bug)
ehci->command &= ~CMD_RUN;
/* restore CMD_RUN, framelist size, and irq threshold */
ehci_writel(ehci, ehci->command, &ehci->regs->command);
/* manually resume the ports we suspended during bus_suspend() */
resume_again:
if (retry_cnt >= RESUME_RETRY_LIMIT) {
pr_info("retry count(%d) reached max, resume in tight loop\n",
retry_cnt);
tight_resume = 1;
}
temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
if (test_bit(0, &ehci->bus_suspended) && (temp & PORT_SUSPEND)) {
temp |= PORT_RESUME;
set_bit(0, &resume_needed);
}
dbg_log_event(NULL, "FPR: Set", temp);
ehci_writel(ehci, temp, &ehci->regs->port_status[0]);
/* HSIC controller has a h/w bug due to which it can try to send SOFs
* (start of frames) during port resume resulting in phy lockup. HSIC hw
* controller in MSM clears FPR bit after driving the resume signal for
* 20ms. Workaround is to stop SOFs before driving resume and then start
* sending SOFs immediately. Need to send SOFs within 3ms of resume
* completion otherwise peripheral may enter undefined state. As
* usleep_range does not gurantee exact sleep time, GPTimer is used to
* to time the resume sequence. If driver exceeds allowable time SOFs,
* repeat the resume process.
*/
if (ehci->resume_sof_bug && resume_needed) {
if (!tight_resume) {
mehci->resume_again = 0;
ehci_writel(ehci, GPT_LD(RESUME_SIGNAL_TIME_MS),
&mehci->timer->gptimer0_ld);
ehci_writel(ehci, GPT_RESET | GPT_RUN,
&mehci->timer->gptimer0_ctrl);
ehci_writel(ehci, INTR_MASK | STS_GPTIMER0_INTERRUPT,
&ehci->regs->intr_enable);
ehci_writel(ehci, GPT_LD(RESUME_SIGNAL_TIME_SOF_MS),
&mehci->timer->gptimer1_ld);
ehci_writel(ehci, GPT_RESET | GPT_RUN,
&mehci->timer->gptimer1_ctrl);
spin_unlock_irq(&ehci->lock);
wait_for_completion(&mehci->gpt0_completion);
spin_lock_irq(&ehci->lock);
} else {
dbg_log_event(NULL, "FPR: Tightloop", 0);
/* do the resume in a tight loop */
handshake(ehci, &ehci->regs->port_status[0],
PORT_RESUME, 0, 22 * 1000);
ehci_writel(ehci, ehci_readl(ehci,
&ehci->regs->command) | CMD_RUN,
&ehci->regs->command);
}
if (mehci->resume_again) {
int temp;
dbg_log_event(NULL, "FPR: Re-Resume", retry_cnt);
pr_info("FPR: retry count: %d\n", retry_cnt);
spin_unlock_irq(&ehci->lock);
temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
temp &= ~PORT_RWC_BITS;
temp |= PORT_SUSPEND;
ehci_writel(ehci, temp, &ehci->regs->port_status[0]);
/* Keep the bus idle for 5ms so that peripheral
* can detect and initiate suspend
*/
usleep_range(5000, 5000);
dbg_log_event(NULL,
"FPR: RResume",
ehci_readl(ehci, &ehci->regs->port_status[0]));
spin_lock_irq(&ehci->lock);
mehci->resume_again = 0;
retry_cnt++;
goto resume_again;
}
}
dbg_log_event(NULL, "FPR: RT-Done", 0);
mehci->resume_status = 1;
spin_unlock_irq(&ehci->lock);
complete(&mehci->rt_completion);
return 0;
}
int ehci_vector(void)
{
int ret=0;
u32 flags;
int message=1;
*((volatile u32 *)0x0d80003c ) &= ~(1<<DEV_EHCI); // disable EHCI interrupt
flags=ehci_readl (&ehci->regs->status);
if(working_callback)
{
message= working_callback(flags);
if(((int)message)<=0)
{
working_callback=NULL;
remote_message=message;
int_send_device_message(DEV_EHCI);
//ret=1;
ehci_writel (flags & INTR_MASK, &ehci->regs->status);
}
else
{
ehci_writel (flags & INTR_MASK, &ehci->regs->status);
//temp=ehci_readl( &ehci->regs->command);
*((volatile u32 *)0x0d80003c ) |= 1<<DEV_EHCI;
*((volatile u32 *)0x0d800038 ) |= 1<<DEV_EHCI;
}
}
else
if(passive_callback)
{
passive_callback(flags);
ehci_writel (flags & INTR_MASK, &ehci->regs->status);
*((volatile u32 *)0x0d80003c ) |= 1<<DEV_EHCI;
*((volatile u32 *)0x0d800038 ) |= 1<<DEV_EHCI;
//ret=1; // remote int_send_device_message
}
else
{
ehci_writel (flags & INTR_MASK, &ehci->regs->status);
*((volatile u32 *)0x0d80003c ) |= 1<<DEV_EHCI;
*((volatile u32 *)0x0d800038 ) |= 1<<DEV_EHCI;
//ret=1; // remote int_send_device_message
}
// ret==1: send message to EHCI queue
return ret;
}
