static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = eint_offset(data->irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
if (offs > 15)
return -EINVAL;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
shift = (offs / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P64X0_EINT0CON0);
/* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
if (soc_is_s5p6450())
s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
else
s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
return 0;
}
static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = eint_offset(data->irq);
int pin, pin_val;
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
void __iomem *reg;
if (offs > 27)
return -EINVAL;
if (offs <= 15)
reg = S3C64XX_EINT0CON0;
else
reg = S3C64XX_EINT0CON1;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
if (offs <= 15)
shift = (offs / 2) * 4;
else
shift = ((offs - 16) / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, reg);
/* set the GPIO pin appropriately */
if (offs < 16) {
pin = S3C64XX_GPN(offs);
pin_val = S3C_GPIO_SFN(2);
} else if (offs < 23) {
pin = S3C64XX_GPL(offs + 8 - 16);
pin_val = S3C_GPIO_SFN(3);
} else {
pin = S3C64XX_GPM(offs - 23);
pin_val = S3C_GPIO_SFN(3);
}
s3c_gpio_cfgpin(pin, pin_val);
return 0;
}
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
void __iomem *reg;
if (offs > 27)
return -EINVAL;
/* fixed by jsgood */
if (offs > 15)
reg = S3C64XX_EINT0CON1; /* org: reg = S3C64XX_EINT0CON0; */
else
reg = S3C64XX_EINT0CON0; /* org: reg = S3C64XX_EINT0CON1; */
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
/* fixed by jsgood */
shift = ((offs % 16) / 2) * 4; /* org: shift = (offs / 2) * 4; */
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, reg);
if (offs < 16)
s3c_gpio_cfgpin(S3C64XX_GPN(offs), 0x2 << (offs * 2));
else if (offs < 23)
s3c_gpio_cfgpin(S3C64XX_GPL(offs - 8), S3C_GPIO_SFN(3));
else
s3c_gpio_cfgpin(S3C64XX_GPM(offs - 23), S3C_GPIO_SFN(3));
return 0;
}
static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S5P_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S5P_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S5P_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S5P_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S5P_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5P_EINTCON(eint_conf_reg(irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5P_EINTCON(eint_conf_reg(irq)));
if ((0 <= offs) && (offs < 8))
s3c_gpio_cfgpin(S5P_EXT_INT0(offs&0x7), 0xf<<((offs&0x7)*4));
else if ((8 <= offs) && (offs < 16))
s3c_gpio_cfgpin(S5P_EXT_INT1(offs&0x7), 0xf<<((offs&0x7)*4));
else if ((16 <= offs) && (offs < 24))
s3c_gpio_cfgpin(S5P_EXT_INT2(offs&0x7), 0xf<<((offs&0x7)*4));
else if ((24 <= offs) && (offs < 32))
s3c_gpio_cfgpin(S5P_EXT_INT3(offs&0x7), 0xf<<((offs&0x7)*4));
else
printk(KERN_ERR "No such irq number %d", offs);
return 0;
}
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int pin;
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
void __iomem *reg;
if (offs > 27)
return -EINVAL;
if (offs <= 15)
reg = S3C64XX_EINT0CON0;
else
reg = S3C64XX_EINT0CON1;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
shift = (offs / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, reg);
if (offs < 23)
pin = S3C64XX_GPN(offs);
else
pin = S3C64XX_GPM(offs - 23);
s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
return 0;
}
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
#if 0
int flt_shift;
int target_offset;
flt_shift = (offs & 0x7)*8;
target_offset = flt_shift/32;
flt_shift = flt_shift%32;
ctrl = __raw_readl((S5PC1XX_EINT30FLTCON0+target_offset));
ctrl &= ~(0xff<<flt_shift);
ctrl |= (0x80 | 0x40 | 0x1) << flt_shift; //0x80:filter enable, 0x40:digital filter, 0x1: delay clocks
__raw_writel(ctrl, (S5PC1XX_EINT30FLTCON0+target_offset));
#endif
ctrl = __raw_readl(S5PC1XX_EINTCON(eint_conf_reg(irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5PC1XX_EINTCON(eint_conf_reg(irq)));
#if defined(CONFIG_CPU_S5PC100)
if((0 <= offs) && (offs < 8))
s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0x2<<((offs&0x7)*4));
else if((8 <= offs) && (offs < 16))
s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0x2<<((offs&0x7)*4));
else if((16 <= offs) && (offs < 24))
s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0x2<<((offs&0x7)*4));
else if((24 <= offs) && (offs < 32))
s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0x2<<((offs&0x7)*4));
else
printk(KERN_ERR "No such irq number %d", offs);
#elif defined(CONFIG_CPU_S5PC110)
if((0 <= offs) && (offs < 8))
s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0xf<<((offs&0x7)*4));
else if((8 <= offs) && (offs < 16))
s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0xf<<((offs&0x7)*4));
else if((16 <= offs) && (offs < 24))
s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0xf<<((offs&0x7)*4));
else if((24 <= offs) && (offs < 32))
s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0xf<<((offs&0x7)*4));
else
printk(KERN_ERR "No such irq number %d", offs);
#endif
return 0;
}