int interrupt_init(void) { enable_interrupts(); return 0; }
void x86_unexpected_exception(iframe* frame) { debug_exception_type type; uint32 signalNumber; int32 signalCode; addr_t signalAddress = 0; int32 signalError = B_ERROR; switch (frame->vector) { case 0: // Divide Error Exception (#DE) type = B_DIVIDE_ERROR; signalNumber = SIGFPE; signalCode = FPE_INTDIV; signalAddress = frame->ip; break; case 4: // Overflow Exception (#OF) type = B_OVERFLOW_EXCEPTION; signalNumber = SIGFPE; signalCode = FPE_INTOVF; signalAddress = frame->ip; break; case 5: // BOUND Range Exceeded Exception (#BR) type = B_BOUNDS_CHECK_EXCEPTION; signalNumber = SIGTRAP; signalCode = SI_USER; break; case 6: // Invalid Opcode Exception (#UD) type = B_INVALID_OPCODE_EXCEPTION; signalNumber = SIGILL; signalCode = ILL_ILLOPC; signalAddress = frame->ip; break; case 13: // General Protection Exception (#GP) type = B_GENERAL_PROTECTION_FAULT; signalNumber = SIGILL; signalCode = ILL_PRVOPC; // or ILL_PRVREG signalAddress = frame->ip; break; case 16: // x87 FPU Floating-Point Error (#MF) type = B_FLOATING_POINT_EXCEPTION; signalNumber = SIGFPE; signalCode = FPE_FLTDIV; // TODO: Determine the correct cause via the FPU status // register! signalAddress = frame->ip; break; case 17: // Alignment Check Exception (#AC) type = B_ALIGNMENT_EXCEPTION; signalNumber = SIGBUS; signalCode = BUS_ADRALN; // TODO: Also get the address (from where?). Since we don't enable // alignment checking this exception should never happen, though. signalError = EFAULT; break; case 19: // SIMD Floating-Point Exception (#XF) type = B_FLOATING_POINT_EXCEPTION; signalNumber = SIGFPE; signalCode = FPE_FLTDIV; // TODO: Determine the correct cause via the MXCSR register! signalAddress = frame->ip; break; default: x86_invalid_exception(frame); return; } if (IFRAME_IS_USER(frame)) { struct sigaction action; Thread* thread = thread_get_current_thread(); enable_interrupts(); // If the thread has a signal handler for the signal, we simply send it // the signal. Otherwise we notify the user debugger first. if ((sigaction(signalNumber, NULL, &action) == 0 && action.sa_handler != SIG_DFL && action.sa_handler != SIG_IGN) || user_debug_exception_occurred(type, signalNumber)) { Signal signal(signalNumber, signalCode, signalError, thread->team->id); signal.SetAddress((void*)signalAddress); send_signal_to_thread(thread, signal, 0); } } else { char name[32]; panic("Unexpected exception \"%s\" occurred in kernel mode! " "Error code: 0x%lx\n", exception_name(frame->vector, name, sizeof(name)), frame->error_code); } }
int cache_post_test (int flags) { void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR; int ints; int res = 0; int tlb = -1; /* index to the victim TLB entry */ /* * All 44x variants deal with cache management differently * because they have the address translation always enabled. * The 40x ppc's don't use address translation in U-Boot at all, * so we have to distinguish here between 40x and 44x. */ #ifdef CONFIG_440 int word0, i; /* * Allocate a new TLB entry, since we are going to modify * the write-through and caching inhibited storage attributes. */ program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE, TLB_WORD2_I_ENABLE); /* Find the TLB entry */ for (i = 0;; i++) { if (i >= PPC4XX_TLB_SIZE) { printf ("Failed to program tlb entry\n"); return -1; } word0 = mftlb1(i); if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { tlb = i; break; } } #endif ints = disable_interrupts (); WATCHDOG_RESET (); if (res == 0) res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE); if (ints) enable_interrupts (); #ifdef CONFIG_440 remove_tlb((u32)virt, CACHE_POST_SIZE); #endif return res; }
extern "C" int _start(kernel_args *bootKernelArgs, int currentCPU) { if (bootKernelArgs->kernel_args_size != sizeof(kernel_args) || bootKernelArgs->version != CURRENT_KERNEL_ARGS_VERSION) { // This is something we cannot handle right now - release kernels // should always be able to handle the kernel_args of earlier // released kernels. debug_early_boot_message("Version mismatch between boot loader and " "kernel!\n"); return -1; } smp_set_num_cpus(bootKernelArgs->num_cpus); // wait for all the cpus to get here smp_cpu_rendezvous(&sCpuRendezvous, currentCPU); // the passed in kernel args are in a non-allocated range of memory if (currentCPU == 0) memcpy(&sKernelArgs, bootKernelArgs, sizeof(kernel_args)); smp_cpu_rendezvous(&sCpuRendezvous2, currentCPU); // do any pre-booting cpu config cpu_preboot_init_percpu(&sKernelArgs, currentCPU); thread_preboot_init_percpu(&sKernelArgs, currentCPU); // if we're not a boot cpu, spin here until someone wakes us up if (smp_trap_non_boot_cpus(currentCPU, &sCpuRendezvous3)) { // init platform arch_platform_init(&sKernelArgs); // setup debug output debug_init(&sKernelArgs); set_dprintf_enabled(true); dprintf("Welcome to kernel debugger output!\n"); dprintf("Haiku revision: %s\n", get_haiku_revision()); // init modules TRACE("init CPU\n"); cpu_init(&sKernelArgs); cpu_init_percpu(&sKernelArgs, currentCPU); TRACE("init interrupts\n"); int_init(&sKernelArgs); TRACE("init VM\n"); vm_init(&sKernelArgs); // Before vm_init_post_sem() is called, we have to make sure that // the boot loader allocated region is not used anymore boot_item_init(); debug_init_post_vm(&sKernelArgs); low_resource_manager_init(); // now we can use the heap and create areas arch_platform_init_post_vm(&sKernelArgs); lock_debug_init(); TRACE("init driver_settings\n"); driver_settings_init(&sKernelArgs); debug_init_post_settings(&sKernelArgs); TRACE("init notification services\n"); notifications_init(); TRACE("init teams\n"); team_init(&sKernelArgs); TRACE("init ELF loader\n"); elf_init(&sKernelArgs); TRACE("init modules\n"); module_init(&sKernelArgs); TRACE("init semaphores\n"); haiku_sem_init(&sKernelArgs); TRACE("init interrupts post vm\n"); int_init_post_vm(&sKernelArgs); cpu_init_post_vm(&sKernelArgs); commpage_init(); TRACE("init system info\n"); system_info_init(&sKernelArgs); TRACE("init SMP\n"); smp_init(&sKernelArgs); TRACE("init timer\n"); timer_init(&sKernelArgs); TRACE("init real time clock\n"); rtc_init(&sKernelArgs); timer_init_post_rtc(); TRACE("init condition variables\n"); condition_variable_init(); // now we can create and use semaphores TRACE("init VM semaphores\n"); vm_init_post_sem(&sKernelArgs); TRACE("init generic syscall\n"); generic_syscall_init(); smp_init_post_generic_syscalls(); TRACE("init scheduler\n"); scheduler_init(); TRACE("init threads\n"); thread_init(&sKernelArgs); TRACE("init kernel daemons\n"); kernel_daemon_init(); arch_platform_init_post_thread(&sKernelArgs); TRACE("init I/O interrupts\n"); int_init_io(&sKernelArgs); TRACE("init VM threads\n"); vm_init_post_thread(&sKernelArgs); low_resource_manager_init_post_thread(); TRACE("init DPC\n"); dpc_init(); TRACE("init VFS\n"); vfs_init(&sKernelArgs); #if ENABLE_SWAP_SUPPORT TRACE("init swap support\n"); swap_init(); #endif TRACE("init POSIX semaphores\n"); realtime_sem_init(); xsi_sem_init(); xsi_msg_init(); // Start a thread to finish initializing the rest of the system. Note, // it won't be scheduled before calling scheduler_start() (on any CPU). TRACE("spawning main2 thread\n"); thread_id thread = spawn_kernel_thread(&main2, "main2", B_NORMAL_PRIORITY, NULL); resume_thread(thread); // We're ready to start the scheduler and enable interrupts on all CPUs. scheduler_enable_scheduling(); // bring up the AP cpus in a lock step fashion TRACE("waking up AP cpus\n"); sCpuRendezvous = sCpuRendezvous2 = 0; smp_wake_up_non_boot_cpus(); smp_cpu_rendezvous(&sCpuRendezvous, 0); // wait until they're booted // exit the kernel startup phase (mutexes, etc work from now on out) TRACE("exiting kernel startup\n"); gKernelStartup = false; smp_cpu_rendezvous(&sCpuRendezvous2, 0); // release the AP cpus to go enter the scheduler TRACE("starting scheduler on cpu 0 and enabling interrupts\n"); scheduler_start(); enable_interrupts(); } else { // lets make sure we're in sync with the main cpu // the boot processor has probably been sending us // tlb sync messages all along the way, but we've // been ignoring them arch_cpu_global_TLB_invalidate(); // this is run for each non boot processor after they've been set loose cpu_init_percpu(&sKernelArgs, currentCPU); smp_per_cpu_init(&sKernelArgs, currentCPU); // wait for all other AP cpus to get to this point smp_cpu_rendezvous(&sCpuRendezvous, currentCPU); smp_cpu_rendezvous(&sCpuRendezvous2, currentCPU); // welcome to the machine scheduler_start(); enable_interrupts(); } #ifdef TRACE_BOOT // We disable interrupts for this dprintf(), since otherwise dprintf() // would acquires a mutex, which is something we must not do in an idle // thread, or otherwise the scheduler would be seriously unhappy. disable_interrupts(); TRACE("main: done... begin idle loop on cpu %d\n", currentCPU); enable_interrupts(); #endif for (;;) arch_cpu_idle(); return 0; }
int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong iflag; ulong load_end = 0; int ret; boot_os_fn *boot_fn; #ifdef CONFIG_NEEDS_MANUAL_RELOC static int relocated = 0; /* relocate boot function table */ if (!relocated) { int i; for (i = 0; i < ARRAY_SIZE(boot_os); i++) if (boot_os[i] != NULL) boot_os[i] += gd->reloc_off; relocated = 1; } #endif /* determine if we have a sub command */ if (argc > 1) { char *endp; simple_strtoul(argv[1], &endp, 16); /* endp pointing to NULL means that argv[1] was just a * valid number, pass it along to the normal bootm processing * * If endp is ':' or '#' assume a FIT identifier so pass * along for normal processing. * * Right now we assume the first arg should never be '-' */ if ((*endp != 0) && (*endp != ':') && (*endp != '#')) return do_bootm_subcommand(cmdtp, flag, argc, argv); } if (bootm_start(cmdtp, flag, argc, argv)) return 1; /* * We have reached the point of no return: we are going to * overwrite all exception vector code, so we cannot easily * recover from any failures any more... */ iflag = disable_interrupts(); #if defined(CONFIG_CMD_USB) /* * turn off USB to prevent the host controller from writing to the * SDRAM while Linux is booting. This could happen (at least for OHCI * controller), because the HCCA (Host Controller Communication Area) * lies within the SDRAM and the host controller writes continously to * this area (as busmaster!). The HccaFrameNumber is for example * updated every 1 ms within the HCCA structure in SDRAM! For more * details see the OpenHCI specification. */ usb_stop(); #endif ret = bootm_load_os(images.os, &load_end, 1); if (ret < 0) { if (ret == BOOTM_ERR_RESET) do_reset (cmdtp, flag, argc, argv); if (ret == BOOTM_ERR_OVERLAP) { if (images.legacy_hdr_valid) { if (image_get_type (&images.legacy_hdr_os_copy) == IH_TYPE_MULTI) puts ("WARNING: legacy format multi component " "image overwritten\n"); } else { puts ("ERROR: new format image overwritten - " "must RESET the board to recover\n"); show_boot_progress (-113); do_reset (cmdtp, flag, argc, argv); } } if (ret == BOOTM_ERR_UNIMPLEMENTED) { if (iflag) enable_interrupts(); show_boot_progress (-7); return 1; } } lmb_reserve(&images.lmb, images.os.load, (load_end - images.os.load)); if (images.os.type == IH_TYPE_STANDALONE) { if (iflag) enable_interrupts(); /* This may return when 'autostart' is 'no' */ bootm_start_standalone(iflag, argc, argv); return 0; } show_boot_progress (8); #ifdef CONFIG_SILENT_CONSOLE if (images.os.os == IH_OS_LINUX) fixup_silent_linux(); #endif boot_fn = boot_os[images.os.os]; if (boot_fn == NULL) { if (iflag) enable_interrupts(); printf ("ERROR: booting os '%s' (%d) is not supported\n", genimg_get_os_name(images.os.os), images.os.os); show_boot_progress (-8); return 1; } arch_preboot_os(); boot_fn(0, argc, argv, &images); show_boot_progress (-9); #ifdef DEBUG puts ("\n## Control returned to monitor - resetting...\n"); #endif do_reset (cmdtp, flag, argc, argv); return 1; }
/* reads data from FDC, seek commands are issued automatic */ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) { /* first seek to start address */ unsigned long len,lastblk,readblk,i,timeout,ii,offset; unsigned char pcn,c,retriesrw,retriescal; unsigned char *bufferw; /* working buffer */ int sect_size; int flags; flags=disable_interrupts(); /* switch off all Interrupts */ select_fdc_drive(pCMD); /* switch on drive */ sect_size=0x080<<pFG->sect_code; retriesrw=0; retriescal=0; offset=0; if(fdc_seek(pCMD,pFG)==FALSE) { stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } if((pCMD->result[STATUS_0]&0x20)!=0x20) { printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]); stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } pcn=pCMD->result[STATUS_PCN]; /* current track */ /* now determine the next seek point */ lastblk=pCMD->blnr + blocks; /* readblk=(pFG->head*pFG->sect)-(pCMD->blnr%(pFG->head*pFG->sect)); */ readblk=pFG->sect-(pCMD->blnr%pFG->sect); PRINTF("1st nr of block possible read %ld start %ld\n",readblk,pCMD->blnr); if(readblk>blocks) /* is end within 1st track */ readblk=blocks; /* yes, correct it */ PRINTF("we read %ld blocks start %ld\n",readblk,pCMD->blnr); bufferw = &buffer[0]; /* setup working buffer */ do { retryrw: len=sect_size * readblk; pCMD->cmd[COMMAND]=FDC_CMD_READ; if(fdc_issue_cmd(pCMD,pFG)==FALSE) { stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } for (i=0;i<len;i++) { timeout=FDC_TIME_OUT; do { c=read_fdc_reg(FDC_MSR); if((c&0xC0)==0xC0) { bufferw[i]=read_fdc_reg(FDC_FIFO); break; } if((c&0xC0)==0x80) { /* output */ PRINTF("Transfer error transfered: at %ld, MSR=%02X\n",i,c); if(i>6) { for(ii=0;ii<7;ii++) { pCMD->result[ii]=bufferw[(i-7+ii)]; } /* for */ } if(retriesrw++>FDC_RW_RETRIES) { if (retriescal++>FDC_CAL_RETRIES) { stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } else { PRINTF(" trying to recalibrate Try %d\n",retriescal); if(fdc_recalibrate(pCMD,pFG)==FALSE) { stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } retriesrw=0; goto retrycal; } /* else >FDC_CAL_RETRIES */ } else { PRINTF("Read retry %d\n",retriesrw); goto retryrw; } /* else >FDC_RW_RETRIES */ }/* if output */ timeout--; }while(TRUE); } /* for len */ /* the last sector of a track or all data has been read, * we need to get the results */ fdc_terminate(pCMD); offset+=(sect_size*readblk); /* set up buffer pointer */ bufferw = &buffer[offset]; pCMD->blnr+=readblk; /* update current block nr */ blocks-=readblk; /* update blocks */ if(blocks==0) break; /* we are finish */ /* setup new read blocks */ /* readblk=pFG->head*pFG->sect; */ readblk=pFG->sect; if(readblk>blocks) readblk=blocks; retrycal: /* a seek is necessary */ if(fdc_seek(pCMD,pFG)==FALSE) { stop_fdc_drive(pCMD); enable_interrupts(); return FALSE; } if((pCMD->result[STATUS_0]&0x20)!=0x20) { PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]); stop_fdc_drive(pCMD); return FALSE; } pcn=pCMD->result[STATUS_PCN]; /* current track */ }while(TRUE); /* start over */ stop_fdc_drive(pCMD); /* switch off drive */ enable_interrupts(); return TRUE; }
void board_init_r(gd_t *id, ulong dest_addr) { ulong malloc_start; #if !defined(CONFIG_SYS_NO_FLASH) ulong flash_size; #endif gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); monitor_flash_len = _end_ofs; /* Enable caches */ enable_caches(); debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ /* * TODO: printing of the clock inforamtion of the board is now * implemented as part of bdinfo command. Currently only support for * davinci SOC's is added. Remove this check once all the board * implement this. */ #ifdef CONFIG_CLOCKS set_cpu_clk_info(); /* Setup clock information */ #endif serial_initialize(); debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); #ifdef CONFIG_LOGBUFFER logbuff_init_ptrs(); #endif #ifdef CONFIG_POST post_output_backlog(); #endif /* The Malloc area is immediately below the monitor copy in DRAM */ malloc_start = dest_addr - TOTAL_MALLOC_LEN; mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); #ifdef CONFIG_ARCH_EARLY_INIT_R arch_early_init_r(); #endif power_init_board(); #if !defined(CONFIG_SYS_NO_FLASH) puts("Flash: "); flash_size = flash_init(); if (flash_size > 0) { # ifdef CONFIG_SYS_FLASH_CHECKSUM print_size(flash_size, ""); /* * Compute and print flash CRC if flashchecksum is set to 'y' * * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX */ if (getenv_yesno("flashchecksum") == 1) { printf(" CRC: %08X", crc32(0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)); } putc('\n'); # else /* !CONFIG_SYS_FLASH_CHECKSUM */ print_size(flash_size, "\n"); # endif /* CONFIG_SYS_FLASH_CHECKSUM */ } else { puts("0 Mib\n"); // hang(); } #endif #if defined(CONFIG_CMD_NAND) puts("NAND: "); nand_init(); /* go init the NAND */ #endif #if defined(CONFIG_CMD_ONENAND) onenand_init(); #endif #ifdef CONFIG_GENERIC_MMC puts("MMC: "); mmc_initialize(gd->bd); #endif #ifdef CONFIG_HAS_DATAFLASH AT91F_DataflashInit(); dataflash_print_info(); #endif /* initialize environment */ if (should_load_env()) env_relocate(); else set_default_env(NULL); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) arm_pci_init(); #endif stdio_init(); /* get the devices list going. */ jumptable_init(); #if defined(CONFIG_API) /* Initialize API */ api_init(); #endif console_init_r(); /* fully init console as a device */ #ifdef CONFIG_DISPLAY_BOARDINFO_LATE # ifdef CONFIG_OF_CONTROL /* Put this here so it appears on the LCD, now it is ready */ display_fdt_model(gd->fdt_blob); # else checkboard(); # endif #endif #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init(); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r(); #endif /* set up exceptions */ interrupt_init(); /* enable exceptions */ enable_interrupts(); /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); #ifdef CONFIG_BOARD_LATE_INIT board_late_init(); #endif #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) puts("Net: "); eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) debug("Reset Ethernet PHY\n"); reset_phy(); #endif #endif #ifdef CONFIG_POST post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) /* * Export available size of memory for Linux, * taking into account the protected RAM at top of memory */ { ulong pram = 0; uchar memsz[32]; #ifdef CONFIG_PRAM pram = getenv_ulong("pram", 10, CONFIG_PRAM); #endif #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram); setenv("mem", (char *)memsz); } #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { main_loop(); /* commom/main.c */ } /* NOTREACHED - no way out of command loop except booting */ }
void main() { UBYTE i, j; disable_interrupts(); DISPLAY_OFF; LCDC_REG = 0x67; /* * LCD = Off * WindowBank = 0x9C00 * Window = On * BG Chr = 0x8800 * BG Bank = 0x9800 * OBJ = 8x16 * OBJ = On * BG = On */ doorstate = CLOSED; /* Set palettes */ BGP_REG = OBP0_REG = OBP1_REG = 0xE4U; /* Initialize the background */ set_bkg_data(0xFC, 0x04, std_data); set_bkg_data(0x00, 0x2D, bkg_data); /* * Draw the background * * Width = 0x100 = 0x20 * 8 * Height = 0x100 = 0x20 * 8 */ for(i = 0; i < 32; i+=8) for(j = 0; j < 32; j+=8) set_bkg_tiles(i, j, 8, 8, bkg_tiles); bposx.w = 0; SCX_REG = 0; bposy.w = 0; SCY_REG = 0; bspx.w = 0xFF00; bspy.w = 0x0080; /* Initialize the window */ set_win_data(0x80, 0x21, frame_data); /* * Draw the frame in the window * * Width = 0x80 = 0x10 * 8 * Height = 0x50 = 0x0A * 8 */ set_win_tiles(0, 0, 16, 10, frame_tiles); /* * Draw the door in the window * * Width = 0x60 = 0x20 * 12 * Height = 0x30 = 0x20 * 6 */ set_win_tiles(2, 2, 12, 6, door1_tiles); wposx.b.h = MAXWNDPOSX; wposx.b.l = 0; WX_REG = MAXWNDPOSX; wposy.b.h = MAXWNDPOSY; wposy.b.l = 0; WY_REG = MAXWNDPOSY; wspx.w = 0xFF80; wspy.w = 0xFFC0; /* Initialize the sprite */ set_sprite_data(0x00, 0x1C, earth_data); set_sprite_prop(0, 0x00); set_sprite_prop(1, 0x00); sframe = 0; sposx.w = 0x1000; sposy.w = 0x1000; sspx.w = 0x0040; sspy.w = 0x0040; tile_sprite(); place_sprite(); DISPLAY_ON; enable_interrupts(); while(1) { /* Skip four VBLs (slow down animation) */ for(i = 0; i < 4; i++) wait_vbl_done(); time++; fade(); door(); scroll(); animate_sprite(); i = joypad(); if(i & J_B) { if(i & J_UP) bspy.w -= 0x0010; if(i & J_DOWN) bspy.w += 0x0010; if(i & J_LEFT) bspx.w -= 0x0010; if(i & J_RIGHT) bspx.w += 0x0010; } else if(i & J_A) { if(i & J_UP) wspy.w -= 0x0010; if(i & J_DOWN) wspy.w += 0x0010; if(i & J_LEFT) wspx.w -= 0x0010; if(i & J_RIGHT) wspx.w += 0x0010; } else { if(i & J_SELECT) color = STARTFADE; if(i & J_START) if(doorstate == CLOSED) { doorstate = OPENING; doorpos = 0; } else if(doorstate == OPENED) { doorstate = CLOSING; doorpos = NBDFRAMES; } if(i & J_UP) sspy.w -= 0x0010; if(i & J_DOWN) sspy.w += 0x0010; if(i & J_LEFT) sspx.w -= 0x0010; if(i & J_RIGHT) sspx.w += 0x0010; } } }
/** * Execute selected states of the bootm command. * * Note the arguments to this state must be the first argument, Any 'bootm' * or sub-command arguments must have already been taken. * * Note that if states contains more than one flag it MUST contain * BOOTM_STATE_START, since this handles and consumes the command line args. * * Also note that aside from boot_os_fn functions and bootm_load_os no other * functions we store the return value of in 'ret' may use a negative return * value, without special handling. * * @param cmdtp Pointer to bootm command table entry * @param flag Command flags (CMD_FLAG_...) * @param argc Number of subcommand arguments (0 = no arguments) * @param argv Arguments * @param states Mask containing states to run (BOOTM_STATE_...) * @param images Image header information * @param boot_progress 1 to show boot progress, 0 to not do this * @return 0 if ok, something else on error. Some errors will cause this * function to perform a reboot! If states contains BOOTM_STATE_OS_GO * then the intent is to boot an OS, so this function will not return * unless the image type is standalone. */ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int states, bootm_headers_t *images, int boot_progress) { boot_os_fn *boot_fn; ulong iflag = 0; int ret = 0, need_boot_fn; images->state |= states; /* * Work through the states and see how far we get. We stop on * any error. */ if (states & BOOTM_STATE_START) ret = bootm_start(cmdtp, flag, argc, argv); if (!ret && (states & BOOTM_STATE_FINDOS)) ret = bootm_find_os(cmdtp, flag, argc, argv); if (!ret && (states & BOOTM_STATE_FINDOTHER)) { ret = bootm_find_other(cmdtp, flag, argc, argv); argc = 0; /* consume the args */ } /* Load the OS */ if (!ret && (states & BOOTM_STATE_LOADOS)) { ulong load_end; iflag = bootm_disable_interrupts(); ret = bootm_load_os(images, &load_end, 0); if (ret == 0) lmb_reserve(&images->lmb, images->os.load, (load_end - images->os.load)); else if (ret && ret != BOOTM_ERR_OVERLAP) goto err; else if (ret == BOOTM_ERR_OVERLAP) ret = 0; #if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) if (images->os.os == IH_OS_LINUX) fixup_silent_linux(); #endif } /* Relocate the ramdisk */ #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH if (!ret && (states & BOOTM_STATE_RAMDISK)) { ulong rd_len = images->rd_end - images->rd_start; ret = boot_ramdisk_high(&images->lmb, images->rd_start, rd_len, &images->initrd_start, &images->initrd_end); if (!ret) { setenv_hex("initrd_start", images->initrd_start); setenv_hex("initrd_end", images->initrd_end); } } #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB) if (!ret && (states & BOOTM_STATE_FDT)) { boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, &images->ft_len); } #endif /* From now on, we need the OS boot function */ if (ret) return ret; boot_fn = bootm_os_get_boot_func(images->os.os); need_boot_fn = states & (BOOTM_STATE_OS_CMDLINE | BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO); if (boot_fn == NULL && need_boot_fn) { if (iflag) enable_interrupts(); printf("ERROR: booting os '%s' (%d) is not supported\n", genimg_get_os_name(images->os.os), images->os.os); bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS); return 1; } /* Call various other states that are not generally used */ if (!ret && (states & BOOTM_STATE_OS_CMDLINE)) ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images); if (!ret && (states & BOOTM_STATE_OS_BD_T)) ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images); if (!ret && (states & BOOTM_STATE_OS_PREP)) ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images); #ifdef CONFIG_TRACE /* Pretend to run the OS, then run a user command */ if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) { char *cmd_list = getenv("fakegocmd"); ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO, images, boot_fn); if (!ret && cmd_list) ret = run_command_list(cmd_list, -1, flag); } #endif /* Check for unsupported subcommand. */ if (ret) { puts("subcommand not supported\n"); return ret; } /* Now run the OS! We hope this doesn't return */ if (!ret && (states & BOOTM_STATE_OS_GO)) ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO, images, boot_fn); /* Deal with any fallout */ err: if (iflag) enable_interrupts(); if (ret == BOOTM_ERR_UNIMPLEMENTED) bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL); else if (ret == BOOTM_ERR_RESET) do_reset(cmdtp, flag, argc, argv); return ret; }
void watchdog_reset(void) { int re_enable = disable_interrupts(); reset_4xx_watchdog(); if (re_enable) enable_interrupts(); }
int flash_erase(flash_info_t *info, int s_first, int s_last) { vu_char *caddr = (vu_char *)(info->start[0]); vu_char *caddr_s; int flag, prot, sect; int rc; if (info->flash_id == FLASH_UNKNOWN) { printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); return (ERR_UNKNOWN_FLASH_TYPE); } if ((s_first < 0) || (s_first > s_last)) { printf("- No sectors to erase\n"); return (ERR_INVAL); } prot = 0; for (sect = s_first; sect <= s_last; ++sect) { if (info->protect[sect]) { prot++; } } if (prot) { printf("- Warning: %d protected sectors will not be erased\n", prot); } else { printf("\n"); } /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ caddr_s = (vu_char *)(info->start[sect]); printf("Erasing sector %2d @ %08lX... ", sect, info->start[sect]); caddr[0xAAA] = 0xAA; caddr[0x555] = 0x55; caddr[0xAAA] = 0x80; caddr[0xAAA] = 0xAA; caddr[0x555] = 0x55; caddr_s[0] = 0x30; reset_timer_masked(); rc = ERR_OK; do { u8 result; if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { rc = ERR_TIMOUT; break; } result = caddr_s[0]; if (result & 0x80) { break; } if (result & 0x20) { rc = ERR_PROG_ERROR; break; } } while (!rc); caddr[0xAAA] = 0x0F; if (rc == ERR_OK) { printf("OK\n"); } else { printf("Failed"); return (rc); } } } /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* reset to read mode */ caddr = (vu_char *)info->start[0]; caddr[0] = 0xF0; /* reset bank */ udelay_masked(10000); return (ERR_OK); }
int main(void) { /* Early system initialisation */ early_board_init(); system_init_early(); leds_init(); set_busy_led(1); set_dirty_led(0); /* Due to an erratum in the LPC17xx chips anything that may change */ /* peripheral clock scalers must come before system_init_late() */ uart_init(); #ifndef SPI_LATE_INIT spi_init(SPI_SPEED_SLOW); #endif timer_init(); i2c_init(); /* Second part of system initialisation, switches to full speed on ARM */ system_init_late(); enable_interrupts(); /* Prompt software name and version string */ uart_puts_P(PSTR("\r\nNODISKEMU " VERSION "\r\n")); /* Internal-only initialisation, called here because it's faster */ buffers_init(); buttons_init(); /* Anything that does something which needs the system clock */ /* should be placed after system_init_late() */ rtc_init(); // accesses I2C disk_init(); // accesses card read_configuration(); // restores configuration, may change device address filesystem_init(0); // FIXME: change_init(); #ifdef CONFIG_REMOTE_DISPLAY /* at this point all buffers should be free, */ /* so just use the data area of the first to build the string */ uint8_t *strbuf = buffers[0].data; ustrcpy_P(strbuf, versionstr); ustrcpy_P(strbuf+ustrlen(strbuf), longverstr); if (display_init(ustrlen(strbuf), strbuf)) { display_address(device_address); display_current_part(0); } #endif set_busy_led(0); #if defined(HAVE_SD) /* card switch diagnostic aid - hold down PREV button to use */ if (menu_system_enabled && get_key_press(KEY_PREV)) board_diagnose(); #endif if (menu_system_enabled) lcd_splashscreen(); bus_interface_init(); bus_init(); read_configuration(); late_board_init(); for (;;) { if (menu_system_enabled) lcd_refresh(); else { lcd_clear(); lcd_printf("#%d", device_address); } /* Unit number may depend on hardware and stored settings */ /* so present it here at last */ printf("#%02d\r\n", device_address); bus_mainloop(); bus_interface_init(); bus_init(); // needs delay, inits device address with HW settings } }
int main(void) { // Disable, configure, and start the watchdog timer iwdg_reset(); iwdg_set_period_ms(8000); iwdg_start(); // Start and configure all hardware peripherals enable_interrupts(); led_init(); //radio_init(); gps_init(); eeprom_init(); //radio_enable(); // Set the radio shift and baud rate //_radio_dac_write(RADIO_COARSE, RADIO_CENTER_FREQ); //_radio_dac_write(RADIO_FINE, 0); //radio_set_shift(RADIO_SHIFT_425); //radio_set_baud(RADIO_BAUD_50); // Radio chatter for(uint8_t i = 0; i < 5; i++) { //radio_chatter(); iwdg_reset(); } int32_t lat = 0, lon = 0, alt = 0; uint8_t hour = 0, minute = 0, second = 0, lock = 0, sats = 0; while(true) { led_set(LED_GREEN, 1); // Get the current system tick and increment uint32_t tick; eeprom_read_dword(ticks_addr, &tick); tick += 1; // Check that we're in airborne <1g mode if( gps_check_nav() != 0x06 ) led_set(LED_RED, 1); // Get information from the GPS gps_check_lock(&lock, &sats); if( lock == 0x02 || lock == 0x03 || lock == 0x04 ) { gps_get_position(&lat, &lon, &alt); gps_get_time(&hour, &minute, &second); } led_set(LED_GREEN, 0); // Format the telemetry string & transmit double lat_fmt = (double)lat / 10000000.0; double lon_fmt = (double)lon / 10000000.0; alt /= 1000; sprintf(s, "$$" CALLSIGN ",%lu,%02u:%02u:%02u,%02.7f,%03.7f,%ld,%u,%x", tick, hour, minute, second, lat_fmt, lon_fmt, alt, sats, lock); //radio_chatter(); //radio_transmit_sentence(s); //radio_chatter(); led_set(LED_RED, 0); eeprom_write_dword(ticks_addr, tick); iwdg_reset(); //_delay_ms(500); } return 0; }
void main(void) { //char c; signed char length; unsigned char msgtype; unsigned char last_reg_recvd; uart_comm uc; i2c_comm ic; unsigned char msgbuffer[MSGLEN + 1]; // unsigned char to_send_buffer[MAX_I2C_SENSOR_DATA_LEN + HEADER_MEMBERS]; // uint8 to_send_len; // int data_points_count = 0; //unsigned char i; //uart_thread_struct uthread_data; // info for uart_lthread //timer1_thread_struct t1thread_data; // info for timer1_lthread //timer0_thread_struct t0thread_data; // info for timer0_lthread #ifdef __USE18F2680 OSCCON = 0xFC; // see datasheet // We have enough room below the Max Freq to enable the PLL for this chip OSCTUNEbits.PLLEN = 1; // 4x the clock speed in the previous line #else #ifdef __USE18F45J10 OSCCON = 0x82; // see datasheeet OSCTUNEbits.PLLEN = 0; // Makes the clock exceed the PIC's rated speed if the PLL is on #else #ifdef __USE18F26J50 OSCCON = 0xE0; // see datasheeet OSCTUNEbits.PLLEN = 1; #else #ifdef __USE18F46J50 OSCCON = 0xE0; //see datasheet OSCTUNEbits.PLLEN = 1; #else Something is messed up. The PIC selected is not supported or the preprocessor directives are wrong. #endif #endif #endif #endif // initialize my uart recv handling code init_uart_recv(&uc); // initialize the i2c code init_i2c(&ic); // init the timer1 lthread // init_timer1_lthread(&t1thread_data); // initialize message queues before enabling any interrupts init_queues(); #ifndef __USE18F26J50 // set direction for PORTB to output #ifndef MOTOR_PIC TRISB = 0x0; LATB = 0x0; #else TRISBbits.RB0 = 0; TRISBbits.RB1 = 0; TRISBbits.RB2 = 0; TRISBbits.RB3 = 0; #endif #endif // how to set up PORTA for input (for the V4 board with the PIC2680) /* PORTA = 0x0; // clear the port LATA = 0x0; // clear the output latch ADCON1 = 0x0F; // turn off the A2D function on these pins // Only for 40-pin version of this chip CMCON = 0x07; // turn the comparator off TRISA = 0x0F; // set RA3-RA0 to inputs */ // initialize Timers #ifndef MASTER_PIC #ifdef SENSOR_PIC OpenTimer0(TIMER_INT_ON & T0_16BIT & T0_SOURCE_INT & T0_PS_1_16); INTCONbits.T0IE = 1; #elif !defined(MOTOR_PIC) OpenTimer0(TIMER_INT_ON & T0_16BIT & T0_SOURCE_INT & T0_PS_1_4); #else OpenTimer0(TIMER_INT_ON & T0_8BIT & T0_PS_1_1 & T0_SOURCE_EXT); #endif #else OpenTimer0(TIMER_INT_ON & T0_16BIT & T0_SOURCE_INT & T0_PS_1_16); #endif #ifdef __USE18F26J50 // MTJ added second argument for OpenTimer1() OpenTimer1(TIMER_INT_ON & T1_SOURCE_FOSC_4 & T1_PS_1_8 & T1_16BIT_RW & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF, 0x0); #else #ifdef __USE18F46J50 //OpenTimer1(TIMER_INT_ON & T1_SOURCE_FOSC_4 & T1_PS_1_8 & T1_16BIT_RW & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF, 0x0); #else #ifndef MOTOR_PIC // OpenTimer1(TIMER_INT_ON & T1_PS_1_8 & T1_16BIT_RW & T1_SOURCE_INT & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF); #else OpenTimer1(TIMER_INT_ON & T1_PS_1_1 & T1_16BIT_RW & T1_SOURCE_EXT & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF); WRITETIMER1(0xFFE8); // leave in here, encoder's for motor 2 doesn't work without it #endif #endif #endif // Decide on the priority of the enabled peripheral interrupts // 0 is low, 1 is high //Timer0 interrupt INTCON2bits.TMR0IP = 1; // Timer1 interrupt #ifdef SENSOR_PIC // IPR1bits.TMR1IP = 0; #else IPR1bits.TMR1IP = 1; #endif // USART RX interrupt IPR1bits.RCIP = 0; IPR1bits.TXIP = 0; // I2C interrupt IPR1bits.SSPIP = 1; //set i2c int high PIE1bits.SSPIE = 1; #ifdef SENSOR_PIC //resetAccumulators(); init_adc(); initUS(); // must specifically enable the I2C interrupts IPR1bits.ADIP = 0; // configure the hardware i2c device as a slave (0x9E -> 0x4F) or (0x9A -> 0x4D) i2c_configure_slave(SENSOR_ADDR << 1); //address 0x10 #elif defined MOTOR_PIC i2c_configure_slave(MOTOR_ADDR << 1); //address 0x20 #elif defined PICMAN i2c_configure_slave(PICMAN_ADDR << 1); //address 0x10,different bus from sensor #elif defined I2C_MASTER //sending clock frequency i2c_configure_master(); //12MHz clock set hardcoded #endif #ifdef MASTER_PIC ///////Color Sensor Interrupt////////// TRISBbits.TRISB0 = 1; ANCON1bits.PCFG12 = 1; //not sure which is port b INTCONbits.INT0IE = 1; INTCON2bits.INTEDG0 = 0; INTCONbits.INT0IF = 0; initializeColorSensor(); /////////////////////////////////////// #endif // configure the hardware USART device #ifdef __USE18F26J50 Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 0x19); #else #ifdef __USE18F46J50 #ifndef MOTOR_PIC Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 38); #else Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 0x19); #endif #else OpenUSART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_HIGH, 38); // BAUDCONbits.BRG16 = 1; // TXSTAbits.TXEN = 1; // RCSTAbits.SPEN = 1; // RCSTAbits.CREN = 1; #endif #endif // Peripheral interrupts can have their priority set to high or low // enable high-priority interrupts and low-priority interrupts enable_interrupts(); LATBbits.LB7 = 0; #ifndef MASTER_PIC LATBbits.LB0 = 0; #endif LATBbits.LB1 = 0; LATBbits.LB2 = 0; LATBbits.LB3 = 0; WRITETIMER0(0x00FF); // loop forever // This loop is responsible for "handing off" messages to the subroutines // that should get them. Although the subroutines are not threads, but // they can be equated with the tasks in your task diagram if you // structure them properly. while (1) { // Call a routine that blocks until either on the incoming // messages queues has a message (this may put the processor into // an idle mode) block_on_To_msgqueues(); //We have a bunch of queues now - ToMainHigh, ToMainLow, FromMainHigh, FromMainLow, //FromUARTInt, and FromI2CInt //From queues are most important because they will be called repeatedly with busy info //Int queues are second because we'll often get data from either UART or I2C //ToMain are least length = FromMainHigh_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // This case be handled by your code. } } else { switch (msgtype) { #ifdef I2C_MASTER case MSGT_MASTER_RECV_BUSY: { //retry //debugNum(4); i2c_master_recv(msgbuffer[0]); break; }; case MSGT_MASTER_SEND_BUSY: { //retry //debugNum(8); i2c_master_send(msgbuffer[0], length - 1, msgbuffer + 1); // point to second position (actual msg start) break; }; case MSGT_MASTER_SEND_NO_RAW_BUSY: { i2c_master_send_no_raw(msgbuffer[0], length-1, msgbuffer + 1); }; case MSGT_TURN_CHECK: { //check IR sensors unsigned char frame[FRAME_MEMBERS] = {0}; packFrame(frame, sizeof frame); //frame[1] is ir1 and frame[2] is ir2 frame[1] = 1;//just for now, provide these dummy values frame[2] = 1; if((frame[1] > frame[2]) && (frame[1] - frame[2]) > 10){ //readjust right char out[HEADER_MEMBERS] = {0}; uint8 len = generateReadjustCW(out, sizeof out, I2C_COMM); i2c_master_send(MOTOR_ADDR, len, out); // no need to call waitForSensorFrame() again } else if((frame[2] > frame[1]) && (frame[2] - frame[1]) > 10){ //readjust left char out[HEADER_MEMBERS] = {0}; uint8 len = generateReadjustCCW(out, sizeof out, I2C_COMM); i2c_master_send(MOTOR_ADDR, len, out); // no need to call waitForSensorFrame() again } else{ char command[HEADER_MEMBERS] = {0}; uint8 len = generateTurnCompleteReq(command, sizeof command, UART_COMM); //tell picman turn complete uart_send_array(command, len); turnCompleted(); } }; #endif case MSGT_UART_TX_BUSY: { // TODO: take out for now uart_send_array(msgbuffer, length); break; }; default: break; } } length = FromUARTInt_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // This case be handled by your code. } } else { switch (msgtype) { case MSGT_OVERRUN: break; case MSGT_UART_DATA: { #ifdef PICMAN setRoverDataLP(msgbuffer); handleRoverDataLP(); #elif defined(MASTER_PIC) || defined(ROVER_EMU) setBrainDataLP(msgbuffer); //pass data received and tell will pass over i2c handleMessageLP(UART_COMM, I2C_COMM); //sends the response and then sets up the command handling #endif break; }; case MSGT_UART_RECV_FAILED: { debugNum(2); debugNum(4); debugNum(2); debugNum(4); break; }; case MSGT_UART_TX_BUSY: { // TODO: take out for now uart_send_array(msgbuffer, length); break; }; default: break; } } length = FromI2CInt_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // This case be handled by your code. } } else { switch (msgtype) { case MSGT_I2C_DATA: { #if defined(MASTER_PIC) || defined(ARM_EMU) //handle whatever data will come through via i2c //msgbuffer can hold real data - error codes will be returned through the error cases setRoverDataLP(msgbuffer); handleRoverDataLP(); #else setBrainDataLP(msgbuffer); #endif break; }; case MSGT_I2C_RQST: { #if defined(MOTOR_PIC) || defined(SENSOR_PIC) handleMessageLP(I2C_COMM, I2C_COMM); #elif defined(PICMAN) handleMessageLP(I2C_COMM, UART_COMM); #endif break; }; case MSGT_I2C_DBG: { // Here is where you could handle debugging, if you wanted // keep track of the first byte received for later use (if desired) last_reg_recvd = msgbuffer[0]; break; }; #ifdef MASTER_PIC case MSGT_I2C_MASTER_RECV_FAILED: { uart_send_array(msgbuffer, length); break; }; case MSGT_I2C_MASTER_SEND_FAILED: { uart_send_array(msgbuffer, length); break; }; case MSGT_MASTER_RECV_BUSY: { //retry // debugNum(4); i2c_master_recv(msgbuffer[0]); break; }; case MSGT_MASTER_SEND_BUSY: { //retry // debugNum(8); i2c_master_send(msgbuffer[0], length - 1, msgbuffer + 1); // point to second position (actual msg start) break; }; case MSGT_COLOR_SENSOR_INIT: { initializeColorSensorStage(); }; #endif default: break; } } length = ToMainHigh_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // This case be handled by your code. } } else { switch (msgtype) { case MSGT_TIMER0: { //timer0_lthread(&t0thread_data, msgtype, length, msgbuffer); break; }; // #ifdef I2C_MASTER // case MSGT_MASTER_RECV_BUSY: // { // //retry // debugNum(4); // i2c_master_recv(msgbuffer[0]); // break; // }; // case MSGT_MASTER_SEND_BUSY: // { // //retry // debugNum(8); // i2c_master_send(msgbuffer[0], length-1, msgbuffer + 1); // point to second position (actual msg start) // break; // }; // #endif // case MSGT_I2C_DATA: // { // debugNum(4); //#if defined(MASTER_PIC) || defined(ARM_EMU) // //handle whatever data will come through via i2c // //msgbuffer can hold real data - error codes will be returned through the error cases // setRoverDataLP(msgbuffer); // handleRoverDataLP(); //#else // setBrainDataLP(msgbuffer); //#endif // debugNum(4); // break; // }; // case MSGT_I2C_RQST: // { //#if defined(MOTOR_PIC) || defined(SENSOR_PIC) // handleMessageLP(I2C_COMM, I2C_COMM); //#elif defined(PICMAN) // handleMessageLP(I2C_COMM, UART_COMM); //#endif // break; // }; // case MSGT_I2C_DBG: // { // // Here is where you could handle debugging, if you wanted // // keep track of the first byte received for later use (if desired) // last_reg_recvd = msgbuffer[0]; // break; // }; //#ifdef MASTER_PIC // case MSGT_I2C_MASTER_RECV_FAILED: // { // uart_send_array(msgbuffer, length); // break; // }; // case MSGT_I2C_MASTER_SEND_FAILED: // { // uart_send_array(msgbuffer, length); // break; // }; //#endif case MSGT_AD: { #ifdef SENSOR_PIC //addDataPoints(sensorADid, msgbuffer, length); #endif break; }; default: { // Your code should handle this error break; }; }; } // Check the low priority queue length = ToMainLow_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // Your code should handle this situation } } else { switch (msgtype) { case MSGT_AD: { #ifdef SENSOR_PIC //addDataPoints(sensorADid, msgbuffer, length); #endif break; }; case MSGT_TIMER1: { //timer1_lthread(&t1thread_data, msgtype, length, msgbuffer); break; }; // case MSGT_OVERRUN: // break; // case MSGT_UART_DATA: // { //#ifdef PICMAN // setRoverDataLP(msgbuffer); // handleRoverDataLP(); //#elif defined(MASTER_PIC) || defined(ROVER_EMU) // setBrainDataLP(msgbuffer);//pass data received and tell will pass over i2c // handleMessageLP(UART_COMM, I2C_COMM); //sends the response and then sets up the command handling //#endif // break; // }; // case MSGT_UART_RECV_FAILED: // { // debugNum(1); // debugNum(2); // debugNum(1); // debugNum(2); // break; // }; default: { // Your code should handle this error break; }; }; } } // }
void board_init_r(gd_t *id, ulong dest_addr) { if (id) gd = id; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif #ifdef CONFIG_POST post_output_backlog(); #endif /* The Malloc area is at the top of simulated DRAM */ mem_malloc_init((ulong)gd->ram_buf + gd->ram_size - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); /* initialize environment */ env_relocate(); /* IP Address */ gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); stdio_init(); /* get the devices list going. */ jumptable_init(); console_init_r(); /* fully init console as a device */ #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) checkboard(); #endif #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init(); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r(); #endif /* set up exceptions */ interrupt_init(); /* enable exceptions */ enable_interrupts(); #ifdef CONFIG_BOARD_LATE_INIT board_late_init(); #endif #ifdef CONFIG_POST post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif sandbox_main_loop_init(); /* * For now, run the main loop. Later we might let this be done * in the main program. */ while (1) main_loop(); /* NOTREACHED - no way out of command loop except booting */ }
static void set_expire_event(timeval_t t) { disable_interrupts(); expire_event.time = t; schedule_insert(current_time(), &expire_event); enable_interrupts(); }
/* * @fn nm_drv_init * @brief Initialize NMC1000 driver * @return M2M_SUCCESS in case of success and Negative error code in case of failure * @param [in] arg * Generic argument * @author M. Abdelmawla * @date 15 July 2012 * @version 1.0 */ sint8 nm_drv_init(void * arg) { tstrM2mRev strtmp; sint8 ret = M2M_SUCCESS; uint8 u8Mode = M2M_WIFI_MODE_NORMAL; if(NULL != arg) { if(M2M_WIFI_MODE_CONFIG == *((uint8 *)arg)) { u8Mode = M2M_WIFI_MODE_CONFIG; } else { /*continue running*/ } } else { /*continue running*/ } ret = nm_bus_iface_init(NULL); if (M2M_SUCCESS != ret) { M2M_ERR("[nmi start]: fail init bus\n"); goto ERR1; } #ifdef BUS_ONLY return; #endif #ifdef NO_HW_CHIP_EN ret = chip_wake(); nm_bsp_sleep(10); if (M2M_SUCCESS != ret) { M2M_ERR("[nmi start]: fail chip_wakeup\n"); goto ERR2; } /** Go... **/ ret = chip_reset(); if (M2M_SUCCESS != ret) { goto ERR2; } #endif M2M_INFO("Chip ID %lx\n", nmi_get_chipid()); #ifdef CONF_WINC_USE_SPI /* Must do this after global reset to set SPI data packet size. */ nm_spi_init(); #endif #ifdef NO_HW_CHIP_EN /*return power save to default value*/ chip_idle(); ret = cpu_start(); if (M2M_SUCCESS != ret) { goto ERR2; } #endif ret = wait_for_bootrom(u8Mode); if (M2M_SUCCESS != ret) { goto ERR2; } ret = wait_for_firmware_start(u8Mode); if (M2M_SUCCESS != ret) { goto ERR2; } if(M2M_WIFI_MODE_CONFIG == u8Mode) { goto ERR1; } else { /*continue running*/ } ret = enable_interrupts(); if (M2M_SUCCESS != ret) { M2M_ERR("failed to enable interrupts..\n"); goto ERR2; } ret = nm_get_firmware_info(&strtmp); M2M_INFO("Firmware ver : %u.%u.%u\n", strtmp.u8FirmwareMajor, strtmp.u8FirmwareMinor, strtmp.u8FirmwarePatch); M2M_INFO("Min driver ver : %u.%u.%u\n", strtmp.u8DriverMajor, strtmp.u8DriverMinor, strtmp.u8DriverPatch); M2M_INFO("Curr driver ver: %u.%u.%u\n", M2M_DRIVER_VERSION_MAJOR_NO, M2M_DRIVER_VERSION_MINOR_NO, M2M_DRIVER_VERSION_PATCH_NO); if(strtmp.u8FirmwareMajor != M2M_DRIVER_VERSION_MAJOR_NO || strtmp.u8FirmwareMinor != M2M_DRIVER_VERSION_MINOR_NO) { ret = M2M_ERR_FW_VER_MISMATCH; M2M_ERR("Firmware version mismatch!\n"); } return ret; ERR2: nm_bus_iface_deinit(); ERR1: return ret; }
void main () { int R_B,L_B, R_VU, L_VU, avg_R=0, avg_L=0; coldstart(); // Grundinitialisierung enable_interrupts(GLOBAL); set_adc_channel(0); delay_ms (1); avg_L = read_adc(); set_adc_channel(1); delay_ms (1); avg_R = read_adc(); while (TRUE) // Beginn Hauptprogramm { // VU-Meter set_adc_channel(0); delay_ms (1); L_VU = read_adc(); set_adc_channel(1); delay_ms (1); R_VU = read_adc(); avg_L = (avg_L + L_VU) /2; avg_R = (avg_R + R_VU) /2; if((avg_L + avg_R) >= 3){ // VU-Meter - Portout L_B = Makevu (L_VU); R_B = Makevu (R_VU); Portout (L_B,R_B); // Bass, mid, treble set_adc_channel(2); delay_ms (1); if (read_adc() > 560) output_low (Ledb_p); else output_high (Ledb_p); set_adc_channel(3); delay_ms (1); if (read_adc() > 570) output_low (Ledm_p); else output_high (Ledm_p); set_adc_channel(4); delay_ms (1); if (read_adc() > 550) output_low (Ledt_p); else output_high (Ledt_p); } else { LEDTest8(); checkKeys(); LEDTest6(); checkKeys(); LEDTest3(); checkKeys(); LEDTest4(); checkKeys(); LEDTest2(); checkKeys(); LEDTest5(); checkKeys(); LEDTest7(); checkKeys(); LEDTest1(); } checkKeys(); } }
static int at91_attach(device_t dev) { struct at91_softc *sc = device_get_softc(dev); int i; arm_post_filter = at91_eoi; at91_softc = sc; sc->sc_st = &at91_bs_tag; sc->sc_sh = AT91_BASE; sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE; sc->dev = dev; sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "AT91 IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) panic("at91_attach: failed to set up IRQ rman"); sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "AT91 Memory"; if (rman_init(&sc->sc_mem_rman) != 0) panic("at91_attach: failed to set up memory rman"); /* * Manage the physical space, defined as being everything that isn't * DRAM. */ if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0) panic("at91_attach: failed to set up memory rman"); if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20), 0xfffffffful) != 0) panic("at91_attach: failed to set up memory rman"); /* * Setup the interrupt table. */ if (soc_info.soc_data == NULL || soc_info.soc_data->soc_irq_prio == NULL) panic("Interrupt priority table missing\n"); for (i = 0; i < 32; i++) { bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + i * 4, i); /* Priority. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, soc_info.soc_data->soc_irq_prio[i]); if (i < 8) bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, 1); } bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); /* No debug. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); /* Disable and clear all interrupts. */ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); /* * Add this device's children... */ at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children); soc_info.soc_data->soc_clock_init(); bus_generic_probe(dev); bus_generic_attach(dev); enable_interrupts(I32_bit | F32_bit); return (0); }
void undefinedinstruction(struct trapframe *frame) { struct thread *td; u_int fault_pc; int fault_instruction; int fault_code; int coprocessor; struct undefined_handler *uh; int error; #ifdef VERBOSE_ARM32 int s; #endif ksiginfo_t ksi; /* Enable interrupts if they were enabled before the exception. */ if (__predict_true(frame->tf_spsr & PSR_I) == 0) enable_interrupts(PSR_I); if (__predict_true(frame->tf_spsr & PSR_F) == 0) enable_interrupts(PSR_F); VM_CNT_INC(v_trap); fault_pc = frame->tf_pc; /* * Get the current thread/proc structure or thread0/proc0 if there is * none. */ td = curthread == NULL ? &thread0 : curthread; coprocessor = 0; if ((frame->tf_spsr & PSR_T) == 0) { /* * Make sure the program counter is correctly aligned so we * don't take an alignment fault trying to read the opcode. */ if (__predict_false((fault_pc & 3) != 0)) { ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLADR; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); userret(td, frame); return; } /* * Should use fuword() here .. but in the interests of * squeezing every bit of speed we will just use ReadWord(). * We know the instruction can be read as was just executed * so this will never fail unless the kernel is screwed up * in which case it does not really matter does it ? */ fault_instruction = *(u_int32_t *)fault_pc; /* Check for coprocessor instruction */ /* * According to the datasheets you only need to look at bit * 27 of the instruction to tell the difference between and * undefined instruction and a coprocessor instruction * following an undefined instruction trap. */ if (ARM_COPROC_INSN(fault_instruction)) coprocessor = ARM_COPROC(fault_instruction); else { /* check for special instructions */ if (ARM_VFP_INSN(fault_instruction)) coprocessor = COPROC_VFP; /* vfp / simd */ } } else { #if __ARM_ARCH >= 7 fault_instruction = *(uint16_t *)fault_pc; if (THUMB_32BIT_INSN(fault_instruction)) { fault_instruction <<= 16; fault_instruction |= *(uint16_t *)(fault_pc + 2); /* * Is it a Coprocessor, Advanced SIMD, or * Floating-point instruction. */ if (THUMB_COPROC_INSN(fault_instruction)) { if (THUMB_COPROC_UNDEFINED(fault_instruction)) { /* undefined insn */ } else if (THUMB_VFP_INSN(fault_instruction)) coprocessor = COPROC_VFP; else coprocessor = THUMB_COPROC(fault_instruction); } } #else /* * No support for Thumb-2 on this cpu */ ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLADR; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); userret(td, frame); return; #endif } if ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) { /* * Modify the fault_code to reflect the USR/SVC state at * time of fault. */ fault_code = FAULT_USER; td->td_frame = frame; } else fault_code = 0; /* OK this is were we do something about the instruction. */ LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link) if (uh->uh_handler(fault_pc, fault_instruction, frame, fault_code) == 0) break; if (fault_code & FAULT_USER) { /* TODO: No support for ptrace from Thumb-2 */ if ((frame->tf_spsr & PSR_T) == 0 && fault_instruction == PTRACE_BREAKPOINT) { PROC_LOCK(td->td_proc); _PHOLD(td->td_proc); error = ptrace_clear_single_step(td); _PRELE(td->td_proc); PROC_UNLOCK(td->td_proc); if (error != 0) { ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLOPC; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); } return; } } if (uh == NULL && (fault_code & FAULT_USER)) { /* Fault has not been handled */ ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLOPC; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); } if ((fault_code & FAULT_USER) == 0) { if (fault_instruction == KERNEL_BREAKPOINT) { #ifdef KDB kdb_trap(T_BREAKPOINT, 0, frame); #else printf("No debugger in kernel.\n"); #endif return; } else panic("Undefined instruction in kernel.\n"); } userret(td, frame); }
void start_armboot (void) { init_fnc_t **init_fnc_ptr; char *s; #if defined(CONFIG_VFD) || defined(CONFIG_LCD) unsigned long addr; #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t)); /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); memset ((void*)gd, 0, sizeof (gd_t)); gd->bd = (bd_t*)((char*)gd - sizeof(bd_t)); memset (gd->bd, 0, sizeof (bd_t)); gd->flags |= GD_FLG_RELOC; monitor_flash_len = _bss_start - _armboot_start; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); } } /* armboot_start is defined in the board-specific linker script */ mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); #ifndef CONFIG_SYS_NO_FLASH /* configure available FLASH banks */ display_flash_config (flash_init ()); #endif /* CONFIG_SYS_NO_FLASH */ #ifdef CONFIG_VFD # ifndef PAGE_SIZE # define PAGE_SIZE 4096 # endif /* * reserve memory for VFD display (always full pages) */ /* bss_end is defined in the board-specific linker script */ addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); vfd_setmem (addr); gd->fb_base = addr; #endif /* CONFIG_VFD */ #ifdef CONFIG_LCD /* board init may have inited fb_base */ if (!gd->fb_base) { # ifndef PAGE_SIZE # define PAGE_SIZE 4096 # endif /* * reserve memory for LCD display (always full pages) */ /* bss_end is defined in the board-specific linker script */ addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); lcd_setmem (addr); gd->fb_base = addr; } #endif /* CONFIG_LCD */ #if defined(CONFIG_CMD_NAND) puts ("NAND: "); nand_init(); /* go init the NAND */ #endif #if defined(CONFIG_CMD_ONENAND) onenand_init(); #endif #ifdef CONFIG_HAS_DATAFLASH AT91F_DataflashInit(); dataflash_print_info(); #endif /* initialize environment */ env_relocate (); #ifdef CONFIG_VFD /* must do this after the framebuffer is allocated */ drv_vfd_init(); #endif /* CONFIG_VFD */ #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif /* IP Address */ gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); stdio_init (); /* get the devices list going. */ jumptable_init (); #if defined(CONFIG_API) /* Initialize API */ api_init (); #endif console_init_r (); /* fully init console as a device */ #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init (); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); #endif /* enable exceptions */ enable_interrupts (); /* Perform network card initialisation if necessary */ #ifdef CONFIG_DRIVER_TI_EMAC /* XXX: this needs to be moved to board init */ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); if (getenv ("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); davinci_eth_set_mac_addr(enetaddr); } #endif #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ if (getenv ("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); smc_set_mac_addr(enetaddr); } #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ /* Initialize from environment */ if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); } #if defined(CONFIG_CMD_NET) if ((s = getenv ("bootfile")) != NULL) { copy_filename (BootFile, s, sizeof (BootFile)); } #endif #ifdef BOARD_LATE_INIT board_late_init (); #endif #ifdef CONFIG_GENERIC_MMC puts ("MMC: "); mmc_initialize (gd->bd); #endif #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts ("Net: "); #endif eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) debug ("Reset Ethernet PHY\n"); reset_phy(); #endif #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { main_loop (); } /* NOTREACHED - no way out of command loop except booting */ }
static void idle(void) { enable_interrupts(); while(1); }
void undefinedinstruction(trapframe_t *frame) { struct proc *p; u_int fault_pc; int fault_instruction; int fault_code; int coprocessor; struct undefined_handler *uh; #ifdef VERBOSE_ARM32 int s; #endif union sigval sv; /* Before enabling interrupts, save FPU state */ vfp_save(); /* Enable interrupts if they were enabled before the exception. */ if (!(frame->tf_spsr & I32_bit)) enable_interrupts(I32_bit); frame->tf_pc -= INSN_SIZE; fault_pc = frame->tf_pc; /* Get the current proc structure or proc0 if there is none. */ p = (curproc == NULL) ? &proc0 : curproc; /* * Make sure the program counter is correctly aligned so we * don't take an alignment fault trying to read the opcode. */ if (__predict_false((fault_pc & 3) != 0)) { /* Give the user an illegal instruction signal. */ sv.sival_int = (u_int32_t) fault_pc; trapsignal(p, SIGILL, 0, ILL_ILLOPC, sv); userret(p); return; } /* * Should use copyin() here .. but in the interests of squeezing every * bit of speed we will just read it directly. We know the instruction * can be read as was just executed so this will never fail unless the * kernel is screwed up in which case it does not really matter does * it? */ fault_instruction = *(u_int32_t *)fault_pc; /* Update vmmeter statistics */ uvmexp.traps++; /* Check for coprocessor instruction */ /* * According to the datasheets you only need to look at bit 27 of the * instruction to tell the difference between and undefined * instruction and a coprocessor instruction following an undefined * instruction trap. */ if ((fault_instruction & (1 << 27)) != 0) coprocessor = (fault_instruction >> 8) & 0x0f; else
static int initr_enable_interrupts(void) { enable_interrupts(); return 0; }
int cpu_post_test_rlwnm (void) { int ret = 0; unsigned int i, reg; int flag = disable_interrupts(); for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++) { struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i; for (reg = 0; reg < 32 && ret == 0; reg++) { unsigned int reg0 = (reg + 0) % 32; unsigned int reg1 = (reg + 1) % 32; unsigned int reg2 = (reg + 2) % 32; unsigned int stk = reg < 16 ? 31 : 15; unsigned long code[] = { ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -24), ASM_STW(3, stk, 12), ASM_STW(4, stk, 16), ASM_STW(reg0, stk, 8), ASM_STW(reg1, stk, 4), ASM_STW(reg2, stk, 0), ASM_LWZ(reg1, stk, 12), ASM_LWZ(reg0, stk, 16), ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), ASM_STW(reg2, stk, 12), ASM_LWZ(reg2, stk, 0), ASM_LWZ(reg1, stk, 4), ASM_LWZ(reg0, stk, 8), ASM_LWZ(3, stk, 12), ASM_ADDI(1, stk, 24), ASM_LWZ(stk, 1, -4), ASM_BLR, }; unsigned long codecr[] = { ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -24), ASM_STW(3, stk, 12), ASM_STW(4, stk, 16), ASM_STW(reg0, stk, 8), ASM_STW(reg1, stk, 4), ASM_STW(reg2, stk, 0), ASM_LWZ(reg1, stk, 12), ASM_LWZ(reg0, stk, 16), ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | BIT_C, ASM_STW(reg2, stk, 12), ASM_LWZ(reg2, stk, 0), ASM_LWZ(reg1, stk, 4), ASM_LWZ(reg0, stk, 8), ASM_LWZ(3, stk, 12), ASM_ADDI(1, stk, 24), ASM_LWZ(stk, 1, -4), ASM_BLR, }; ulong res; ulong cr; if (ret == 0) { cr = 0; cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); ret = res == test->res && cr == 0 ? 0 : -1; if (ret != 0) { post_log ("Error at rlwnm test %d !\n", i); } } if (ret == 0) { cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); ret = res == test->res && (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; if (ret != 0) { post_log ("Error at rlwnm test %d !\n", i); } } } } if (flag) enable_interrupts(); return ret; }
void main(void) { char c; signed char length; unsigned char msgtype; unsigned char last_reg_recvd; uart_comm uc; i2c_comm ic; unsigned char msgbuffer[MSGLEN + 1]; unsigned char i; uart_thread_struct uthread_data; // info for uart_lthread timer1_thread_struct t1thread_data; // info for timer1_lthread timer0_thread_struct t0thread_data; // info for timer0_lthread #ifdef __USE18F2680 OSCCON = 0xFC; // see datasheet // We have enough room below the Max Freq to enable the PLL for this chip OSCTUNEbits.PLLEN = 1; // 4x the clock speed in the previous line #else #ifdef __USE18F45J10 OSCCON = 0x82; // see datasheeet OSCTUNEbits.PLLEN = 0; // Makes the clock exceed the PIC's rated speed if the PLL is on #else #ifdef __USE18F26J50 OSCCON = 0xE0; // see datasheeet OSCTUNEbits.PLLEN = 1; #else #ifdef __USE18F46J50 OSCCON = 0xE0; //see datasheet OSCTUNEbits.PLLEN = 1; //Initialize TRISEbits.TRISE0 = 0x0; LATEbits.LE0 = 0x0; LATEbits.LE0 = 0x1; TRISCbits.TRISC7 = 0x1; // input RX TRISCbits.TRISC6 = 0x0; // output TX SPBRGH1 = 0x00; SPBRG1 = 0xcf; TXSTA1bits.BRGH = 1; BAUDCON1bits.BRG16 = 1; TXSTA1bits.SYNC = 0; RCSTA1bits.SPEN = 0x1; TXSTA1bits.TXEN = 0x1; #else Something is messed up. The PIC selected is not supported or the preprocessor directives are wrong. #endif #endif #endif #endif // initialize my uart recv handling code init_uart_recv(&uc); // initialize the i2c code init_i2c(&ic); // init the timer1 lthread init_timer1_lthread(&t1thread_data); // initialize message queues before enabling any interrupts init_queues(); #ifndef __USE18F26J50 // set direction for PORTB to output TRISB = 0x0; LATB = 0x0; #endif // how to set up PORTA for input (for the V4 board with the PIC2680) /* PORTA = 0x0; // clear the port LATA = 0x0; // clear the output latch ADCON1 = 0x0F; // turn off the A2D function on these pins // Only for 40-pin version of this chip CMCON = 0x07; // turn the comparator off TRISA = 0x0F; // set RA3-RA0 to inputs */ //Initialize the ADC module ADC_Init(); // initialize Timers OpenTimer0(TIMER_INT_ON & T0_16BIT & T0_SOURCE_INT & T0_PS_1_64); #ifdef __USE18F26J50 // MTJ added second argument for OpenTimer1() OpenTimer1(TIMER_INT_ON & T1_SOURCE_FOSC_4 & T1_PS_1_8 & T1_16BIT_RW & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF,0x0); #else #ifdef __USE18F46J50 OpenTimer1(TIMER_INT_ON & T1_SOURCE_FOSC_4 & T1_PS_1_8 & T1_16BIT_RW & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF,0x0); #else OpenTimer1(TIMER_INT_ON & T1_PS_1_8 & T1_16BIT_RW & T1_SOURCE_INT & T1_OSC1EN_OFF & T1_SYNC_EXT_OFF); #endif #endif // Decide on the priority of the enabled peripheral interrupts // 0 is low, 1 is high // Timer1 interrupt IPR1bits.TMR1IP = 0; // USART RX interrupt IPR1bits.RCIP = 0; // I2C interrupt IPR1bits.SSPIP = 1; // configure the hardware i2c device as a slave (0x9E -> 0x4F) or (0x9A -> 0x4D) #if 1 // Note that the temperature sensor Address bits (A0, A1, A2) are also the // least significant bits of LATB -- take care when changing them // They *are* changed in the timer interrupt handlers if those timers are // enabled. They are just there to make the lights blink and can be // disabled. i2c_configure_slave(0x9E); #else // If I want to test the temperature sensor from the ARM, I just make // sure this PIC does not have the same address and configure the // temperature sensor address bits and then just stay in an infinite loop i2c_configure_slave(0x9A); #ifdef __USE18F2680 LATBbits.LATB1 = 1; LATBbits.LATB0 = 1; LATBbits.LATB2 = 1; #endif for (;;); #endif // must specifically enable the I2C interrupts PIE1bits.SSPIE = 1; // configure the hardware USART device #ifdef __USE18F26J50 Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 0x19); #else #ifdef __USE18F46J50 Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 0x19); #else OpenUSART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_LOW, 0x19); #endif #endif // Peripheral interrupts can have their priority set to high or low // enable high-priority interrupts and low-priority interrupts enable_interrupts(); /* Junk to force an I2C interrupt in the simulator (if you wanted to) PIR1bits.SSPIF = 1; _asm goto 0x08 _endasm; */ // printf() is available, but is not advisable. It goes to the UART pin // on the PIC and then you must hook something up to that to view it. // It is also slow and is blocking, so it will perturb your code's operation // Here is how it looks: printf("Hello\r\n"); // loop forever // This loop is responsible for "handing off" messages to the subroutines // that should get them. Although the subroutines are not threads, but // they can be equated with the tasks in your task diagram if you // structure them properly. while (1) { // Call a routine that blocks until either on the incoming // messages queues has a message (this may put the processor into // an idle mode) block_on_To_msgqueues(); // At this point, one or both of the queues has a message. It // makes sense to check the high-priority messages first -- in fact, // you may only want to check the low-priority messages when there // is not a high priority message. That is a design decision and // I haven't done it here. length = ToMainHigh_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // This case be handled by your code. } } else { switch (msgtype) { case MSGT_TIMER0: { DEBUG_ON(TIMER0_MSG_RCV); timer0_lthread(&t0thread_data, msgtype, length, msgbuffer); DEBUG_OFF(TIMER0_MSG_RCV); break; }; case MSGT_I2C_DATA: case MSGT_I2C_DBG: { // Here is where you could handle debugging, if you wanted // keep track of the first byte received for later use (if desired) last_reg_recvd = msgbuffer[0]; break; }; case MSGT_I2C_RQST: { // Generally, this is *NOT* how I recommend you handle an I2C slave request // I recommend that you handle it completely inside the i2c interrupt handler // by reading the data from a queue (i.e., you would not send a message, as is done // now, from the i2c interrupt handler to main to ask for data). // // The last byte received is the "register" that is trying to be read // The response is dependent on the register. switch (last_reg_recvd) { case 0xaa: { length = 2; msgbuffer[0] = 0x55; msgbuffer[1] = 0xAA; break; } case 0xa8: { length = 1; msgbuffer[0] = 0x3A; break; } case 0xa9: { length = 1; msgbuffer[0] = 0xA3; break; } }; start_i2c_slave_reply(length, msgbuffer); break; }; default: { // Your code should handle this error break; }; }; } // Check the low priority queue length = ToMainLow_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); if (length < 0) { // no message, check the error code to see if it is concern if (length != MSGQUEUE_EMPTY) { // Your code should handle this situation } } else { switch (msgtype) { case MSGT_TIMER1: { timer1_lthread(&t1thread_data, msgtype, length, msgbuffer); break; }; case MSGT_OVERRUN: case MSGT_UART_DATA: { SensorData_recvmsg(MSGLEN, &msgtype, (void *) msgbuffer); unsigned int *msgval; msgval = (unsigned int *) msgbuffer; unsigned int val = *msgval; uart_lthread(&uthread_data, msgtype, length, &val); //unsigned char *msgbuf = msgbuffer; //unsigned int* newval = (unsigned int *) msgbuf; //*newval is the ADC result in hex format //uart_lthread(&uthread_data, msgtype, length, msgbuffer); break; }; default: { // Your code should handle this error break; }; }; } } }
void x86_page_fault_exception(struct iframe* frame) { Thread* thread = thread_get_current_thread(); addr_t cr2 = x86_read_cr2(); addr_t newip; if (debug_debugger_running()) { // If this CPU or this thread has a fault handler, we're allowed to be // here. if (thread != NULL) { cpu_ent* cpu = &gCPU[smp_get_current_cpu()]; if (cpu->fault_handler != 0) { debug_set_page_fault_info(cr2, frame->ip, (frame->error_code & 0x2) != 0 ? DEBUG_PAGE_FAULT_WRITE : 0); frame->ip = cpu->fault_handler; frame->bp = cpu->fault_handler_stack_pointer; return; } if (thread->fault_handler != 0) { kprintf("ERROR: thread::fault_handler used in kernel " "debugger!\n"); debug_set_page_fault_info(cr2, frame->ip, (frame->error_code & 0x2) != 0 ? DEBUG_PAGE_FAULT_WRITE : 0); frame->ip = thread->fault_handler; return; } } // otherwise, not really panic("page fault in debugger without fault handler! Touching " "address %p from ip %p\n", (void*)cr2, (void*)frame->ip); return; } else if ((frame->flags & 0x200) == 0) { // interrupts disabled // If a page fault handler is installed, we're allowed to be here. // TODO: Now we are generally allowing user_memcpy() with interrupts // disabled, which in most cases is a bug. We should add some thread // flag allowing to explicitly indicate that this handling is desired. if (thread && thread->fault_handler != 0) { if (frame->ip != thread->fault_handler) { frame->ip = thread->fault_handler; return; } // The fault happened at the fault handler address. This is a // certain infinite loop. panic("page fault, interrupts disabled, fault handler loop. " "Touching address %p from ip %p\n", (void*)cr2, (void*)frame->ip); } // If we are not running the kernel startup the page fault was not // allowed to happen and we must panic. panic("page fault, but interrupts were disabled. Touching address " "%p from ip %p\n", (void*)cr2, (void*)frame->ip); return; } else if (thread != NULL && thread->page_faults_allowed < 1) { panic("page fault not allowed at this place. Touching address " "%p from ip %p\n", (void*)cr2, (void*)frame->ip); return; } enable_interrupts(); vm_page_fault(cr2, frame->ip, (frame->error_code & 0x2) != 0, // write access (frame->error_code & 0x4) != 0, // userland &newip); if (newip != 0) { // the page fault handler wants us to modify the iframe to set the // IP the cpu will return to this ip frame->ip = newip; } }
static int at91_attach(device_t dev) { struct at91_softc *sc = device_get_softc(dev); int i; at91_softc = sc; sc->sc_st = &at91_bs_tag; sc->sc_sh = AT91RM92_BASE; sc->dev = dev; if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) panic("Enable to map IRQ registers"); sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "AT91 IRQs"; sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "AT91 Memory"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) panic("at91_attach: failed to set up IRQ rman"); if (rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_mem_rman, 0xdff00000ul, 0xdffffffful) != 0) panic("at91_attach: failed to set up memory rman"); if (rman_manage_region(&sc->sc_mem_rman, AT91RM92_OHCI_BASE, AT91RM92_OHCI_BASE + AT91RM92_OHCI_SIZE - 1) != 0) panic("at91_attach: failed to set up ohci memory"); if (rman_manage_region(&sc->sc_mem_rman, AT91RM92_CF_BASE, AT91RM92_CF_BASE + AT91RM92_CF_SIZE - 1) != 0) panic("at91_attach: failed to set up CompactFlash ATA memory"); for (i = 0; i < 32; i++) { bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SVR + i * 4, i); /* Priority. */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SMR + i * 4, irq_prio[i]); if (i < 8) bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_EOICR, 1); } bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SPU, 32); /* No debug. */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_DCR, 0); /* Disable and clear all interrupts. */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_ICCR, 0xffffffff); /* XXX */ /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); /* DIsable all interrupts for DBGU */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x20c, 0xffffffff); /* Disable all interrupts for the SDRAM controller */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); at91_cpu_add_builtin_children(dev, sc); bus_generic_probe(dev); bus_generic_attach(dev); enable_interrupts(I32_bit | F32_bit); return (0); }
void board_init_r(gd_t *id, ulong dest_addr) { char *s; bd_t *bd; ulong malloc_start; #if !defined(CONFIG_SYS_NO_FLASH) ulong flash_size; #endif gd = id; bd = gd->bd; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ monitor_flash_len = _end_ofs; /* Enable caches */ enable_caches(); debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); #ifdef CONFIG_LOGBUFFER logbuff_init_ptrs(); #endif #ifdef CONFIG_POST post_output_backlog(); #endif /* The Malloc area is immediately below the monitor copy in DRAM */ malloc_start = dest_addr - TOTAL_MALLOC_LEN; mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); #if !defined(CONFIG_SYS_NO_FLASH) puts("Flash: "); flash_size = flash_init(); if (flash_size > 0) { # ifdef CONFIG_SYS_FLASH_CHECKSUM print_size(flash_size, ""); /* * Compute and print flash CRC if flashchecksum is set to 'y' * * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX */ s = getenv("flashchecksum"); if (s && (*s == 'y')) { printf(" CRC: %08X", crc32(0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)); } putc('\n'); # else /* !CONFIG_SYS_FLASH_CHECKSUM */ print_size(flash_size, "\n"); # endif /* CONFIG_SYS_FLASH_CHECKSUM */ } else { puts(failed); hang(); } #endif #if defined(CONFIG_CMD_NAND) puts("NAND: "); nand_init(); /* go init the NAND */ #endif #if defined(CONFIG_CMD_ONENAND) onenand_init(); #endif #ifdef CONFIG_GENERIC_MMC puts("MMC: "); mmc_initialize(bd); #endif #ifdef CONFIG_HAS_DATAFLASH AT91F_DataflashInit(); dataflash_print_info(); #endif /* initialize environment */ env_relocate(); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) arm_pci_init(); #endif /* IP Address */ gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); stdio_init(); /* get the devices list going. */ jumptable_init(); #if defined(CONFIG_API) /* Initialize API */ api_init(); #endif console_init_r(); /* fully init console as a device */ #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init(); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r(); #endif /* set up exceptions */ interrupt_init(); /* enable exceptions */ enable_interrupts(); /* Perform network card initialisation if necessary */ #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ if (getenv("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); smc_set_mac_addr(enetaddr); } #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ /* Initialize from environment */ s = getenv("loadaddr"); if (s != NULL) load_addr = simple_strtoul(s, NULL, 16); #if defined(CONFIG_CMD_NET) s = getenv("bootfile"); if (s != NULL) copy_filename(BootFile, s, sizeof(BootFile)); #endif #ifdef BOARD_LATE_INIT board_late_init(); #endif #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts("Net: "); #endif eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) debug("Reset Ethernet PHY\n"); reset_phy(); #endif #endif #ifdef CONFIG_POST post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) /* * Export available size of memory for Linux, * taking into account the protected RAM at top of memory */ { ulong pram; uchar memsz[32]; #ifdef CONFIG_PRAM char *s; s = getenv("pram"); if (s != NULL) pram = simple_strtoul(s, NULL, 10); else pram = CONFIG_PRAM; #else pram = 0; #endif #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram); setenv("mem", (char *)memsz); } #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { main_loop(); } /* NOTREACHED - no way out of command loop except booting */ }
void board_init_r(gd_t *new_gd, ulong dest_addr) { #ifndef CONFIG_ENV_IS_NOWHERE extern char * env_name_spec; #endif bd_t *bd; gd = new_gd; bd = gd->bd; gd->flags |= GD_FLG_RELOC; gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; /* Enable the MMU so that we can keep u-boot simple */ mmu_init_r(dest_addr); board_early_init_r(); monitor_flash_len = _edata - _text; #if defined(CONFIG_NEEDS_MANUAL_RELOC) /* * We have to relocate the command table manually */ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE env_name_spec += gd->reloc_off; #endif timer_init(); /* The malloc area is right below the monitor image in RAM */ mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); enable_interrupts(); bd->bi_flashstart = 0; bd->bi_flashsize = 0; bd->bi_flashoffset = 0; #ifndef CONFIG_SYS_NO_FLASH bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; bd->bi_flashsize = flash_init(); bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text; if (bd->bi_flashsize) display_flash_config(); #endif if (bd->bi_dram[0].size) display_dram_config(); gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN); if (!gd->bd->bi_boot_params) puts("WARNING: Cannot allocate space for boot parameters\n"); /* initialize environment */ env_relocate(); stdio_init(); jumptable_init(); console_init_r(); /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) puts("Net: "); eth_initialize(gd->bd); #endif #ifdef CONFIG_GENERIC_ATMEL_MCI mmc_initialize(gd->bd); #endif for (;;) { main_loop(); } }