コード例 #1
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/* Enable the full line of zero */
	if (soc_is_exynos4210() || soc_is_exynos4212() ||
	    soc_is_exynos4412() || soc_is_exynos4415())
		enable_cache_foz();

	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	write_pen_release(-1);

#ifdef CONFIG_ARM_TRUSTZONE
	clear_boot_flag(cpu, HOTPLUG);
#endif

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #2
0
ファイル: platsmp.c プロジェクト: Analias/SNOWLeo-SDR-1
/* Secondary CPU kernel startup is a 2 step process. The primary CPU
 * starts the secondary CPU by giving it the address of the kernel and
 * then sending it an event to wake it up. The secondary CPU then
 * starts the kernel and tells the primary CPU it's up and running.
 */
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/* Indicate to the primary core that the secondary is up and running.
	 * Let the write buffer drain.
	 */

	/* Restore memory content */
	if (mem_backup_done) {
		__raw_writel(mem_backup[0], zero + 0x0);
		__raw_writel(mem_backup[1], zero + 0x4);
		__raw_writel(mem_backup[2], zero + 0x8);
	}


	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #3
0
void platform_secondary_init(unsigned int cpu)
{
	pr_debug("CPU%u: Booted secondary processor\n", cpu);

	WARN_ON(msm_platform_secondary_init(cpu));

	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	write_pen_release(-1);

	/* clear the IPC1(SPI-8) pending SPI */
	if (power_collapsed) {
		raise_clear_spi(1, false);
		clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
		power_collapsed = 0;
	}

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #4
0
static void __cpuinit omap4_secondary_init(unsigned int cpu)
{
	/*
	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
	 * OMAP443X GP devices- SMP bit isn't accessible.
	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
	 */
	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
							4, 0, 0, 0, 0, 0);

	/*
	 * If any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #5
0
ファイル: platsmp.c プロジェクト: anewkirk/AJK
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/* Configure edge-triggered PPIs */
	writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);

	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	pen_release = -1;
	smp_wmb();

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #6
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	u32 diag0_errata_flags = 0;
	/* Enable NS access to SMP bit for this CPU on HS devices */
	if (cpu_is_omap446x() || cpu_is_omap443x()) {
		if (omap_type() != OMAP2_DEVICE_TYPE_GP)
			omap4_secure_dispatcher(PPA_SERVICE_DEFAULT_POR_NS_SMP,
					FLAG_START_CRITICAL,
					0, 0, 0, 0, 0);
		else {
			diag0_errata_flags =
				omap4_get_diagctrl0_errata_flags();
			if (diag0_errata_flags)
				omap_smc1(HAL_DIAGREG_0, diag0_errata_flags);
		}

	}

	/*
	 * If any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #7
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);

	cpumask_set_cpu(cpu, to_cpumask(tegra_cpu_init_bits));
	if (!tegra_all_cpus_booted)
		if (cpumask_equal(tegra_cpu_init_mask, cpu_present_mask))
			tegra_all_cpus_booted = true;
}
コード例 #8
0
ファイル: platsmp.c プロジェクト: FadyAzar/linux-te-3.9
/* Secondary CPU kernel startup is a 2 step process. The primary CPU
 * starts the secondary CPU by giving it the address of the kernel and
 * then sending it an event to wake it up. The secondary CPU then
 * starts the kernel and tells the primary CPU it's up and running.
 */
static void __cpuinit zynq_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);
}
コード例 #9
0
void platform_secondary_init(unsigned int cpu)
{
	WARN_ON(msm_platform_secondary_init(cpu));

	gic_secondary_init(0);

	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #10
0
ファイル: smp.c プロジェクト: WayWingsDev/gopro-linux
/* ==========================================================================*/
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);

	spin_lock(&boot_lock);
#ifdef CONFIG_OUTER_CACHE
	if (smp_l2_mode)
		ambcache_l2_enable_raw();
#endif
	spin_unlock(&boot_lock);
}
コード例 #11
0
ファイル: irq-gic.c プロジェクト: IRT-SystemX/xvisor-next
static int __cpuinit gic_eoimode_init(struct vmm_devtree_node *node)
{
	int rc;

	if (vmm_smp_is_bootcpu()) {
		rc = gic_devtree_init(node, NULL, TRUE);
	} else {
		gic_secondary_init(0);
		rc = VMM_OK;
	}

	return rc;
}
コード例 #12
0
ファイル: platsmp.c プロジェクト: Avasz/D33_KK_Kernel
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

#ifdef CONFIG_FIQ
	gic_secondary_init_non_secure();
	fiq_glue_resume();
#endif
}
コード例 #13
0
ファイル: sunxi-platsmp.c プロジェクト: alex-deng/a33_linux
/*
 * Perform platform specific initialisation of the specified CPU.
 */
void sunxi_smp_secondary_init(unsigned int cpu)
{
    /*
     * if any interrupts are already enabled for the primary
     * core (e.g. timer irq), then they will not have been enabled
     * for us: do so
     */
    gic_secondary_init(0);

    /*
     * Synchronise with the boot thread.
     */
    spin_lock(&boot_lock);
    spin_unlock(&boot_lock);
}
コード例 #14
0
ファイル: platsmp.c プロジェクト: BillTheBest/pandorabox
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
	 * If any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);
	
	write_pen_release(-1);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #15
0
ファイル: platsmp.c プロジェクト: jthatch12/STi2_M7
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	WARN_ON(msm_platform_secondary_init(cpu));

	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	write_pen_release(-1);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #16
0
/* Initialization routine for secondary CPUs after they are brought out of
 * reset.
*/
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	pr_debug("CPU%u: Booted secondary processor\n", cpu);

	WARN_ON(msm_platform_secondary_init(cpu));

	trace_hardirqs_off();

	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);

	/* RUMI does not adhere to GIC spec by enabling STIs by default.
	 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
	 */
	if (!machine_is_msm8x60_sim())
		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);

	gic_secondary_init(0);
}
コード例 #17
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	pr_debug("CPU%u: Booted secondary processor\n", cpu);

	WARN_ON(msm_platform_secondary_init(cpu));

	gic_secondary_init(0);

	write_pen_release(-1);

	
	if (per_cpu(power_collapsed, cpu)) {
		raise_clear_spi(cpu, false);
		clear_pending_spi(cpu_data[cpu].ipc_irq);		
		per_cpu(power_collapsed, cpu) = 0;
	}

	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #18
0
ファイル: platsmp.c プロジェクト: SEREGIZ/linux-xlnx
/* Secondary CPU kernel startup is a 2 step process. The primary CPU
 * starts the secondary CPU by giving it the address of the kernel and
 * then sending it an event to wake it up. The secondary CPU then
 * starts the kernel and tells the primary CPU it's up and running.
 */
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/* Indicate to the primary core that the secondary is up and running.
	 * Let the write buffer drain.
	 */
	__raw_writel(BOOT_STATUS_CPU1_UP, OCM_HIGH_BASE + BOOT_STATUS_OFFSET);
	wmb();

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #19
0
ファイル: platsmp.c プロジェクト: 4atty/linux
static void __cpuinit ux500_secondary_init(unsigned int cpu)
{
	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	write_pen_release(-1);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #20
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	/*
                                                         
                                                               
                 
  */
	gic_secondary_init(0);

	/*
                                                   
                                             
  */
	write_pen_release(-1);

	/*
                                     
  */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #21
0
void __cpuinit platform_secondary_init(unsigned int cpu)
{
	edb_putstr("platform_secondary_init\n");

	/*
	 * if any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * let the primary processor know we're out of the
	 * pen, then head off into the C entry point
	 */
	pen_release = -1;
	smp_wmb();

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}
コード例 #22
0
ファイル: platsmp.c プロジェクト: 8563/millennium-sources
static void __cpuinit virt_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);
}
コード例 #23
0
static void __cpuinit mcpm_secondary_init(unsigned int cpu)
{
	mcpm_cpu_powered_up();
	gic_secondary_init(0);
}
コード例 #24
0
void r8a7779_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);
}
コード例 #25
0
static void __cpuinit highbank_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);
}
コード例 #26
0
ファイル: platsmp.c プロジェクト: bigdreamteam/loftq-linux
void __cpuinit platform_secondary_init(unsigned int cpu)
{
    pr_debug("[%s] enter, cpu:%d\n", __FUNCTION__, cpu);
    gic_secondary_init(0);
}
コード例 #27
0
void platform_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);
}
コード例 #28
0
static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
{
	gic_secondary_init(0);
}