void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size) { int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16; current_reg |= (frame_size.pplen - 1); isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE); }
void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync) { int val = 0; val = isp5_read(DM365_ISP5_CCDCMUX); val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT); val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT); isp5_write(val, DM365_ISP5_CCDCMUX); }
static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) { u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK; if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG) temp |= 0x08; temp |= (src_sel << CCD_SRC_SEL_SHIFT); isp5_write(temp, DM365_ISP5_CCDCMUX); }
static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel) { u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK; /* if we are using pattern generator, enable it */ if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG) temp |= 0x08; temp |= (src_sel << CCD_SRC_SEL_SHIFT); isp5_write(temp, DM365_ISP5_CCDCMUX); }
static int __init vpss_probe(struct platform_device *pdev) { struct resource *r1, *r2; char *platform_name; int status; if (!pdev->dev.platform_data) { dev_err(&pdev->dev, "no platform data\n"); return -ENOENT; } platform_name = pdev->dev.platform_data; if (!strcmp(platform_name, "dm355_vpss")) oper_cfg.platform = DM355; else if (!strcmp(platform_name, "dm365_vpss")) oper_cfg.platform = DM365; else if (!strcmp(platform_name, "dm644x_vpss")) oper_cfg.platform = DM644X; else { dev_err(&pdev->dev, "vpss driver not supported on" " this platform\n"); return -ENODEV; } dev_info(&pdev->dev, "%s vpss probed\n", platform_name); r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r1) return -ENOENT; r1 = request_mem_region(r1->start, resource_size(r1), r1->name); if (!r1) return -EBUSY; oper_cfg.vpss_regs_base0 = ioremap(r1->start, resource_size(r1)); if (!oper_cfg.vpss_regs_base0) { status = -EBUSY; goto fail1; } if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) { r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (!r2) { status = -ENOENT; goto fail2; } r2 = request_mem_region(r2->start, resource_size(r2), r2->name); if (!r2) { status = -EBUSY; goto fail2; } oper_cfg.vpss_regs_base1 = ioremap(r2->start, resource_size(r2)); if (!oper_cfg.vpss_regs_base1) { status = -EBUSY; goto fail3; } } if (oper_cfg.platform == DM355) { oper_cfg.hw_ops.enable_clock = dm355_enable_clock; oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source; bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL); bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL); } else if (oper_cfg.platform == DM365) { oper_cfg.hw_ops.enable_clock = dm365_enable_clock; oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source; isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1); isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2); isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3); } else oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow; spin_lock_init(&oper_cfg.vpss_lock); dev_info(&pdev->dev, "%s vpss probe success\n", platform_name); return 0; fail3: release_mem_region(r2->start, resource_size(r2)); fail2: iounmap(oper_cfg.vpss_regs_base0); fail1: release_mem_region(r1->start, resource_size(r1)); return status; }
static int vpss_probe(struct platform_device *pdev) { struct resource *res; char *platform_name; if (!pdev->dev.platform_data) { dev_err(&pdev->dev, "no platform data\n"); return -ENOENT; } platform_name = pdev->dev.platform_data; if (!strcmp(platform_name, "dm355_vpss")) oper_cfg.platform = DM355; else if (!strcmp(platform_name, "dm365_vpss")) oper_cfg.platform = DM365; else if (!strcmp(platform_name, "dm644x_vpss")) oper_cfg.platform = DM644X; else { dev_err(&pdev->dev, "vpss driver not supported on this platform\n"); return -ENODEV; } dev_info(&pdev->dev, "%s vpss probed\n", platform_name); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(oper_cfg.vpss_regs_base0)) return PTR_ERR(oper_cfg.vpss_regs_base0); if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) { res = platform_get_resource(pdev, IORESOURCE_MEM, 1); oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(oper_cfg.vpss_regs_base1)) return PTR_ERR(oper_cfg.vpss_regs_base1); } if (oper_cfg.platform == DM355) { oper_cfg.hw_ops.enable_clock = dm355_enable_clock; oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source; /* Setup vpss interrupts */ bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL); bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL); } else if (oper_cfg.platform == DM365) { oper_cfg.hw_ops.enable_clock = dm365_enable_clock; oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source; /* Setup vpss interrupts */ isp5_write((isp5_read(DM365_ISP5_PCCR) | DM365_ISP5_PCCR_BL_CLK_ENABLE | DM365_ISP5_PCCR_ISIF_CLK_ENABLE | DM365_ISP5_PCCR_H3A_CLK_ENABLE | DM365_ISP5_PCCR_RSZ_CLK_ENABLE | DM365_ISP5_PCCR_IPIPE_CLK_ENABLE | DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE | DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR); isp5_write((isp5_read(DM365_ISP5_BCR) | DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR); isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1); isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2); isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3); } else oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow; pm_runtime_enable(&pdev->dev); pm_runtime_get(&pdev->dev); spin_lock_init(&oper_cfg.vpss_lock); dev_info(&pdev->dev, "%s vpss probe success\n", platform_name); return 0; }