int misc_init_r (void) { unsigned long CPC0_CR0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); }
/* * Disables the burst on the channel (BTEN bit in the control/count register) * Note: * For scatter/gather dma, this function MUST be called before the * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the * sgl list and used as each sgl element is added. */ int ppc4xx_disable_burst(unsigned int dmanr) { unsigned int ctc; if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr); return DMA_STATUS_BAD_CHANNEL; } ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN; mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc); return DMA_STATUS_GOOD; }
static void ppc405_uic_disable(unsigned int irq) { int bit, word; bit = irq & 0x1f; word = irq >> 5; #ifdef UIC_DEBUG printk("ppc405_uic_disable - irq %d word %d bit 0x%x\n", irq, word, bit); #endif ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); switch (word) { case 0: mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]); break; case 1: mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]); break; } }
int misc_init_r (void) { unsigned long cntrl0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00001000); return (0); }
int pci_pre_init(struct pci_controller *hose) { unsigned long addr; /*-------------------------------------------------------------------------+ | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); mtdcr(plb3_acr, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; mtdcr(plb0_acr, addr); /* Segment1 */ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); return 1; }
/* * Sets the burst size (number of peripheral widths) for the channel * (BSIZ bits in the control/count register)) * must be one of: * DMA_CTC_BSIZ_2 * DMA_CTC_BSIZ_4 * DMA_CTC_BSIZ_8 * DMA_CTC_BSIZ_16 * Note: * For scatter/gather dma, this function MUST be called before the * ppc4xx_alloc_dma_handle() func as the chan count register is copied into the * sgl list and used as each sgl element is added. */ int ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize) { unsigned int ctc; if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr); return DMA_STATUS_BAD_CHANNEL; } ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK; ctc |= (bsize & DMA_CTC_BSIZ_MSK); mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc); return DMA_STATUS_GOOD; }
void ppc4xx_set_sg_addr(int dmanr, phys_addr_t sg_addr) { if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { printk("ppc4xx_set_sg_addr: bad channel: %d\n", dmanr); return; } #ifdef PPC4xx_DMA_64BIT mtdcr(DCRN_ASGH0 + (dmanr * 0x8), (u32)(sg_addr >> 32)); #endif mtdcr(DCRN_ASG0 + (dmanr * 0x8), (u32)sg_addr); }
int board_early_init_f(void) { /* taken from PPCBoot */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ return 0; }
int cpci405_version(void) { unsigned long cntrl0Reg; unsigned long value; /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings */ mtdcr(cntrl0, cntrl0Reg); switch (value) { case 0x00180000: /* CS2==1 && CS3==1 -> version 1 */ return 1; case 0x00080000: /* CS2==0 && CS3==1 -> version 2 */ return 2; case 0x00100000: /* CS2==1 && CS3==0 -> version 3 */ return 3; case 0x00000000: /* CS2==0 && CS3==0 -> version 4 */ return 4; default: /* should not be reached! */ return 2; } }
void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr) { if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { printk("set_dst_addr: bad channel: %d\n", dmanr); return; } #ifdef PPC4xx_DMA64BIT mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32)); #else mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr); #endif }
/* ------------------------------------------------------------------------- */ int board_early_init_f (void) { /* Running from ROM: global data is still READONLY */ init_sdram (); mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr (uicer, 0x00000000); /* disable all ints */ mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ mtdcr (uictr, 0x10000000); /* set int trigger levels */ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; }
int board_early_init_f(void) { mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ /* * Configure CPC0_PCI to enable PerWE as output */ mtdcr(CPC0_PCI, CPC0_PCI_SPE); return 0; }
/* * Determine device configuration for a machine. */ void cpu_configure(void) { intr_init(); calc_delayconst(); /* Make sure that timers run at CPU frequency */ mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE); if (config_rootfound("plb", NULL) == NULL) panic("configure: mainbus not configured"); (void)spl0(); }
int board_early_init_f (void) { /* * First pull fpga-prg pin low, to disable fpga logic */ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ out_be32((void*)GPIO0_OR, 0); /* pull prg low */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks */ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * New boards have a single 32MB flash connected to CS0 * instead of two 16MB flashes on CS0+1. */ if (board_revision() >= 8) { /* disable CS1 */ mtebc(PB1AP, 0); mtebc(PB1CR, 0); /* resize CS0 to 32MB */ mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8); mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8); } return 0; }
int misc_init_r (void) { unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; /* * Select cts (and not dsr) on uart1 */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); }
int board_early_init_f (void) { /* * Interrupt controller setup for the HCU4 board. * Note: IRQ 0-15 405GP internally generated; high; level sensitive * IRQ 16 405GP internally generated; low; level sensitive * IRQ 17-24 RESERVED/UNUSED * IRQ 31 (EXT IRQ 6) (unused) */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ mtdcr(uictr, 0x00000000); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(CPC0_CR1, CPC0_CR1_VALUE); mtdcr(CPC0_ECR, 0x60606000); mtdcr(CPC0_EIRR, 0x7C000000); return 0; }
int board_early_init_f (void) { /*-------------------------------------------------------------------------+ | Interrupt controller setup for the ERIC board. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | IRQ 16 405GP internally generated; active low; level sensitive | IRQ 17-24 RESERVED | IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive | IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive | IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive | indicates NO Power or HOST RESET active | check GPIO7 (HOST RESET#) and GPIO8 (NO Power#) | for real IRQ source | IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive | IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR, | else tristate) | Note for ERIC board: | An interrupt taken for the HOST (IRQ 28) indicates that | the HOST wrote a "1" to one of the following locations | - VGA CRT_GPIO0 (if R1216 is loaded) | - VGA CRT_GPIO1 (if R1217 is loaded) | +-------------------------------------------------------------------------*/ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr (UIC0ER, 0x00000000); /* disable all ints */ mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */ mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ out32 (PPC405GP_GPIO0_TCR, 0x7E400000); return 0; }
int board_early_init_f(void) { mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000010); mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; }
int __ft_board_setup(void *blob, bd_t *bd) { int rc; int i; u32 bxcr; u32 ranges[EBC_NUM_BANKS * 4]; u32 *p = ranges; char ebc_path[] = "/plb/opb/ebc"; ft_cpu_setup(blob, bd); /* * Read 4xx EBC bus bridge registers to get mappings of the * peripheral banks into the OPB/PLB address space */ for (i = 0; i < EBC_NUM_BANKS; i++) { mtdcr(EBC0_CFGADDR, EBC_BXCR(i)); bxcr = mfdcr(EBC0_CFGDATA); if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) { *p++ = i; *p++ = 0; *p++ = bxcr & EBC_BXCR_BAS_MASK; *p++ = EBC_BXCR_BANK_SIZE(bxcr); } } #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE /* Update reg property in all nor flash nodes too */ fdt_fixup_nor_flash_size(blob); #endif /* Some 405 PPC's have EBC as direct PLB child in the dts */ if (fdt_path_offset(blob, ebc_path) < 0) strcpy(ebc_path, "/plb/ebc"); rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges, (p - ranges) * sizeof(u32), 1); if (rc) { printf("Unable to update property EBC mappings, err=%s\n", fdt_strerror(rc)); } return 0; }
int checkboard (void) { u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER); u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION); u16 generation = boardVersReg & 0x0f; u16 index = boardVersReg & 0xf0; /* Cannot be done in board_early_init */ mtdcr(CPC0_CR0, CPC0_CR0_VALUE); /* Force /RTS to active. The board it not wired quite * correctly to use cts/rtc flow control, so just force the * /RST active and forget about it. */ writeb (readb (0xef600404) | 0x03, 0xef600404); nm_show_print(generation, index, hwConfig); return 0; }
/* * Board-specific pci initialization * Platform code can reimplement pci_pre_init() if needed */ int __pci_pre_init(struct pci_controller *hose) { #if defined(CONFIG_405EP) /* * Enable the internal PCI arbiter by default. * * On 405EP CPUs the internal arbiter can be controlled * by the I2C strapping EEPROM. If you want to do so * or if you want to disable the arbiter pci_pre_init() * must be reimplemented without enabling the arbiter. * The arbiter is enabled in this place because of * compatibility reasons. */ mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ return 1; }
void __init ppc4xx_pic_init(void) { int i; /* * Disable all external interrupts until they are * explicity requested. */ ppc_cached_irq_mask[0] = 0; mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]); ppc_md.get_irq = ppc403_pic_get_irq; for (i = 0; i < NR_IRQS; i++) irq_desc[i].chip = &ppc403_aic; }
/* * Handle external interrupts */ void external_interrupt(struct pt_regs *regs) { u32 uic_msr; /* * Read masked interrupt status register to determine interrupt source */ uic_msr = mfdcr(uic0msr); mtdcr(uic0sr, (uic_msr & UICB0_ALL)); if (uic_msr & ~(UICB0_ALL)) { uic_interrupt(UIC0_DCR_BASE, 0); } return; }
/* * Enable (start) the DMA described by the sgl handle. */ static __inline__ void ppc4xx_enable_dma_sgl(sgl_handle_t handle) { sgl_list_info_t *psgl = (sgl_list_info_t *) handle; ppc_dma_ch_t *p_dma_ch; uint32_t sg_command; if (!handle) { printk("ppc4xx_enable_dma_sgl: null handle\n"); return; } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", psgl->dmanr); return; } else if (!psgl->phead) { printk("ppc4xx_enable_dma_sgl: sg list empty\n"); return; } p_dma_ch = &dma_channels[psgl->dmanr]; psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */ sg_command = mfdcr(DCRN_ASGC); ppc4xx_set_sg_addr(psgl->dmanr, iopa((unsigned long)psgl->phead)); switch (psgl->dmanr) { case 0: sg_command |= SSG0_ENABLE; break; case 1: sg_command |= SSG1_ENABLE; break; case 2: sg_command |= SSG2_ENABLE; break; case 3: sg_command |= SSG3_ENABLE; break; default: printk("ppc4xx_enable_dma_sgl: bad channel: %d\n", psgl->dmanr); } mtdcr(DCRN_ASGC, sg_command); /* start transfer */ }
/* * Halt an active scatter/gather DMA operation. */ void ppc4xx_disable_dma_sgl(sgl_handle_t handle) { sgl_list_info_t *psgl = (sgl_list_info_t *) handle; uint32_t sg_command; if (!handle) { printk("ppc4xx_enable_dma_sgl: null handle\n"); return; } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) { printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n", psgl->dmanr); return; } sg_command = mfdcr(DCRN_ASGC); sg_command &= ~SSG_ENABLE(psgl->dmanr); mtdcr(DCRN_ASGC, sg_command); /* stop transfer */ }
/* * Disables the channel interrupt. * * If performing a scatter/gatter transfer, this function * MUST be called before calling alloc_dma_handle() and building * the sgl list. Otherwise, interrupts will not be disabled, if * they were previously enabled. */ int ppc4xx_disable_dma_interrupt(unsigned int dmanr) { unsigned int control; ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) { printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr); return DMA_STATUS_BAD_CHANNEL; } p_dma_ch->int_enable = 0; control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */ mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control); return DMA_STATUS_GOOD; }
int board_early_init_f (void) { unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ CPC0_CR0Reg = mfdcr(CPC0_CR0); mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); /* set output pins to high */ out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); /* setup for output (LED=off) */ out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) unused */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; }
/* * board_early_init_f */ int board_early_init_f(void) { lcd_init(); mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0CR, 0x00000000); mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); /* * Configure CPC0_PCI to enable PerWE as output * and enable the internal PCI arbiter */ mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); return 0; }
/* * board_early_init_f */ int board_early_init_f(void) { lcd_init(); mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ mtdcr(uictr, 0x00000000); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(pb3cr, CFG_EBC_PB3CR); /* * Configure CPC0_PCI to enable PerWE as output * and enable the internal PCI arbiter */ mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); return 0; }
/************************************************************************* * void l2cache_enable() * ************************************************************************/ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ { mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ mtdcr( L2_CACHE_SNP1, 0 ); __asm__ volatile ("sync"); /* msync */ mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ __asm__ volatile ("sync"); }