static int imx51_ccm_probe(struct device_d *dev) { void __iomem *regs; regs = dev_request_mem_region(dev, 0); mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */ return 0; }
static int imx51_ccm_probe(struct device_d *dev) { struct resource *iores; void __iomem *regs; iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) return PTR_ERR(iores); regs = IOMEM(iores->start); mx51_clocks_init(dev, regs); return 0; }
static void __init mx51_babbage_timer_init(void) { struct clk *uart_clk; /* Change the CPU voltages for TO2*/ if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) { cpu_wp_auto[0].cpu_voltage = 1175000; cpu_wp_auto[1].cpu_voltage = 1100000; cpu_wp_auto[2].cpu_voltage = 1000000; } mx51_clocks_init(32768, 24000000, 22579200, 24576000); uart_clk = clk_get(NULL, "uart_clk.0"); early_console_setup(UART1_BASE_ADDR, uart_clk); }
static void __init mx51_babbage_timer_init(void) { struct clk *uart_clk; /* Change the CPU voltages for TO2*/ if (mx51_revision() == IMX_CHIP_REVISION_2_0) { cpu_wp_auto[0].cpu_voltage = 1175000; cpu_wp_auto[1].cpu_voltage = 1100000; cpu_wp_auto[2].cpu_voltage = 1000000; } mx51_clocks_init(32768, 24000000, 22579200, 24576000); uart_clk = clk_get_sys("mxcintuart.0", NULL); early_console_setup(UART1_BASE_ADDR, uart_clk); }
static void __init mx51_efikamx_timer_init(void) { mx51_clocks_init(32768, 24000000, 22579200, 24576000); }
static void __init eukrea_cpuimx51_timer_init(void) { mx51_clocks_init(32768, 24000000, 22579200, 0); }
int __init mx51_clocks_init_dt(void) { return mx51_clocks_init(0, 0, 0, 0); }
static void __init mx51_babbage_timer_init(void) { mx51_clocks_init(32768, 24000000, 22579200, 0); }
static void __init mx51_clocks_init_dt(struct device_node *np) { mx51_clocks_init(0, 0, 0, 0); }