int board_mmc_init(bd_t *bis) { #ifndef CONFIG_SPL_BUILD int ret; int i; for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; #ifndef CONFIG_CMD_NAND case 1: imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); break; #endif default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; #else struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg = readl(&psrc->sbmr1) >> 11; /* * Upon reading BOOT_CFG register the following map is done: * Bit 11 and 12 of BOOT_CFG register can determine the current * mmc port * 0x1 SD1 * 0x2 SD2 * 0x3 SD4 */ switch (reg & 0x3) { case 0x0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); usdhc_cfg[0].max_bus_width = 4; gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; break; } return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); #endif }
int board_mmc_init(bd_t *bis) { enum boot_device dev = get_boot_device(); /* Internal MMC */ switch (dev) { case MX6_SD0_BOOT: /* Internal SD card */ puts("Internal SD card\n"); usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); return fsl_esdhc_initialize(bis, &usdhc3_cfg); case MX6_SD1_BOOT: /* External SD card */ puts("External SD card\n"); usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); return fsl_esdhc_initialize(bis, &usdhc2_cfg); case MX6_SATA_BOOT: puts("Don't yet support booting from SATA\n"); hang(); default: printf("Unrecognized boot source: %d\n", dev); hang(); } return 0; }
int board_mmc_init(bd_t *bis) { int ret; int i; for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 1: SETUP_IOMUX_PADS(usdhc2_pads); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; }
int board_mmc_init(bd_t *bis) { int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: break; case 1: gpio_direction_output(GP_EMMC_RESET, 1); /* de-assert nRESET */ break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); if (ret) return ret; } return 0; }
int board_mmc_init(bd_t *bis) { s32 status = 0; int i; for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; case 1: imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); gpio_direction_input(USDHC3_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); return status; } status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); } return status; }
int board_mmc_init(bd_t *bis) { s32 status = 0; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); usdhc_cfg[0].max_bus_width = 4; usdhc_cfg[1].max_bus_width = 4; for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); break; case 1: imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); return status; } status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); } return status; }
int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); return 0; }
int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t sd1_pads[] = { NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), MX53_PAD_EIM_DA13__GPIO3_13, }; static const iomux_v3_cfg_t sd2_pads[] = { NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), MX53_PAD_EIM_DA11__GPIO3_11, }; u32 index; int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); break; case 1: imx_iomux_v3_setup_multiple_pads(sd2_pads, ARRAY_SIZE(sd2_pads)); break; default: printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); if (ret) return ret; } return 0; }
int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); #endif #endif return 0; }
int board_mmc_init(bd_t *bis) { int ret = 0; imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); ret |= fsl_esdhc_initialize(bis, &usdhc_cfg[0]); ret |= fsl_esdhc_initialize(bis, &usdhc_cfg[1]); return ret; }
int board_mmc_init(bd_t *bis) { printf("%s:\n", __func__ ); #if !defined(CONFIG_REV2) usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); #else usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); #endif return fsl_esdhc_initialize(bis, &usdhc_cfg); }
/* * Dump some core clockes. */ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 addr = 0; u32 freq; freq = decode_pll(PLL_A7_SPLL); printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000); freq = decode_pll(PLL_A7_APLL); printf("PLL_A7_APLL %8d MHz\n", freq / 1000000); freq = decode_pll(PLL_USB); printf("PLL_USB %8d MHz\n", freq / 1000000); printf("\n"); printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000); addr = (u32) clock_init; printf("[%s] addr = 0x%08X\r\n", __func__, addr); scg_a7_info(); return 0; }
int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_USDHC gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); #else gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); #endif #endif #ifdef CONFIG_IMX_MMC gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); /////// #endif return 0; }
int board_mmc_init(bd_t *bis) { int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); gpio_direction_output(USDHC1_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC1_PWR_GPIO, 1); break; case 1: #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) imx_iomux_v3_setup_multiple_pads( usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); #else imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board\n", i + 1); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); } } return 0; }
int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
int board_mmc_init(bd_t *bis) { printf("%s:\n", __func__ ); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); gpio_set_value(GP_EMMC_RESET, 1); /* release reset */ return fsl_esdhc_initialize(bis, &usdhc_cfg); }
int board_mmc_init(bd_t *bis) { int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) * mmc0 USDHC1 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); return 0; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); return ret; } } return 0; }
int board_mmc_init(bd_t *bis) { SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
static void set_ata_bus_timing(unsigned char mode) { uint32_t val; uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); struct mxc_ata_config_regs *ata_regs; ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; if (mode >= NR_PIO_SPECS) return; /* Write TIME_OFF/ON/1/2W */ val = (3 << REG2OFF(&ata_regs->time_off)) | (3 << REG2OFF(&ata_regs->time_on)) | (((pio_t1[mode] + T) / T) << REG2OFF(&ata_regs->time_1)) | (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2w)); writel(val, &ata_regs->time_off); /* Write TIME_2R/AX/RDX/4 */ val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2r)) | (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_regs->time_ax)) | (1 << REG2OFF(&ata_regs->time_pio_rdx)) | (((pio_t4[mode] + T) / T) << REG2OFF(&ata_regs->time_4)); writel(val, &ata_regs->time_2r); /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_regs->time_9)); writel(val, &ata_regs->time_9); }
int board_mmc_init(bd_t *bis) { int i, ret; /* USDHC1 is mmc0 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board\n", i + 1); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; }
/* * Calculate and set proper clock divider */ static void i2c_imx_set_clk(unsigned int rate) { struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; unsigned int i2c_clk_rate; unsigned int div; int i; #if defined(CONFIG_MX31) struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE; /* start the required I2C clock */ writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), &sc_regs->cgr0); #endif /* Divider value calculation */ i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); div = (i2c_clk_rate + rate - 1) / rate; if (div < i2c_clk_div[0][0]) i = 0; else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) i = ARRAY_SIZE(i2c_clk_div) - 1; else for (i = 0; i2c_clk_div[i][0] < div; i++) ; /* Store divider value */ clk_idx = i2c_clk_div[i][1]; writeb(clk_idx, &i2c_regs->ifdr); }
static inline unsigned long long us_to_tick(unsigned long long usec) { usec = usec * mxc_get_clock(MXC_IPG_CLK) + 999999; do_div(usec, 1000000); return usec; }
static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; do_div(tick, mxc_get_clock(MXC_IPG_CLK)); return tick; }
static int set_otp_timing(void) { u32 clk_rate = 0; u32 relax, strobe_read, strobe_prog; u32 timing = 0; /* get clock */ clk_rate = mxc_get_clock(MXC_IPG_CLK); if (clk_rate == -1) { printf("ERROR: mxc_get_clock failed\n"); return -1; } log("clk_rate: %d.", clk_rate); relax = clk_rate / (1000000000 / DEF_RELAX) - 1; strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; timing = BF(relax, OCOTP_TIMING_RELAX); timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); log("timing: 0x%X", timing); writel(timing, IMX_OTP_BASE + HW_OCOTP_TIMING); return 0; }
int board_mmc_init(bd_t *bis) { int ret; static const iomux_v3_cfg_t sd3_pads[] = { NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (ret) return ret; return 0; }
int board_mmc_init(bd_t *bis) { cm_fx6_set_usdhc_iomux(); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg); }
int board_mmc_init(bd_t *bis) { s32 status = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | fsl_esdhc_initialize(bis, &usdhc_cfg[1]); return status; }
int board_mmc_init(bd_t *bis) { int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-Boot device node) (Physical Port) * mmc0 USDHC3 * mmc1 USDHC4 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); gpio_direction_input(USDHC3_CD_GPIO); /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/ gpio_direction_output(USDHC3_RST_GPIO, 0); udelay(1000); /* need 1ms at least */ gpio_direction_output(USDHC3_RST_GPIO, 1); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 1: imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); gpio_direction_input(USDHC4_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board\n", i + 1); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); return ret; } } return 0; }
int board_mmc_init(bd_t *bis) { SETUP_IOMUX_PADS(usdhc2_pads); usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
int board_mmc_init(bd_t *bis) { /* Only one USDHC controller on Ventana */ SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg.max_bus_width = 4; return fsl_esdhc_initialize(bis, &usdhc_cfg); }