static int host1x_tickctrl_init_channel(struct platform_device *dev)
{
struct nvhost_device_data *pdata = platform_get_drvdata(dev);
void __iomem *regs = pdata->channel->aperture;
nvhost_module_busy(nvhost_get_parent(dev));
/* Initialize counter */
writel(0, regs + host1x_channel_tickcount_hi_r());
writel(0, regs + host1x_channel_tickcount_lo_r());
writel(0, regs + host1x_channel_stallcount_hi_r());
writel(0, regs + host1x_channel_stallcount_lo_r());
writel(0, regs + host1x_channel_xfercount_hi_r());
writel(0, regs + host1x_channel_xfercount_lo_r());
writel(host1x_channel_channelctrl_enabletickcnt_f(1),
regs + host1x_channel_channelctrl_r());
writel(host1x_channel_stallctrl_enable_channel_stall_f(1),
regs + host1x_channel_stallctrl_r());
writel(host1x_channel_xferctrl_enable_channel_xfer_f(1),
regs + host1x_channel_xferctrl_r());
nvhost_module_idle(nvhost_get_parent(dev));
host1x_tickctrl_debug_init(dev);
return 0;
}
static int host1x_tickctrl_xfercount(struct platform_device *dev, u64 *val)
{
struct nvhost_device_data *pdata = platform_get_drvdata(dev);
void __iomem *regs = pdata->channel->aperture;
nvhost_module_busy(nvhost_get_parent(dev));
*val = readl64(regs + host1x_channel_xfercount_hi_r(),
regs + host1x_channel_xfercount_lo_r());
rmb();
nvhost_module_idle(nvhost_get_parent(dev));
return 0;
}
static void host1x_tickctrl_deinit_channel(struct platform_device *dev)
{
struct nvhost_device_data *pdata = platform_get_drvdata(dev);
void __iomem *regs = pdata->channel->aperture;
nvhost_module_busy(nvhost_get_parent(dev));
writel(host1x_channel_stallctrl_enable_channel_stall_f(0),
regs + host1x_channel_stallctrl_r());
writel(host1x_channel_xferctrl_enable_channel_xfer_f(0),
regs + host1x_channel_xferctrl_r());
writel(host1x_channel_channelctrl_enabletickcnt_f(0),
regs + host1x_channel_channelctrl_r());
nvhost_module_idle(nvhost_get_parent(dev));
}
u32 nvhost_syncpt_read_ext(struct platform_device *dev, u32 id)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
BUG_ON(!nvhost_get_parent(dev));
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
return nvhost_syncpt_read(sp, id);
}
void nvhost_syncpt_cpu_incr_ext(struct platform_device *dev, u32 id)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
BUG_ON(!nvhost_get_parent(dev));
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
nvhost_syncpt_cpu_incr(sp, id);
}
int nvhost_syncpt_wait_timeout_ext(struct platform_device *dev, u32 id,
u32 thresh, u32 timeout, u32 *value)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
BUG_ON(!nvhost_get_parent(dev));
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
return nvhost_syncpt_wait_timeout(sp, id, thresh, timeout, value);
}
static irqreturn_t tegra_dc_irq(int irq, void *ptr)
{
#ifndef CONFIG_TEGRA_FPGA_PLATFORM
struct tegra_dc *dc = ptr;
unsigned long status;
unsigned long underflow_mask;
u32 val;
if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
WARN(1, "IRQ when DC not powered!\n");
tegra_dc_io_start(dc);
status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
tegra_dc_io_end(dc);
return IRQ_HANDLED;
}
/* clear all status flags except underflow, save those for the worker */
status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
/*
* Overlays can get thier internal state corrupted during and underflow
* condition. The only way to fix this state is to reset the DC.
* if we get 4 consecutive frames with underflows, assume we're
* hosed and reset.
*/
underflow_mask = status & ALL_UF_INT;
/* Check underflow */
if (underflow_mask) {
dc->underflow_mask |= underflow_mask;
schedule_delayed_work(&dc->underflow_work,
msecs_to_jiffies(1));
}
if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
tegra_dc_one_shot_irq(dc, status);
else
tegra_dc_continuous_irq(dc, status);
return IRQ_HANDLED;
#else /* CONFIG_TEGRA_FPGA_PLATFORM */
return IRQ_NONE;
#endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
}
u32 nvhost_syncpt_read_ext(struct platform_device *dev, u32 id)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
if (!nvhost_get_parent(dev)) {
dev_err(&dev->dev, "Read called with wrong dev\n");
return 0;
}
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
return nvhost_syncpt_read(sp, id);
}
void nvhost_syncpt_cpu_incr_ext(struct platform_device *dev, u32 id)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
if (!nvhost_get_parent(dev)) {
dev_err(&dev->dev, "Incr called with wrong dev\n");
return;
}
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
nvhost_syncpt_cpu_incr(sp, id);
}
int nvhost_syncpt_wait_timeout_ext(struct platform_device *dev, u32 id,
u32 thresh, u32 timeout, u32 *value, struct timespec *ts)
{
struct platform_device *pdev;
struct nvhost_syncpt *sp;
if (!nvhost_get_parent(dev)) {
dev_err(&dev->dev, "Wait called with wrong dev\n");
return -EINVAL;
}
/* get the parent */
pdev = to_platform_device(dev->dev.parent);
sp = &(nvhost_get_host(pdev)->syncpt);
return nvhost_syncpt_wait_timeout(sp, id, thresh, timeout, value, ts);
}
