status_t ArchFBArmOmap3::SetVideoMode(int width, int height, int depth) { TRACE("%s: %dx%d@%d\n", __func__, width, height, depth); omap_set_lcd_mode(width, height); omap_attach_framebuffer(fBase, width, height, depth); return B_OK; }
int main(int argc, char **argv) { local_exceptions_init(); // example is too fast/boring with caches on, so don't //mmu_simple_init(); video_init(1280, 1024); rp = graphics_init(FBADDR, WIDTH, HEIGHT, BM_RGB16); omap_attach_framebuffer(0, rp->drawable.bitmap); // also set it to the tv out (top-left corner of same data) omap_attach_framebuffer(VID_VID2 | VID_TVOUT, rp->drawable.bitmap); moveTo(rp, 0, 0); setColour(rp, 0x3e31a2); drawRect(rp, WIDTH, HEIGHT); // setup tasks to run int i; NewList(&tasks); dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n", &tasks, tasks.Head, tasks.Tail, tasks.TailPred); for (i=0;taskinit[i];i++ ){ struct task *t = taskinit[i]; // set initial pc and proc state t->tcb.pc = taskpc[i]; // runs in user mode t->tcb.spsr = 0x10; // initial argument 0 in reg 0 t->tcb.regs[0] = i; t->id = i; int j; for (j=1;j<10;j++) t->tcb.regs[j] = j; // initial stack - 4K each, before 32K of master stack t->tcb.regs[13] = 0x88000000 - 32768 - i*4096; AddTail((struct List *)&tasks, &t->Node); dprintf("adding task %d = %08x pc=%08x sp=%08x\n", i, t, t->tcb.pc, t->tcb.regs[13]); } dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n", &tasks, tasks.Head, tasks.Tail, tasks.TailPred); // set task 0 to `execute first' (it's actually us) thistask = &t1; fptask = 0; irq_new_task(tcb_to_sp(&thistask->tcb)); // add an irq handler for the vsync interrupt (lcd display?) irq_set_handler(INTC_DSS_IRQ, dispc_handler); irq_set_mask(INTC_DSS_IRQ, 1); // disable all but vsync reg32w(DISPC_BASE, DISPC_IRQENABLE, DISPC_VSYNC); reg32w(DISPC_BASE, DISPC_IRQSTATUS, ~0); // dss intterrupt can also receive DSI, so disable those too reg32w(DSI_BASE, DSI_IRQENABLE, 0); reg32w(DSI_BASE, DSI_IRQSTATUS, ~0); dprintf("enabling interrupts\n"); // data barrier for previous register writes asm volatile("dsb"); // turn on irq's, which enables task switching irq_enable(); // jump to user mode - we are now 'task 0' asm volatile("cps #0x10"); asm volatile("ldr sp,=0x88000000 - 32768"); task1(0); return 0; }
int main(int argc, char **argv) { local_exceptions_init(); // example is too fast/boring with caches on, so don't //mmu_simple_init(); video_init(1280, 1024); rp = graphics_init(FBADDR, WIDTH, HEIGHT, BM_RGB16); omap_attach_framebuffer(0, rp->drawable.bitmap); // also set it to the tv out (top-left corner of same data) omap_attach_framebuffer(VID_VID2 | VID_TVOUT, rp->drawable.bitmap); moveTo(rp, 0, 0); setColour(rp, 0x3e31a2); drawRect(rp, WIDTH, HEIGHT); // setup tasks to run int i; NewList(&tasks); dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n", &tasks, tasks.Head, tasks.Tail, tasks.TailPred); for (i=0;taskinit[i];i++ ){ struct task *t = taskinit[i]; // set initial pc and proc state t->tcb.pc = (uint32_t)task; // runs in user mode t->tcb.spsr = 0x10; // initial argument 0 in reg 0 t->tcb.regs[0] = i; t->id = i; int j; for (j=1;j<10;j++) t->tcb.regs[j] = j; // initial stack - 4K each, before 32K of master stack t->tcb.regs[13] = 0x88000000 - 32768 - i*4096; AddTail((struct List *)&tasks, &t->Node); dprintf("adding task %d = %08x pc=%08x sp=%08x\n", i, t, t->tcb.pc, t->tcb.regs[13]); } dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n", &tasks, tasks.Head, tasks.Tail, tasks.TailPred); // set task 0 to `execute first' (it's actually us) thistask = &t1; irq_new_task(tcb_to_sp(&thistask->tcb)); // // Setup timer interrupt via GPTIMER1 // // timer off reg32s(GPTIMER1_BASE, GPT_TCLR, 1, 0); // Sets true 1Khz rate w/ 32768Hz clock: S 16.2.4.3 TRM D reg32w(GPTIMER1_BASE, GPT_TPIR, 232000); reg32w(GPTIMER1_BASE, GPT_TNIR, -768000); reg32w(GPTIMER1_BASE, GPT_TLDR, 0xffffffe0); reg32w(GPTIMER1_BASE, GPT_TCRR, 0xffffffe0); // clear int status bits reg32w(GPTIMER1_BASE, GPT_TISR, ~0); // enable overflow int reg32w(GPTIMER1_BASE, GPT_TIER, OVF_IT_FLAG); // dividisor = 100 -> 10Hz so it's visible reg32w(GPTIMER1_BASE, GPT_TOCR, 0); reg32w(GPTIMER1_BASE, GPT_TOWR, 100); irq_set_handler(INTC_GPT1_IRQ, gptimer1_handler); irq_set_mask(INTC_GPT1_IRQ, 1); // force 32K clock reg32s(0x48004c00, 0x40, 1, 0); // turn timer back on reg32s(GPTIMER1_BASE, GPT_TCLR, 1|2|(2<<10), ~0); dprintf("enabling interrupts\n"); // data barrier for previous register writes asm volatile("dsb"); // turn on irq's, which enables task switching irq_enable(); // jump to user mode - we are now 'task 0' asm volatile("cps #0x10"); asm volatile("ldr sp,=0x88000000 - 32768"); task(0); return 0; }