コード例 #1
0
static void __init omap4_panda_init(void)
{
	int package = OMAP_PACKAGE_CBS;
	int ret;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(board_mux, NULL, package);

	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
	if (ret)
		pr_err("error setting wl12xx data: %d\n", ret);

	omap4_panda_init_rev();
	omap4_panda_i2c_init();
	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
	platform_device_register(&omap_vwlan_device);
	omap_serial_init();
	omap_sdrc_init(NULL, NULL);
	omap4_twl6030_hsmmc_init(mmc);
	omap4_ehci_init();
	usb_musb_init(&musb_board_data);
	omap4_panda_display_init();
}
コード例 #2
0
void __init omap3xxx_clockdomains_init(void)
{
	struct clockdomain **sc;
	unsigned int rev;

	if (!cpu_is_omap34xx())
		return;

	clkdm_register_platform_funcs(&omap3_clkdm_operations);
	clkdm_register_clkdms(clockdomains_common);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		clkdm_register_clkdms(clockdomains_am35x);
		clkdm_register_autodeps(clkdm_am35x_autodeps);
	} else {
		clkdm_register_clkdms(clockdomains_omap3430);

		sc = (rev == OMAP3430_REV_ES1_0) ?
			clockdomains_omap3430es1 : clockdomains_omap3430es2plus;

		clkdm_register_clkdms(sc);
		clkdm_register_autodeps(clkdm_autodeps);
	}

	clkdm_complete_init();
}
コード例 #3
0
/**
 * omap3_opp_init() - initialize omap3 opp table
 */
int __init omap3_opp_init(void)
{
	int r = -ENODEV;

	if (!cpu_is_omap34xx())
		return r;

	if (cpu_is_omap3630())
		r = omap_init_opp_table(omap36xx_opp_def_list,
			ARRAY_SIZE(omap36xx_opp_def_list));
	else if (cpu_is_am33xx()) { /* Modified by MYIR */
		if (omap_rev() != AM335X_REV_ES1_0) {
            r = omap_init_opp_table(am33xx_es2x_opp_def_list,
                ARRAY_SIZE(am33xx_es2x_opp_def_list));
		} else {
			r = omap_init_opp_table(am33xx_opp_def_list,
				ARRAY_SIZE(am33xx_opp_def_list));
		}
		
	} else
		r = omap_init_opp_table(omap34xx_opp_def_list,
			ARRAY_SIZE(omap34xx_opp_def_list));

	return r;
}
コード例 #4
0
ファイル: board-omap4panda.c プロジェクト: 0rt/mpokang_kernel
static void __init omap4_panda_init(void)
{
	int package = OMAP_PACKAGE_CBS;

	omap_emif_setup_device_details(&emif_devices, &emif_devices);

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(board_mux, NULL, package);

	if (wl12xx_set_platform_data(&omap_panda_wlan_data))
		pr_err("error setting wl12xx data\n");

	omap4_panda_i2c_init();
	omap4_audio_conf();
	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
/*
 * 	This is temporaray. With WLAN regsitering, we see that UART2 is not
 * 	idling on panda and CORE RET is not happening. So removing this FTM.
 * 	Later will be enabled.
 *
 *	platform_device_register(&omap_vwlan_device);
 */
	board_serial_init();
	omap4_twl6030_hsmmc_init(mmc);
	omap4_ehci_init();
	usb_musb_init(&musb_board_data);

	omap_dmm_init();
	omap4_panda_display_init();
}
コード例 #5
0
u8 omap_pm_get_max_vdd1_opp()
{
	if (cpu_is_omap3630()) {
		switch (omap_rev_id()) {
		case OMAP_3630:
		default:
			if (sr_read_efuse_nvalues(VDD1_OPP5) != 0)
				return VDD1_OPP5;
			else
		case OMAP_3630_600:
			return VDD1_OPP5;
		case OMAP_3630_800:
			return VDD1_OPP6;
		case OMAP_3630_1000:
			return VDD1_OPP6;
		}

	} else {
		if (omap_rev() < OMAP3430_REV_ES3_1)
			return VDD1_OPP5;
		else {
			switch (omap_rev_id()) {
			case OMAP_3420:
			case OMAP_3430:
				return VDD1_OPP5;
			case OMAP_3440:
				return VDD1_OPP6;
			default:
				return VDD1_OPP5;
			}
		}
	}
}
コード例 #6
0
void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx())
		return;

	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_omap3430_common);

	rev = omap_rev();

	if (rev == OMAP3430_REV_ES1_0)
		pwrdm_register_pwrdms(powerdomains_omap3430es1);
	else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
		 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
		pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
	else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
		 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
		 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
		pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
	else
		WARN(1, "OMAP3 powerdomain init: unknown chip type\n");

	pwrdm_complete_init();
}
コード例 #7
0
ファイル: board-4430sdp.c プロジェクト: BorisTw/BBB-kernel
static void __init omap_4430sdp_init(void)
{
	int status;
	int package = OMAP_PACKAGE_CBS;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(board_mux, NULL, package);

	omap4_i2c_init();
	omap_sfh7741prox_init();
	platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
	omap_serial_init();
	omap_sdrc_init(NULL, NULL);
	omap4_sdp4430_wifi_init();
	omap4_twl6030_hsmmc_init(mmc);

	usb_musb_init(&musb_board_data);

	status = omap_ethernet_init();
	if (status) {
		pr_err("Ethernet initialization failed: %d\n", status);
	} else {
		sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
		spi_register_board_info(sdp4430_spi_board_info,
				ARRAY_SIZE(sdp4430_spi_board_info));
	}

	status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
	if (status)
		pr_err("Keypad initialization failed: %d\n", status);

	omap_4430sdp_display_init();
}
コード例 #8
0
/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	clear_cpu_prev_pwrst(cpu);
	set_cpu_next_pwrst(cpu, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
	scu_pwrst_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap_secondary_startup().
	 */
	omap4_finish_suspend(cpu_state);

	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
	return 0;
}
コード例 #9
0
ファイル: pm34xx.c プロジェクト: matianfu/kunlun-kernel
static void omap3_core_save_context(void)
{
	u32 control_padconf_off;

	/* Save the padconf registers */
	control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
	control_padconf_off |= START_PADCONF_SAVE;
	omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
	/* wait for the save to complete */
	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
			& PADCONF_SAVE_DONE))
		udelay(1);

	/*
	 * Force write last pad into memory, as this can fail in some
	 * cases according to erratas 1.157, 1.185
	 */
	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);

	/*
	 * override the value saved in scratchpad memory, errata i583
	 */
	if (omap_rev() <= OMAP3630_REV_ES1_1)
		omap_ctrl_writew(0x1f, OMAP343X_CONTROL_MEM_WKUP +
			OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET);

	/* Save the Interrupt controller context */
	omap_intc_save_context();
	/* Save the GPMC context */
	omap3_gpmc_save_context();
	/* Save the system control module context, padconf already save above*/
	omap3_control_save_context();
}
コード例 #10
0
static void __init omap_tablet_init(void)
{
	int status;
	int package = OMAP_PACKAGE_CBS;
	int tablet_rev = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(board_mux, NULL, package);

	omap_emif_setup_device_details(&emif_devices, &emif_devices);

	omap_board_config = tablet_config;
	omap_board_config_size = ARRAY_SIZE(tablet_config);
	tablet_rev = omap_init_board_version(0);
	omap4_create_board_props();
	omap4_audio_conf();
	omap4_i2c_init();
	tablet_touch_init();
	tablet_camera_mux_init();
	omap_dmm_init();
	tablet_panel_init();
	tablet_pmic_mux_init();
	tablet_set_osc_timings();
	tablet_button_init();
	omap4_register_ion();
	board_serial_init();
	omap4_tablet_wifi_init();
	omap4_twl6030_hsmmc_init(mmc);
	tablet_sensor_init();
	platform_add_devices(tablet4430_devices,
			ARRAY_SIZE(tablet4430_devices));
	wake_lock_init(&st_wk_lock, WAKE_LOCK_SUSPEND, "st_wake_lock");
	omap4_ehci_ohci_init();
	usb_musb_init(&musb_board_data);

	status = omap_ethernet_init();
	if (status) {
		pr_err("Ethernet initialization failed: %d\n", status);
	} else {
		tablet_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
		spi_register_board_info(tablet_spi_board_info,
				ARRAY_SIZE(tablet_spi_board_info));
	}

	if (cpu_is_omap446x()) {
		/* Vsel0 = gpio, vsel1 = gnd */
		status = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
					OMAP_PIN_OFF_OUTPUT_HIGH, -1);
		if (status)
			pr_err("TPS62361 initialization failed: %d\n", status);
	}

	omap_enable_smartreflex_on_init();
        if (enable_suspend_off)
                omap_pm_enable_off_mode();

}
コード例 #11
0
static void __init zoom_lcd_panel_init(void)
{
	zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
			LCD_PANEL_RESET_GPIO_PROD :
			LCD_PANEL_RESET_GPIO_PILOT;

	if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios)))
		pr_err("%s: Failed to get LCD GPIOs.\n", __func__);
}
コード例 #12
0
ファイル: board-3430sdp.c プロジェクト: 01org/KVMGT-kernel
static void __init board_smc91x_init(void)
{
	if (omap_rev() > OMAP3430_REV_ES1_0)
		board_smc91x_data.gpio_irq = 6;
	else
		board_smc91x_data.gpio_irq = 29;

	gpmc_smc91x_init(&board_smc91x_data);
}
コード例 #13
0
static void __init omap4_panda_init(void)
{
	int package = OMAP_PACKAGE_CBS;
	int ret;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;

	omap_emif_set_device_details(1, &lpddr2_elpida_2G_S4_x2_info,
			lpddr2_elpida_2G_S4_timings,
			ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
			&lpddr2_elpida_S4_min_tck,
			&custom_configs);

	omap_emif_set_device_details(2, &lpddr2_elpida_2G_S4_x2_info,
			lpddr2_elpida_2G_S4_timings,
			ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
			&lpddr2_elpida_S4_min_tck,
			&custom_configs);

	if (cpu_is_omap446x())
		gpio_leds[0].gpio = 110;

	omap4_mux_init(board_mux, NULL, package);

	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);

	omap_register_mac_device_fixup_paths(panda_fixup_mac_device_paths,
				     ARRAY_SIZE(panda_fixup_mac_device_paths));

	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
	if (ret)
		pr_err("error setting wl12xx data: %d\n", ret);

	omap4_panda_init_rev();
	omap4_panda_i2c_init();
	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
	platform_device_register(&omap_vwlan_device);
	omap_serial_init();
	omap_sdrc_init(NULL, NULL);
	omap4_twl6030_hsmmc_init(mmc);
	omap4_ehci_init();
	usb_musb_init(&musb_board_data);
	omap4_panda_display_init();
#ifdef CONFIG_MACH_OMAP4_PANDA_CAMERA_SUPPORT
	panda_camera_init(&panda_camera_board_info);
#endif
	if (cpu_is_omap446x()) {
		/* Vsel0 = gpio, vsel1 = gnd */
		ret = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
				OMAP_PIN_OFF_OUTPUT_HIGH, -1);
		if (ret)
			pr_err("TPS62361 initialization failed: %d\n", ret);
	}
	omap_enable_smartreflex_on_init();
}
コード例 #14
0
static __init int omap4_ldo_trim_init(void)
{
	u32 bgap_trimmed = 0;

	/* Applicable only for OMAP4 */
	if (!cpu_is_omap44xx())
		return 0;

	/*
	 * Some ES2.2 efuse  values for BGAP and SLDO trim
	 * are not programmed. For these units
	 * 1. we can set overide mode for SLDO trim,
	 * and program the max multiplication factor, to ensure
	 * high enough voltage on SLDO output.
	 * 2. trim VDAC value for TV output as per recomendation
	 */
	if (omap_rev() >= CHIP_IS_OMAP4430ES2_2)
		bgap_trimmed = omap_ctrl_readl(
			OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP);

	bgap_trimmed &= OMAP4_STD_FUSE_OPP_BGAP_MASK_LSB;

	/* if not trimmed, we set force overide, insted of efuse. */
	if (!bgap_trimmed)
		bgap_trim_sw_overide = true;

	/* If not already trimmed, use s/w override */
	if (cpu_is_omap446x())
		omap4460_mpu_dpll_trim_override();

	/*
	 * Errata i684 (revision B)
	 * Impacts all OMAP4430ESx.y trimmed and untrimmed excluding units
	 * with with ProdID[51:50]=11
	 * OMAP4460/70 are not impacted.
	 *
	 * ProdID:
	 * 51 50
	 * 0  0  Incorrect trim, SW WA needed.
	 * 0  1  Fixed test program issue of overlapping of LPDDR & SmartIO
	 *	 efuse fields, SW WA needed for LPDDR.
	 * 1  1  New LPDDR trim formula to compensate for vertical vs horizontal
	 *	 cell layout. No overwrite required.
	 */
	if (cpu_is_omap443x()) {
		u32 prod_id;

		prod_id = omap_ctrl_readl(
				OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
		prod_id &= OMAP4_PROD_ID_I684_MASK;
		if (prod_id != OMAP4_PROD_ID_I684_MASK)
			ddr_io_trim_override = true;
	}

	return omap4_ldo_trim_configure();
}
コード例 #15
0
static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
{
	
	if (omap_rev() == OMAP3430_REV_ES1_0) {
		printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
		       "silicon 'Limitation 2.5' on 3430ES1.\n");
		return -EINVAL;
	}
	return omap3_noncore_dpll_set_rate(clk, rate);
}
コード例 #16
0
ファイル: timer-mpu.c プロジェクト: andi34/Dhollmen_Kernel
/*
 * Setup the local clock events for a CPU.
 */
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
	/* Local timers are not supprted on OMAP4430 ES1.0 */
	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
	twd_timer_setup(evt);
	return 0;
}
コード例 #17
0
ファイル: lcd_2430sdp.c プロジェクト: percy-g2/rowboat-kernel
static void sdp2430_panel_disable(struct lcd_panel *panel)
{
	gpio_set_value(enable_gpio, 0);
	gpio_set_value(backlight_gpio, 0);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
		mdelay(4);
	}
}
コード例 #18
0
static void sdp3430_panel_disable_dvi(struct omap_display *display)
{
	dvi_enabled = 0;

	if (omap_rev() > OMAP3430_REV_ES1_0) {
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
		mdelay(4);
	}
}
コード例 #19
0
/*
 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 * @clk: struct clk * of DPLL to set
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 * @freqsel: FREQSEL value to set
 *
 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 * lock..  Returns -EINVAL upon error, or 0 upon success.
 */
static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
	struct dpll_data *dd;
	u32 v;

	if (!clk)
		return -EINVAL;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	/*
	 * According to the 12-5 CDP code from TI, "Limitation 2.5"
	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
	 * on DPLL4.
	 */
	if (omap_rev() == OMAP3430_REV_ES1_0 &&
	    !strcmp("dpll4_ck", clk->name)) {
		printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
		       "silicon 'Limitation 2.5' on 3430ES1.\n");
		return -EINVAL;
	}

	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
	_omap3_noncore_dpll_bypass(clk);

	/* Set jitter correction */
	v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
	v &= ~dd->freqsel_mask;
	v |= freqsel << __ffs(dd->freqsel_mask);
	cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);

	/* Set DPLL multiplier, divider */
	v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
	v &= ~(dd->mult_mask | dd->div1_mask);
	v |= m << __ffs(dd->mult_mask);
	v |= (n - 1) << __ffs(dd->div1_mask);
	if (dd->jtype) {
		u8 dco, sd_div;
		lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
		v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
		v |=  dco << __ffs(dd->dco_sel_mask);
		v |=  sd_div << __ffs(dd->sd_div_mask);
	}
	cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);

	/* We let the clock framework set the other output dividers later */

	/* REVISIT: Set ramp-up delay? */

	_omap3_noncore_dpll_lock(clk);

	return 0;
}
コード例 #20
0
/*
 * Initialise the wakeupgen module.
 */
int __init omap_wakeupgen_init(void)
{
	int i;
	unsigned int boot_cpu = smp_processor_id();

	/* Not supported on OMAP4 ES1.0 silicon */
	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
		return -EPERM;
	}

	/* Static mapping, never released */
	wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
	if (WARN_ON(!wakeupgen_base))
		return -ENOMEM;

	if (cpu_is_omap44xx()) {
		irq_banks = OMAP4_NR_BANKS;
		max_irqs = OMAP4_NR_IRQS;
		omap_secure_apis = 1;
	} else if (soc_is_am43xx()) {
		irq_banks = AM43XX_NR_REG_BANKS;
		max_irqs = AM43XX_IRQS;
	}

	/* Clear all IRQ bitmasks at wakeupGen level */
	for (i = 0; i < irq_banks; i++) {
		wakeupgen_writel(0, i, CPU0_ID);
		if (!soc_is_am43xx())
			wakeupgen_writel(0, i, CPU1_ID);
	}

	/*
	 * Override GIC architecture specific functions to add
	 * OMAP WakeupGen interrupt controller along with GIC
	 */
	gic_arch_extn.irq_mask = wakeupgen_mask;
	gic_arch_extn.irq_unmask = wakeupgen_unmask;
	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;

	/*
	 * FIXME: Add support to set_smp_affinity() once the core
	 * GIC code has necessary hooks in place.
	 */

	/* Associate all the IRQs to boot CPU like GIC init does. */
	for (i = 0; i < max_irqs; i++)
		irq_target_cpu[i] = boot_cpu;

	irq_hotplug_init();
	irq_pm_init();

	return 0;
}
コード例 #21
0
ファイル: cache-l2x0.c プロジェクト: egonalter/R-Link_kernel
static void debug_writel(unsigned long val)
{
	extern void omap_smc1(u32 fn, u32 arg);

	/*
	 * Texas Instrument secure monitor api to modify the
	 * PL310 Debug Control Register.
	 */
	if (omap_rev() == OMAP4430_REV_ES1_0)
		omap_smc1(0x100, val);
}
コード例 #22
0
ファイル: omap_hsi.c プロジェクト: SciAps/android-kernel
static u32 omap_hsi_configure_errata(void)
{
	u32 errata = 0;

	if (cpu_is_omap44xx())
		SET_HSI_ERRATA(errata, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP);

	if (cpu_is_omap44xx() ||
	    (cpu_is_omap54xx() && (omap_rev() <= OMAP5430_REV_ES1_0))) {
		SET_HSI_ERRATA(errata, HSI_ERRATUM_i696_SW_RESET_FSM_STUCK);
		SET_HSI_ERRATA(errata, HSI_ERRATUM_i702_PM_HSI_SWAKEUP);
	}

	if (cpu_is_omap44xx() &&
		(omap_rev() > OMAP4430_REV_ES1_0))
		SET_HSI_ERRATA(errata,
				HSI_ERRATUM_i646_ERROR_COUNTERS_DISABLED);

	return errata;
}
コード例 #23
0
ファイル: board-nooktablet.c プロジェクト: Ntemis/Bexus-N
static void __init acclaim_init(void)
{
	int status;
	int package = OMAP_PACKAGE_CBS;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(acclaim_board_mux, NULL, package);

	acclaim_board_init();
	acclaim_ram_init ();
	omap4_create_board_props();
	acclaim_set_osc_timings();
	acclaim_i2c_init();
	acclaim_enable_rtc_gpio();
	omap4_register_ion();
	platform_add_devices(acclaim_devices, ARRAY_SIZE(acclaim_devices));
	
#ifdef CONFIG_CHARGER_MAX8903	
	acclaim_init_charger();
#endif
	
	acclaim_serial_init();

	acclaim_twl6030_hsmmc_init(mmc);
	acclaim_wifi_init();
#ifdef CONFIG_INPUT_KXTF9
	kxtf9_dev_init();
#endif
	
#ifdef CONFIG_INPUT_KXTJ9
	kxtj9_dev_init();
#endif

#ifdef CONFIG_BATTERY_MAX17042
	acclaim_max17042_dev_init();
#endif
	acclaim_ehci_ohci_init();

	usb_musb_init(&musb_board_data);

	keyboard_mux_init();
	status = omap4_keyboard_init(&acclaim_keypad_data);
	if (status)
		pr_err("Keypad initialization failed: %d\n", status);
	omap_dmm_init();
	acclaim_panel_init();
	omap_enable_smartreflex_on_init();
	if (enable_suspend_off)
		omap_pm_enable_off_mode();

}
コード例 #24
0
static int __init omap_l2_cache_init(void)
{
	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	BUG_ON(!l2cache_base);

	if (omap_rev() != OMAP4430_REV_ES1_0) {
		/* Set POR through PPA service only in EMU/HS devices */
		if (omap_type() != OMAP2_DEVICE_TYPE_GP)
			omap4_secure_dispatcher(
				PPA_SERVICE_PL310_POR, 0x7, 1,
				PL310_POR, 0, 0, 0);
		else
			omap_smc1(0x113, 0x7);

		omap_smc1(0x109, OMAP4_L2X0_AUXCTL_VALUE);
	}

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	/*
	 * 32KB way size, 16-way associativity,
	 * parity disabled
	 */
	if (omap_rev() == OMAP4430_REV_ES1_0)
		l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
	else
		l2x0_init(l2cache_base, OMAP4_L2X0_AUXCTL_VALUE, 0xd0000fff);

	return 0;
}
コード例 #25
0
static void sdp3430_panel_disable_lcd(struct omap_display *display)
{
	lcd_enabled = 0;

	gpio_direction_output(enable_gpio, 0);
	gpio_direction_output(backlight_gpio, 0);

	if (omap_rev() > OMAP3430_REV_ES1_0) {
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
		t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
		mdelay(4);
	}
}
コード例 #26
0
static void irq_save_context(void)
{
	u32 i, val;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return;

	if (!sar_base)
		sar_base = omap4_get_sar_ram_base();

	for (i = 0; i < NR_REG_BANKS; i++) {
		/*                                               */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);

		/*
                                                        
                                                          
                                                          
                                                           
                                                   
   */
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/*                         */
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);

	/*                               */
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);

	/*                               */
	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);

	/*                                */
	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
コード例 #27
0
/*
 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
 * ROM code. WakeupGen IP is integrated along with GIC to manage the
 * interrupt wakeups from CPU low power states. It manages
 * masking/unmasking of Shared peripheral interrupts(SPI). So the
 * interrupt enable/disable control should be in sync and consistent
 * at WakeupGen and GIC so that interrupts are not lost.
 */
static void irq_save_context(void)
{
	u32 i, val;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return;

	if (!sar_base)
		sar_base = omap4_get_sar_ram_base();

	for (i = 0; i < NR_REG_BANKS; i++) {
		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);

		/*
		 * Disable the secure interrupts for CPUx. The restore
		 * code blindly restores secure and non-secure interrupt
		 * masks from SAR RAM. Secure interrupts are not suppose
		 * to be enabled from HLOS. So overwrite the SAR location
		 * so that the secure interrupt remains disabled.
		 */
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/* Save AuxBoot* registers */
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);

	/* Save SyncReq generation logic */
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);

	/* Save SyncReq generation logic */
	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);

	/* Set the Backup Bit Mask status */
	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
}
コード例 #28
0
static void __init omap5evm_modem_pad_conf_enable(void)
{
	/*
	 * Modem pad conf:
	 * UART pads are already configured by serial driver
	 * HSI pads are already configured by HSI driver
	 * I2S pads are already configured by audio soc driver
	 */

	pr_info("%s: Configure PADs for modem connection\n", __func__);

	/* GPIO_MOD_RESOUT2 */
	/* This pad should be wakeup capable to detect a modem reboot */
	/* Note: The WAKEUPENABLE bit is set later to get the WAKEUPEVENT
	 * cleared only when necessary */
	omap_mux_init_gpio(OMAP5_GPIO_MOD_RESOUT2, \
		OMAP_PIN_INPUT_PULLDOWN | \
		OMAP_PIN_OFF_NONE);

	/* GPIO_MOD_PWR_STATUS */
	omap_mux_init_gpio(OMAP5_GPIO_MDM_PWRSTATE, \
			OMAP_PIN_INPUT_PULLDOWN | \
			OMAP_PIN_OFF_NONE);

	/* GPIO_MOD_ON (ONSWC) */
	if (cpu_is_omap54xx() &&
		(omap_rev() == OMAP5430_REV_ES1_0 ||
		omap_rev() == OMAP5432_REV_ES1_0)) {
		omap_mux_init_gpio(OMAP5_GPIO_MDM_ONSWC, \
				OMAP_PIN_INPUT_PULLUP | \
				OMAP_PIN_OUTPUT | \
				OMAP_PIN_OFF_NONE);
	} else {
		omap_mux_init_gpio(OMAP5_GPIO_MDM_ONSWC, \
				OMAP_PIN_OUTPUT | \
				OMAP_PIN_OFF_NONE);
	}
}
コード例 #29
0
static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
{
	/*
	 * According to the 12-5 CDP code from TI, "Limitation 2.5"
	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
	 * on DPLL4.
	 */
	if (omap_rev() == OMAP3430_REV_ES1_0) {
		printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
		       "silicon 'Limitation 2.5' on 3430ES1.\n");
		return -EINVAL;
	}
	return omap3_noncore_dpll_set_rate(clk, rate);
}
コード例 #30
0
ファイル: pm34xx.c プロジェクト: arnd/linux-2.6
static int _prcm_int_handle_wakeup(void)
{
	int c;

	c = prcm_clear_mod_irqs(WKUP_MOD, 1);
	c += prcm_clear_mod_irqs(CORE_MOD, 1);
	c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		c += prcm_clear_mod_irqs(CORE_MOD, 3);
		c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
	}

	return c;
}