/* Returns non-zero if we have a chipset write-combining problem */
static int have_wc_errata(void)
{
struct pci_dev *dev;
u8 rev;
if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
/*
* ServerWorks LE chipsets < rev 6 have problems with
* write-combining.
*/
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
if (rev <= 5) {
printk(KERN_INFO "ib_mlx4: Serverworks LE rev < 6"
" detected. Write-combining disabled.\n");
pci_dev_put(dev);
return -ENOSYS;
}
}
/* Intel 450NX errata # 23. Non ascending cacheline evictions
to write combining memory may resulting in data corruption */
if (dev->vendor == PCI_VENDOR_ID_INTEL &&
dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
printk(KERN_INFO "ib_mlx4: Intel 450NX MMC detected."
" Write-combining disabled.\n");
pci_dev_put(dev);
return -ENOSYS;
}
pci_dev_put(dev);
}
return 0;
}
void __init
locate_and_init_vga(void *(*sel_func)(void *, void *))
{
struct pci_controller *hose = NULL;
struct pci_dev *dev = NULL;
/* */
if (!sel_func) sel_func = (void *)default_vga_hose_select;
/* */
for(dev=NULL; (dev=pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, dev));) {
if (!hose)
hose = dev->sysdata;
else
hose = sel_func(hose, dev->sysdata);
}
/* */
if (!hose || (conswitchp == &vga_con && pci_vga_hose == hose))
return;
/* */
alpha_vga.start += hose->io_space->start;
alpha_vga.end += hose->io_space->start;
request_resource(hose->io_space, &alpha_vga);
/* */
pci_vga_hose = hose;
take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
}
void intel_detect_pch(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pch;
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
if (pch) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
int id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
}
}
pci_dev_put(pch);
}
}
void intel_detect_pch(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pch;
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
* (which really amounts to a PCH but no South Display).
*/
if (INTEL_INFO(dev)->num_pipes == 0) {
dev_priv->pch_type = PCH_NOP;
return;
}
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
* need to expose ISA bridge to let driver know the real hardware
* underneath. This is a requirement from virtualization team.
*
* In some virtualized environments (e.g. XEN), there is irrelevant
* ISA bridge in the system. To work reliably, we should scan trhough
* all the ISA bridge devices and check for the first match, instead
* of only checking the first one.
*/
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
while (pch) {
struct pci_dev *curr = pch;
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("F
static int
cbb_pci_probe(device_t brdev)
{
const char *name;
uint32_t progif;
uint32_t baseclass;
uint32_t subclass;
/*
* Do we know that we support the chipset? If so, then we
* accept the device.
*/
if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
device_set_desc(brdev, name);
return (BUS_PROBE_DEFAULT);
}
/*
* We do support generic CardBus bridges. All that we've seen
* to date have progif 0 (the Yenta spec, and successors mandate
* this).
*/
baseclass = pci_get_class(brdev);
subclass = pci_get_subclass(brdev);
progif = pci_get_progif(brdev);
if (baseclass == PCIC_BRIDGE &&
subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
device_set_desc(brdev, "PCI-CardBus Bridge");
return (BUS_PROBE_GENERIC);
}
return (ENXIO);
}
static const char *
xhci_pci_match(device_t self)
{
uint32_t device_id = pci_get_devid(self);
switch (device_id) {
case 0x01941033:
return ("NEC uPD720200 USB 3.0 controller");
case 0x1e318086:
return ("Intel Panther Point USB 3.0 controller");
case 0x8c318086:
return ("Intel Lynx Point USB 3.0 controller");
default:
break;
}
if ((pci_get_class(self) == PCIC_SERIALBUS)
&& (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
&& (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
return ("XHCI (generic) USB 3.0 controller");
}
return (NULL); /* dunno */
}
static int
vga_pci_probe(device_t dev)
{
device_t bdev;
int unit;
uint16_t bctl;
switch (pci_get_class(dev)) {
case PCIC_DISPLAY:
break;
case PCIC_OLD:
if (pci_get_subclass(dev) != PCIS_OLD_VGA)
return (ENXIO);
break;
default:
return (ENXIO);
}
/* Probe default display. */
unit = device_get_unit(dev);
bdev = device_get_parent(device_get_parent(dev));
bctl = pci_read_config(bdev, PCIR_BRIDGECTL_1, 2);
if (vga_pci_default_unit < 0 && (bctl & PCIB_BCR_VGA_ENABLE) != 0)
vga_pci_default_unit = unit;
if (vga_pci_default_unit == unit)
device_set_flags(dev, 1);
device_set_desc(dev, "VGA-compatible display");
return (BUS_PROBE_GENERIC);
}
static int
ofw_pcib_probe(device_t dev)
{
char desc[sizeof("OFW PCIe-PCIe bridge")];
const char *dtype, *pbdtype;
#define ISDTYPE(dtype, type) \
(((dtype) != NULL) && strcmp((dtype), (type)) == 0)
if ((pci_get_class(dev) == PCIC_BRIDGE) &&
(pci_get_subclass(dev) == PCIS_BRIDGE_PCI) &&
ofw_bus_get_node(dev) != 0) {
dtype = ofw_bus_get_type(dev);
pbdtype = ofw_bus_get_type(device_get_parent(
device_get_parent(dev)));
snprintf(desc, sizeof(desc), "OFW PCI%s-PCI%s bridge",
ISDTYPE(pbdtype, OFW_TYPE_PCIE) ? "e" : "",
ISDTYPE(dtype, OFW_TYPE_PCIE) ? "e" : "");
device_set_desc_copy(dev, desc);
return (0);
}
#undef ISDTYPE
return (ENXIO);
}
void __init
locate_and_init_vga(void *(*sel_func)(void *, void *))
{
struct pci_controller *hose = NULL;
struct pci_dev *dev = NULL;
/* Default the select function */
if (!sel_func) sel_func = (void *)default_vga_hose_select;
/* Find the console VGA device */
for(dev=NULL; (dev=pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, dev));) {
if (!hose)
hose = dev->sysdata;
else
hose = sel_func(hose, dev->sysdata);
}
/* Did we already initialize the correct one? Is there one? */
if (!hose || (conswitchp == &vga_con && pci_vga_hose == hose))
return;
/* Create a new VGA ioport resource WRT the hose it is on. */
alpha_vga.start += hose->io_space->start;
alpha_vga.end += hose->io_space->start;
request_resource(hose->io_space, &alpha_vga);
/* Set the VGA hose and init the new console. */
pci_vga_hose = hose;
console_lock();
do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
console_unlock();
}
static int
nvme_probe (device_t device)
{
struct _pcsid *ep;
uint32_t devid;
uint16_t subdevice;
devid = pci_get_devid(device);
subdevice = pci_get_subdevice(device);
ep = pci_ids;
while (ep->devid) {
if (nvme_match(devid, subdevice, ep))
break;
++ep;
}
if (ep->desc) {
device_set_desc(device, ep->desc);
return (BUS_PROBE_DEFAULT);
}
#if defined(PCIS_STORAGE_NVM)
if (pci_get_class(device) == PCIC_STORAGE &&
pci_get_subclass(device) == PCIS_STORAGE_NVM &&
pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
device_set_desc(device, "Generic NVMe Device");
return (BUS_PROBE_GENERIC);
}
#endif
return (ENXIO);
}
/*
* Provide a device to "eat" the host->pci bridge devices that show up
* on PCI busses and stop them showing up twice on the probes. This also
* stops them showing up as 'none' in pciconf -l. If the host bridge
* provides an AGP capability then we create a child agp device for the
* agp GART driver to attach to.
*/
static int
pci_hostb_probe(device_t dev)
{
u_int32_t id;
id = pci_get_devid(dev);
switch (id) {
/* VIA VT82C596 Power Managment Function */
case 0x30501106:
return (ENXIO);
default:
break;
}
if (pci_get_class(dev) == PCIC_BRIDGE &&
pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
device_set_desc(dev, "Host to PCI bridge");
device_quiet(dev);
return (-10000);
}
return (ENXIO);
}
static int
nvme_probe (device_t device)
{
struct _pcsid *ep;
u_int32_t type;
type = pci_get_devid(device);
ep = pci_ids;
while (ep->type && ep->type != type)
++ep;
if (ep->desc) {
device_set_desc(device, ep->desc);
return (BUS_PROBE_DEFAULT);
}
#if defined(PCIS_STORAGE_NVM)
if (pci_get_class(device) == PCIC_STORAGE &&
pci_get_subclass(device) == PCIS_STORAGE_NVM &&
pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
device_set_desc(device, "Generic NVMe Device");
return (BUS_PROBE_GENERIC);
}
#endif
return (ENXIO);
}
/* Returns non-zero if we have the write-combining memory type */
static int have_wrcomb(void)
{
struct pci_dev *dev;
dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
if (dev != NULL) {
/*
* ServerWorks LE chipsets < rev 6 have problems with
* write-combining. Don't allow it and leave room for other
* chipsets to be tagged
*/
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
dev->revision <= 5) {
pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
pci_dev_put(dev);
return 0;
}
/*
* Intel 450NX errata # 23. Non ascending cacheline evictions to
* write combining memory may resulting in data corruption
*/
if (dev->vendor == PCI_VENDOR_ID_INTEL &&
dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
pci_dev_put(dev);
return 0;
}
pci_dev_put(dev);
}
return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
}
static const char *
ohci_pci_match(device_t self)
{
u_int32_t device_id = pci_get_devid(self);
switch(device_id) {
case PCI_OHCI_DEVICEID_ALADDIN_V:
return (ohci_device_aladdin_v);
case PCI_OHCI_DEVICEID_AMD756:
return (ohci_device_amd756);
case PCI_OHCI_DEVICEID_USB0670:
return (ohci_device_usb0670);
case PCI_OHCI_DEVICEID_USB0673:
return (ohci_device_usb0673);
case PCI_OHCI_DEVICEID_FIRELINK:
return (ohci_device_firelink);
case PCI_OHCI_DEVICEID_NEC:
return (ohci_device_nec);
default:
if ( pci_get_class(self) == PCIC_SERIALBUS
&& pci_get_subclass(self) == PCIS_SERIALBUS_USB
&& pci_get_progif(self) == PCI_INTERFACE_OHCI) {
return (ohci_device_generic);
}
}
return NULL; /* dunno */
}
static int
eisab_probe(device_t dev)
{
int matched = 0;
/*
* Generic match by class/subclass.
*/
if ((pci_get_class(dev) == PCIC_BRIDGE) &&
(pci_get_subclass(dev) == PCIS_BRIDGE_EISA))
matched = 1;
/*
* Some bridges don't correctly report their class.
*/
switch (pci_get_devid(dev)) {
case 0x04828086: /* may show up as PCI-HOST or 0:0 */
matched = 1;
break;
default:
break;
}
if (matched) {
device_set_desc(dev, "PCI-EISA bridge");
return(-10000);
}
return(ENXIO);
}
void intel_detect_pch (struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pch;
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
* need to expose ISA bridge to let driver know the real hardware
* underneath. This is a requirement from virtualization team.
*/
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
if (pch) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
int id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
}
}
pci_dev_put(pch);
}
}
/* Returns non-zero if we have the write-combining memory type */
static int have_wrcomb(void)
{
struct pci_dev *dev;
u8 rev;
if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
/* ServerWorks LE chipsets < rev 6 have problems with write-combining
Don't allow it and leave room for other chipsets to be tagged */
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
if (rev <= 5) {
printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
pci_dev_put(dev);
return 0;
}
}
/* Intel 450NX errata # 23. Non ascending cacheline evictions to
write combining memory may resulting in data corruption */
if (dev->vendor == PCI_VENDOR_ID_INTEL &&
dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
pci_dev_put(dev);
return 0;
}
pci_dev_put(dev);
}
return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
}
/*
* drm_probe_helper: called by a driver at the end of its probe
* method.
*/
int
drm_probe_helper(device_t kdev, drm_pci_id_list_t *idlist)
{
drm_pci_id_list_t *id_entry;
int vendor, device;
vendor = pci_get_vendor(kdev);
device = pci_get_device(kdev);
if (pci_get_class(kdev) != PCIC_DISPLAY ||
(pci_get_subclass(kdev) != PCIS_DISPLAY_VGA &&
pci_get_subclass(kdev) != PCIS_DISPLAY_OTHER))
return (-ENXIO);
id_entry = drm_find_description(vendor, device, idlist);
if (id_entry != NULL) {
if (device_get_desc(kdev) == NULL) {
DRM_DEBUG("%s desc: %s\n",
device_get_nameunit(kdev), id_entry->name);
device_set_desc(kdev, id_entry->name);
}
return (0);
}
return (-ENXIO);
}
/*
* XXX we need to add a quirk list here for bridges that don't correctly
* report themselves.
*/
static int
isab_pci_probe(device_t dev)
{
int matched = 0;
/*
* Try for a generic match based on class/subclass.
*/
if ((pci_get_class(dev) == PCIC_BRIDGE) &&
(pci_get_subclass(dev) == PCIS_BRIDGE_ISA)) {
matched = 1;
} else {
/*
* These are devices that we *know* are PCI:ISA bridges.
* Sometimes, however, they don't report themselves as
* such. Check in case one of them is pretending to be
* something else.
*/
switch (pci_get_devid(dev)) {
case 0x04848086: /* Intel 82378ZB/82378IB */
case 0x122e8086: /* Intel 82371FB */
case 0x70008086: /* Intel 82371SB */
case 0x71108086: /* Intel 82371AB */
case 0x71988086: /* Intel 82443MX */
case 0x24108086: /* Intel 82801AA (ICH) */
case 0x24208086: /* Intel 82801AB (ICH0) */
case 0x24408086: /* Intel 82801AB (ICH2) */
case 0x00061004: /* VLSI 82C593 */
case 0x05861106: /* VIA 82C586 */
case 0x05961106: /* VIA 82C596 */
case 0x06861106: /* VIA 82C686 */
case 0x153310b9: /* AcerLabs M1533 */
case 0x154310b9: /* AcerLabs M1543 */
case 0x00081039: /* SiS 85c503 */
case 0x00001078: /* Cyrix Cx5510 */
case 0x01001078: /* Cyrix Cx5530 */
case 0xc7001045: /* OPTi 82C700 (FireStar) */
case 0x00011033: /* NEC 0001 (C-bus) */
case 0x002c1033: /* NEC 002C (C-bus) */
case 0x003b1033: /* NEC 003B (C-bus) */
case 0x886a1060: /* UMC UM8886 ISA */
case 0x02001166: /* ServerWorks IB6566 PCI */
if (bootverbose)
printf("PCI-ISA bridge with incorrect subclass 0x%x\n",
pci_get_subclass(dev));
matched = 1;
break;
default:
break;
}
}
if (matched) {
device_set_desc(dev, "PCI-ISA bridge");
return(-10000);
}
return(ENXIO);
}
static const char *
ehci_pci_match(device_t self)
{
u_int32_t device_id = pci_get_devid(self);
switch (device_id) {
case PCI_EHCI_DEVICEID_M5239:
return (ehci_device_m5239);
case PCI_EHCI_DEVICEID_8111:
return (ehci_device_8111);
case PCI_EHCI_DEVICEID_CS5536:
return (ehci_device_cs5536);
case PCI_EHCI_DEVICEID_SB200:
return (ehci_device_sb200);
case PCI_EHCI_DEVICEID_SB400:
return (ehci_device_sb400);
case PCI_EHCI_DEVICEID_6300:
return (ehci_device_6300);
case PCI_EHCI_DEVICEID_63XX:
return (ehci_device_63XX);
case PCI_EHCI_DEVICEID_ICH4:
return (ehci_device_ich4);
case PCI_EHCI_DEVICEID_ICH5:
return (ehci_device_ich5);
case PCI_EHCI_DEVICEID_ICH6:
return (ehci_device_ich6);
case PCI_EHCI_DEVICEID_ICH7:
return (ehci_device_ich7);
case PCI_EHCI_DEVICEID_ICH8_A:
return (ehci_device_ich8_a);
case PCI_EHCI_DEVICEID_ICH8_B:
return (ehci_device_ich8_b);
case PCI_EHCI_DEVICEID_NEC:
return (ehci_device_nec);
case PCI_EHCI_DEVICEID_NF2:
return (ehci_device_nf2);
case PCI_EHCI_DEVICEID_NF2_400:
return (ehci_device_nf2_400);
case PCI_EHCI_DEVICEID_NF3:
return (ehci_device_nf3);
case PCI_EHCI_DEVICEID_NF3_250:
return (ehci_device_nf3_250);
case PCI_EHCI_DEVICEID_NF4:
return (ehci_device_nf4);
case PCI_EHCI_DEVICEID_ISP156X:
return (ehci_device_isp156x);
case PCI_EHCI_DEVICEID_VIA:
return (ehci_device_via);
default:
if (pci_get_class(self) == PCIC_SERIALBUS
&& pci_get_subclass(self) == PCIS_SERIALBUS_USB
&& pci_get_progif(self) == PCI_INTERFACE_EHCI) {
return (ehci_device_generic);
}
}
return NULL; /* dunno */
}
static const char *
ohci_pci_match(device_t self)
{
uint32_t device_id = pci_get_devid(self);
switch (device_id) {
case 0x523710b9:
return ("AcerLabs M5237 (Aladdin-V) USB controller");
case 0x740c1022:
return ("AMD-756 USB Controller");
case 0x74141022:
return ("AMD-766 USB Controller");
case 0x43741002:
return "ATI SB400 USB Controller";
case 0x43751002:
return "ATI SB400 USB Controller";
case 0x06701095:
return ("CMD Tech 670 (USB0670) USB controller");
case 0x06731095:
return ("CMD Tech 673 (USB0673) USB controller");
case 0xc8611045:
return ("OPTi 82C861 (FireLink) USB controller");
case 0x00351033:
return ("NEC uPD 9210 USB controller");
case 0x00d710de:
return ("nVidia nForce3 USB Controller");
case 0x03f110de:
return ("nVidia nForce MCP61 USB Controller");
case 0x70011039:
return ("SiS 5571 USB controller");
case 0x1103108e:
return "Sun PCIO-2 USB controller";
case 0x0019106b:
return ("Apple KeyLargo USB controller");
default:
break;
}
if ((pci_get_class(self) == PCIC_SERIALBUS) &&
(pci_get_subclass(self) == PCIS_SERIALBUS_USB) &&
(pci_get_progif(self) == PCI_INTERFACE_OHCI)) {
return ("OHCI (generic) USB controller");
}
return (NULL);
}
/*
* generic PCI ATA device probe
*/
static int
hv_ata_pci_probe(device_t dev)
{
int ata_disk_enable = 0;
if(bootverbose)
device_printf(dev,
"hv_ata_pci_probe dev_class/subslcass = %d, %d\n",
pci_get_class(dev), pci_get_subclass(dev));
/* is this a storage class device ? */
if (pci_get_class(dev) != PCIC_STORAGE)
return (ENXIO);
/* is this an IDE/ATA type device ? */
if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
return (ENXIO);
if(bootverbose)
device_printf(dev,
"Hyper-V probe for disabling ATA-PCI, emulated driver\n");
/*
* On Hyper-V the default is to use the enlightened driver for
* IDE disks. However, if the user wishes to use the native
* ATA driver, the environment variable
* hw_ata.disk_enable must be explicitly set to 1.
*/
if (hv_check_for_hyper_v()) {
if (getenv_int("hw.ata.disk_enable", &ata_disk_enable)) {
if(bootverbose)
device_printf(dev,
"hw.ata.disk_enable flag is disabling Hyper-V"
" ATA driver support\n");
return (ENXIO);
}
}
if(bootverbose)
device_printf(dev, "Hyper-V ATA storage driver enabled.\n");
return (BUS_PROBE_VENDOR);
}
/*
* Generic device interface
*/
static int
pcib_probe(device_t dev)
{
if ((pci_get_class(dev) == PCIC_BRIDGE) &&
(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
device_set_desc(dev, "PCI-PCI bridge");
return(-10000);
}
return(ENXIO);
}
static const char *
xhci_pci_match(device_t self)
{
if ((pci_get_class(self) == PCIC_SERIALBUS)
&& (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
&& (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
return ("XHCI (generic) USB 3.0 controller");
}
return (NULL); /* dunno */
}
static int
ipmi2_pci_probe(device_t dev)
{
if (pci_get_class(dev) == PCIC_SERIALBUS &&
pci_get_subclass(dev) == PCIS_SERIALBUS_IPMI) {
device_set_desc(dev, "IPMI System Interface");
return (BUS_PROBE_GENERIC);
}
return (ENXIO);
}
/**
* amdgpu_atpx_detect - detect whether we have PX
*
* Check if we have a PX system (all asics).
* Returns true if we have a PX system, false if not.
*/
static bool amdgpu_atpx_detect(void)
{
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
struct pci_dev *pdev = NULL;
bool has_atpx = false;
int vga_count = 0;
bool d3_supported = false;
struct pci_dev *parent_pdev;
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
parent_pdev = pci_upstream_bridge(pdev);
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
amdgpu_atpx_get_quirks(pdev);
}
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
parent_pdev = pci_upstream_bridge(pdev);
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
amdgpu_atpx_get_quirks(pdev);
}
if (has_atpx && vga_count == 2) {
acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
pr_info("vga_switcheroo: detected switching method %s handle\n",
acpi_method_name);
amdgpu_atpx_priv.atpx_detected = true;
amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
amdgpu_atpx_init();
return true;
}
return false;
}
static const char *
uhci_pci_match(device_t self)
{
u_int32_t device_id = pci_get_devid(self);
if (device_id == PCI_UHCI_DEVICEID_PIIX3) {
return (uhci_device_piix3);
} else if (device_id == PCI_UHCI_DEVICEID_PIIX4) {
return (uhci_device_piix4);
} else if (device_id == PCI_UHCI_DEVICEID_ICH) {
return (uhci_device_ich);
} else if (device_id == PCI_UHCI_DEVICEID_ICH0) {
return (uhci_device_ich0);
} else if (device_id == PCI_UHCI_DEVICEID_ICH2_A) {
return (uhci_device_ich2_a);
} else if (device_id == PCI_UHCI_DEVICEID_ICH2_B) {
return (uhci_device_ich2_b);
} else if (device_id == PCI_UHCI_DEVICEID_ICH3_A) {
return (uhci_device_ich3_a);
} else if (device_id == PCI_UHCI_DEVICEID_ICH3_B) {
return (uhci_device_ich3_b);
} else if (device_id == PCI_UHCI_DEVICEID_ICH3_C) {
return (uhci_device_ich3_c);
} else if (device_id == PCI_UHCI_DEVICEID_ICH4_A) {
return (uhci_device_ich4_a);
} else if (device_id == PCI_UHCI_DEVICEID_ICH4_B) {
return (uhci_device_ich4_b);
} else if (device_id == PCI_UHCI_DEVICEID_ICH4_C) {
return (uhci_device_ich4_c);
} else if (device_id == PCI_UHCI_DEVICEID_ICH5_A) {
return (uhci_device_ich5_a);
} else if (device_id == PCI_UHCI_DEVICEID_ICH5_B) {
return (uhci_device_ich5_b);
} else if (device_id == PCI_UHCI_DEVICEID_ICH5_C) {
return (uhci_device_ich5_c);
} else if (device_id == PCI_UHCI_DEVICEID_ICH5_D) {
return (uhci_device_ich5_d);
} else if (device_id == PCI_UHCI_DEVICEID_440MX) {
return (uhci_device_440mx);
} else if (device_id == PCI_UHCI_DEVICEID_460GX) {
return (uhci_device_460gx);
} else if (device_id == PCI_UHCI_DEVICEID_VT83C572) {
return (uhci_device_vt83c572);
} else {
if (pci_get_class(self) == PCIC_SERIALBUS
&& pci_get_subclass(self) == PCIS_SERIALBUS_USB
&& pci_get_progif(self) == PCI_INTERFACE_UHCI) {
return (uhci_device_generic);
}
}
return NULL; /* dunno... */
}
/**
* radeon_atpx_detect - detect whether we have PX
*
* Check if we have a PX system (all asics).
* Returns true if we have a PX system, false if not.
*/
static bool radeon_atpx_detect(void)
{
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
struct pci_dev *pdev = NULL;
bool has_atpx = false;
int vga_count = 0;
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
}
/* some newer PX laptops mark the dGPU as a non-VGA display device */
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
}
if (has_atpx && vga_count == 2) {
acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
acpi_method_name);
radeon_atpx_priv.atpx_detected = true;
/*
* On some systems hotplug events are generated for the device
* being switched off when ATPX is executed. They cause ACPI
* hotplug to trigger and attempt to remove the device from
* the system, which causes it to break down. Prevent that from
* happening by setting the no_hotplug flag for the involved
* ACPI device objects.
*/
acpi_bus_no_hotplug(radeon_atpx_priv.dhandle);
acpi_bus_no_hotplug(radeon_atpx_priv.other_handle);
return true;
}
return false;
}
/**
* radeon_atpx_detect - detect whether we have PX
*
* Check if we have a PX system (all asics).
* Returns true if we have a PX system, false if not.
*/
static bool radeon_atpx_detect(void)
{
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
struct pci_dev *pdev = NULL;
bool has_atpx = false;
int vga_count = 0;
bool d3_supported = false;
struct pci_dev *parent_pdev;
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
parent_pdev = pci_upstream_bridge(pdev);
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
/* some newer PX laptops mark the dGPU as a non-VGA display device */
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
parent_pdev = pci_upstream_bridge(pdev);
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
if (has_atpx && vga_count == 2) {
acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n",
acpi_method_name);
radeon_atpx_priv.atpx_detected = true;
radeon_atpx_priv.bridge_pm_usable = d3_supported;
radeon_atpx_init();
return true;
}
return false;
}
/*
* Driver to swallow UniNorth host bridges from the PCI bus side.
*/
static int
unhb_probe(device_t dev)
{
if (pci_get_class(dev) == PCIC_BRIDGE &&
pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
device_set_desc(dev, "Host to PCI bridge");
device_quiet(dev);
return (-10000);
}
return (ENXIO);
}
