static int marvell_config_aneg(struct phy_device *phydev) { int err; /* */ err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x1f); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x200c); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x5); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x100); if (err < 0) return err; err = phy_write(phydev, MII_M1011_PHY_SCR, MII_M1011_PHY_SCR_AUTO_CROSS); if (err < 0) return err; err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, MII_M1111_PHY_LED_DIRECT); if (err < 0) return err; err = genphy_config_aneg(phydev); if (err < 0) return err; if (phydev->autoneg != AUTONEG_ENABLE) { int bmcr; /* */ bmcr = phy_read(phydev, MII_BMCR); if (bmcr < 0) return bmcr; err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); if (err < 0) return err; } return 0; }
void cs4340_upload_firmware(struct phy_device *phydev) { char line_temp[0x50] = {0}; char reg_addr[0x50] = {0}; char reg_data[0x50] = {0}; int i, line_cnt = 0, column_cnt = 0; struct cortina_reg_config fw_temp; char *addr = NULL; #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) addr = (char *)CONFIG_CORTINA_FW_ADDR; #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) int ret; size_t fw_length = CONFIG_CORTINA_FW_LENGTH; addr = malloc(CONFIG_CORTINA_FW_LENGTH); ret = nand_read(get_nand_dev_by_index(0), (loff_t)CONFIG_CORTINA_FW_ADDR, &fw_length, (u_char *)addr); if (ret == -EUCLEAN) { printf("NAND read of Cortina firmware at 0x%x failed %d\n", CONFIG_CORTINA_FW_ADDR, ret); } #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) int ret; struct spi_flash *ucode_flash; addr = malloc(CONFIG_CORTINA_FW_LENGTH); ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); if (!ucode_flash) { puts("SF: probe for Cortina ucode failed\n"); } else { ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, CONFIG_CORTINA_FW_LENGTH, addr); if (ret) puts("SF: read for Cortina ucode failed\n"); spi_flash_free(ucode_flash); } #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) int dev = CONFIG_SYS_MMC_ENV_DEV; u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; u32 blk = CONFIG_CORTINA_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) { puts("Failed to find MMC device for Cortina ucode\n"); } else { addr = malloc(CONFIG_CORTINA_FW_LENGTH); printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr); } #endif while (*addr != 'Q') { i = 0; while (*addr != 0x0a) { line_temp[i++] = *addr++; if (0x50 < i) { printf("Not found Cortina PHY ucode at 0x%p\n", (char *)CONFIG_CORTINA_FW_ADDR); return; } } addr++; /* skip '\n' */ line_cnt++; column_cnt = i; line_temp[column_cnt] = '\0'; if (CONFIG_CORTINA_FW_LENGTH < line_cnt) return; for (i = 0; i < column_cnt; i++) { if (isspace(line_temp[i++])) break; } memcpy(reg_addr, line_temp, i); memcpy(reg_data, &line_temp[i], column_cnt - i); strim(reg_addr); strim(reg_data); fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & 0xffff; phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); } }
static int dp83867_config_init(struct phy_device *phydev) { struct dp83867_private *dp83867; int ret, val, bs; u16 delay; if (!phydev->priv) { dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), GFP_KERNEL); if (!dp83867) return -ENOMEM; phydev->priv = dp83867; ret = dp83867_of_init(phydev); if (ret) return ret; } else { dp83867 = (struct dp83867_private *)phydev->priv; } /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ if (dp83867->rxctrl_strap_quirk) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); val &= ~BIT(7); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); } if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) return val; val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap. * * Such N/A mode enabled by mistake can put PHY IC in some * internal testing mode and disable RGMII transmission. * * In this particular case one needs to check STRAP_STS1 * register's bit 11 (marked as RESERVED). */ bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); if (bs & DP83867_STRAP_STS1_RESERVED) val &= ~DP83867_PHYCR_RESERVED_MASK; ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); if (ret) return ret; } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) val |= DP83867_RGMII_TX_CLK_DELAY_EN; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) val |= DP83867_RGMII_RX_CLK_DELAY_EN; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); delay = (dp83867->rx_id_delay | (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, delay); if (dp83867->io_impedance >= 0) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG); val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; val |= dp83867->io_impedance & DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); } } /* Enable Interrupt output INT_OE in CFG3 register */ if (phy_interrupt_is_valid(phydev)) { val = phy_read(phydev, DP83867_CFG3); val |= BIT(7); phy_write(phydev, DP83867_CFG3, val); } if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) dp83867_config_port_mirroring(phydev); /* Clock output selection if muxing property is set */ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG); val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); } return 0; }
static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { int err, oldpage, temp; oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); if (wol->wolopts & WAKE_MAGIC) { /* Explicitly switch to page 0x00, just to be sure */ err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); if (err < 0) return err; /* Enable the WOL interrupt */ temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); if (err < 0) return err; err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1318S_PHY_LED_PAGE); if (err < 0) return err; /* Setup LED[2] as interrupt pin (active low) */ temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); if (err < 0) return err; err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1318S_PHY_WOL_PAGE); if (err < 0) return err; /* Store the device address for the magic packet */ err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, ((phydev->attached_dev->dev_addr[5] << 8) | phydev->attached_dev->dev_addr[4])); if (err < 0) return err; err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, ((phydev->attached_dev->dev_addr[3] << 8) | phydev->attached_dev->dev_addr[2])); if (err < 0) return err; err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, ((phydev->attached_dev->dev_addr[1] << 8) | phydev->attached_dev->dev_addr[0])); if (err < 0) return err; /* Clear WOL status and enable magic packet matching */ temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); if (err < 0) return err; } else { err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1318S_PHY_WOL_PAGE); if (err < 0) return err; /* Clear WOL status and disable magic packet matching */ temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); if (err < 0) return err; } err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); if (err < 0) return err; return 0; }
static int m88e1111_config_init(struct phy_device *phydev) { int err; int temp; if (phy_interface_is_rgmii(phydev)) { temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); if (temp < 0) return temp; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { temp &= ~MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY; } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { temp &= ~MII_M1111_RX_DELAY; temp |= MII_M1111_TX_DELAY; } err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); if (err < 0) return err; temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; else temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; /* make sure copper is selected */ err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE); if (err < 0) return err; err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, err & (~0xff)); if (err < 0) return err; } if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); if (temp < 0) return temp; temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); if (err < 0) return err; temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; /* soft reset */ err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; do temp = phy_read(phydev, MII_BMCR); while (temp & BMCR_RESET); temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } err = marvell_of_reg_init(phydev); if (err < 0) return err; return phy_write(phydev, MII_BMCR, BMCR_RESET); }
static int edm_cf_imx6_fec_phy_init(struct phy_device *phydev) { unsigned short val; /* Ar8031 phy SmartEEE feature cause link status generates glitch, * which cause ethernet link down/up issue, so disable SmartEEE */ phy_write(phydev, 0xd, 0x3); phy_write(phydev, 0xe, 0x805d); phy_write(phydev, 0xd, 0x4003); val = phy_read(phydev, 0xe); val &= ~(0x1 << 8); phy_write(phydev, 0xe, val); /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ phy_write(phydev, 0xd, 0x7); phy_write(phydev, 0xe, 0x8016); phy_write(phydev, 0xd, 0x4007); val = phy_read(phydev, 0xe); val &= 0xffe3; val |= 0x18; phy_write(phydev, 0xe, val); /* Introduce tx clock delay */ phy_write(phydev, 0x1d, 0x5); val = phy_read(phydev, 0x1e); val |= 0x0100; phy_write(phydev, 0x1e, val); /*check phy power*/ val = phy_read(phydev, 0x0); if (val & BMCR_PDOWN) phy_write(phydev, 0x0, (val & ~BMCR_PDOWN)); return 0; }
static int m88e1111_config_init(struct phy_device *phydev) { int err; int temp; /* Enable Fiber/Copper auto selection */ temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); temp = phy_read(phydev, MII_BMCR); temp |= BMCR_RESET; phy_write(phydev, MII_BMCR, temp); phydev->interface = PHY_INTERFACE_MODE_RGMII_ID; if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); if (temp < 0) return temp; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { temp &= ~MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY; } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { temp &= ~MII_M1111_RX_DELAY; temp |= MII_M1111_TX_DELAY; } err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); if (err < 0) return err; temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; else temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; return 0; }
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) { /* extended registers */ phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); }
/*---------------------------------------------------------------------------- Ethernet Device initialize *----------------------------------------------------------------------------*/ int ethernet_init() { int regv, tout; char mac[ETHERNET_ADDR_SIZE]; unsigned int clock = clockselect(); LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; LPC_EMAC->MAXF = ETH_MAX_FLEN; LPC_EMAC->CLRT = CLRT_DEF; LPC_EMAC->IPGR = IPGR_DEF; LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ for(tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; LPC_EMAC->MCMD = 0; LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ for (tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->SUPP = 0; phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ regv = phy_read(PHY_REG_BMCR); if(regv < 0 || tout == 0) { return -1; /* Error */ } if(!(regv & PHY_BMCR_RESET)) { break; /* Reset complete. */ } } ethernet_set_link(-1, 0); /* Set the Ethernet MAC Address registers */ ethernet_address(mac); LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; txdscr_init(); /* initialize DMA TX Descriptor */ rxdscr_init(); /* initialize DMA RX Descriptor */ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; /* Receive Broadcast, Perfect Match Packets */ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ LPC_EMAC->MAC1 |= MAC1_REC_EN; #if NEW_LOGIC rx_consume_offset = -1; tx_produce_offset = -1; #else send_doff = 0; send_idx = -1; send_size = 0; receive_soff = 0; receive_idx = -1; #endif return 0; }
/* * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T * 0x1c shadow registers. */ static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow) { phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD)); }
static int ksz8021_config_init(struct phy_device *phydev) { const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE; phy_write(phydev, MII_KSZPHY_OMSO, val); return 0; }
static int ksz8091_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { int err, oldpage, temp; int i = 0; oldpage = phy_read(phydev, KSZ8091_MMD_CTRL); /* Magic-packet detection is enabled by writing a 1 to MMD address 1Fh,register 0h, bit [6] The MAC address (for the local MAC device) is written to and stored in MMD address 1Fh, registers 19h -1Bh The KSZ8091MNX/RNB does not generate the magic packet. The magic packet must be provided by the external system. */ printk("wol->wolopts = %d\nWAKE_MAGIC = %d\n",wol->wolopts,WAKE_MAGIC); if (wol->wolopts & WAKE_MAGIC) { temp = phy_read(phydev, KSZ8091_WOL_OMSO); phy_write(phydev, KSZ8091_WOL_OMSO,temp| 1<<15); /* Explicitly switch to page 0x1F, just to be sure */ printk("wol->wolopts = %d\nWAKE_MAGIC = %d\n",wol->wolopts,WAKE_MAGIC); for(i =0;i< 6;i++){ printk("phydev->attached_dev->dev_addr[%d] = %x \n ",i,phydev->attached_dev->dev_addr[i]); } /* Store the device address for the magic packet */ /***************************************KSZ8091_WOL_MACDA2************************************************************/ err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA2); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[5] ) << 8 |(phydev->attached_dev->dev_addr[4])); if (err < 0) return err; /***************************************KSZ8091_WOL_MACDA1*********************************************/ err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA1); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[3] ) << 8 | (phydev->attached_dev->dev_addr[2])); if (err < 0) return err; /***************************************KSZ8091_WOL_MACDA0*****************************************************/ err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA0);// select reg 0 if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[1] ) << 8 |(phydev->attached_dev->dev_addr[0])); if (err < 0) return err; /**************************************************MACEND***************************************************/ err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_C);// select reg 0 if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, 1<<6| 1<<14); //link down enable if (err < 0) return err; /* Clear WOL status and enable magic packet matching */ } else { // write addr 1f reg 0 bit6 0 disable Magic err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F); if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_C);// select reg 0 if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write if (err < 0) return err; err = phy_write(phydev, KSZ8091_MMD_REG_DATA, ~(1<<6)); //link down enable if (err < 0) return err; temp = phy_read(phydev, KSZ8091_WOL_OMSO); phy_write(phydev, KSZ8091_WOL_OMSO,temp|~( 1<<15)); } return 0; }
static int ksz9031_RNX_config_init(struct phy_device *phydev) {/*Set Auto-Negotiation FLP interval to 16ms using the following programming sequence to set MMD ? Device Address 0h, Register 4h = 0x0006 and MMD ? Device Address 0h, Register 3h = 0x1A80 */ int val=0; cnt = 0; #if 1 phy_write(phydev,MMD_CTRL,0x0); phy_write(phydev,MMD_REG_DATA,0x4); phy_write(phydev,MMD_CTRL,0x4000); phy_write(phydev,MMD_REG_DATA,0x6); phy_write(phydev,MMD_CTRL,0x0); phy_write(phydev,MMD_REG_DATA,0x3); phy_write(phydev,MMD_CTRL,0x4000); phy_write(phydev,MMD_REG_DATA,0x1A80); phy_write(phydev,MMD_CTRL,0x1); phy_write(phydev,MMD_REG_DATA,0x5a); phy_write(phydev,MMD_CTRL,0x4001); phy_write(phydev,MMD_REG_DATA,0x106); #endif printk("----micrel phy init--------\n"); /* delay rxclock SET MMD ? Device Address 2h, Register 8h = 0x01F */ #if 0 phy_write(phydev,MMD_CTRL,0x2); phy_write(phydev,MMD_REG_DATA,0x8); phy_write(phydev,MMD_CTRL,0x4002); phy_write(phydev,MMD_REG_DATA,0x3de0); #endif phy_write(phydev,MMD_CTRL,0x2); phy_write(phydev,MMD_REG_DATA,0x5); phy_write(phydev,MMD_CTRL,0x4002); phy_write(phydev,MMD_REG_DATA,0xffff); phy_write(phydev,0x4,0x5e1); val=phy_read(phydev,0x0); phy_write(phydev,0x0,val| 1<<9); return 0; }
static int m88e1111_config_init(struct phy_device *phydev) { int err; int temp; /* */ temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); temp = phy_read(phydev, MII_BMCR); temp |= BMCR_RESET; phy_write(phydev, MII_BMCR, temp); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); if (temp < 0) return temp; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { temp &= ~MII_M1111_TX_DELAY; temp |= MII_M1111_RX_DELAY; } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { temp &= ~MII_M1111_RX_DELAY; temp |= MII_M1111_TX_DELAY; } err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); if (err < 0) return err; temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; else temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK); temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); if (temp < 0) return temp; temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); if (err < 0) return err; temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; /* */ err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; do temp = phy_read(phydev, MII_BMCR); while (temp & BMCR_RESET); temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); if (err < 0) return err; } err = marvell_of_reg_init(phydev); if (err < 0) return err; err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; return 0; }
static int rtl8211e_config_init(struct phy_device *phydev) { int val; /* Disable CLK_OUT */ phy_write(phydev, RTL8211F_REGPAGE, 0x0a43); // return to page 0xa43 val = phy_read(phydev, RTL8211F_PHYCR2); phy_write(phydev, RTL8211F_PHYCR2, val & ~(1 << 0));// disable clock out phy_write(phydev, RTL8211F_REGPAGE, 0x0000); // return to page 0 phy_write(phydev, RTL8211F_REGPAGE, 0x0a43); // return to page 0xa43 #ifdef RTL_SPRD_CLK_MODE phy_write(phydev, 0x19, 0x8eb); // 125mhz clock, rxc ssc, clock ssc, and enable EEE #else phy_write(phydev, 0x19, 0x803); // 125mhz clock, no EEE, RXC clock enable, clock #endif #ifdef RTL_GREEN_MODE phy_write(phydev, RTL8211F_REGPAGE, 0x0000); // return to page 0 phy_write(phydev, 31, 0x0a43); /* 3, hk test values */ phy_write(phydev, 27, 0x8011); // I do it twice since not sure yet if it survives PHY reset phy_write(phydev, 28, 0x573f); // boosted perf about 2-3% #endif printk("am_rtl811f called phy reset\n"); phy_write(phydev, RTL8211F_PHYCTRL, 0x9200); // PHY reset msleep(10); // calls for min 50msec #ifdef RTL_GREEN_MODE phy_write(phydev, 31, 0x0a43); /* 3, hk test values */ phy_write(phydev, 27, 0x8011); phy_write(phydev, 28, 0x573f); #endif // can modify the last write, 0x00 disables EEE phy_write(phydev, RTL8211F_MMD_CTRL, 0x7); // device 7 phy_write(phydev, RTL8211F_MMD_DATA, 0x3c); // address 0x3c phy_write(phydev, RTL8211F_MMD_CTRL, 0x4007); // no post increment, reg 7 again phy_write(phydev, RTL8211F_MMD_DATA, 0x00); return 0; }
static int dp83867_config_init(struct phy_device *phydev) { struct dp83867_private *dp83867; int ret, bs; u16 val, delay, cfg2; if (!phydev->priv) { dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), GFP_KERNEL); if (!dp83867) return -ENOMEM; phydev->priv = dp83867; ret = dp83867_of_init(phydev); if (ret) return ret; } else { dp83867 = (struct dp83867_private *)phydev->priv; } /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ if (dp83867->rxctrl_strap_quirk) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); val &= ~BIT(7); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); } if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) return ret; val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) return val; val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap. * * Such N/A mode enabled by mistake can put PHY IC in some * internal testing mode and disable RGMII transmission. * * In this particular case one needs to check STRAP_STS1 * register's bit 11 (marked as RESERVED). */ bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); if (bs & DP83867_STRAP_STS1_RESERVED) val &= ~DP83867_PHYCR_RESERVED_MASK; ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); if (ret) return ret; } else { /* Set SGMIICTL1 6-wire mode */ if (dp83867->wiremode_6) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIITYPE, DP83867_SGMIICLK_EN); phy_write(phydev, MII_BMCR, (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); cfg2 = phy_read(phydev, MII_DP83867_CFG2); cfg2 &= MII_DP83867_CFG2_MASK; cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN | MII_DP83867_CFG2_SGMII_AUTONEGEN | MII_DP83867_CFG2_SPEEDOPT_ENH | MII_DP83867_CFG2_SPEEDOPT_CNT | MII_DP83867_CFG2_SPEEDOPT_INTLOW); phy_write(phydev, MII_DP83867_CFG2, cfg2); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, 0x0); phy_write(phydev, MII_DP83867_PHYCTRL, DP83867_PHYCTRL_SGMIIEN | (DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER) | (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) | (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT)); phy_write(phydev, MII_DP83867_BISCR, 0x0); /* This is a SW workaround for link instability if * RX_CTRL is not strapped to mode 3 or 4 in HW. */ if (dp83867->rxctrl_strap_quirk) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); val &= ~DP83867_CFG4_RESVDBIT7; val |= DP83867_CFG4_RESVDBIT8; val &= ~DP83867_CFG4_SGMII_AUTONEG_TIMER_MASK; val |= DP83867_CFG4_SGMII_AUTONEG_TIMER_11MS; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); } } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) val |= DP83867_RGMII_TX_CLK_DELAY_EN; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) val |= DP83867_RGMII_RX_CLK_DELAY_EN; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); delay = (dp83867->rx_id_delay | (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, delay); if (dp83867->io_impedance >= 0) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG); val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; val |= dp83867->io_impedance & DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); } } /* Enable Interrupt output INT_OE in CFG3 register */ if (phy_interrupt_is_valid(phydev)) { val = phy_read(phydev, DP83867_CFG3); val |= BIT(7); phy_write(phydev, DP83867_CFG3, val); } if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) dp83867_config_port_mirroring(phydev); /* Clock output selection if muxing property is set */ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG); val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); } return 0; }
static int mvphy_reset_88e1149(phy_handle_t *ph) { uint16_t reg; int rv; /* make sure that this PHY uses page 0 (copper) */ phy_write(ph, MVPHY_EADR, 0); reg = phy_read(ph, MVPHY_PSC); /* Disable energy detect mode */ reg &= ~MV_PSC_EN_DETECT_MASK; reg |= MV_PSC_AUTO_X_MODE; reg |= MV_PSC_DOWNSHIFT_EN; reg &= ~MV_PSC_POL_REVERSE; phy_write(ph, MVPHY_PSC, reg); rv = phy_reset(ph); phy_write(ph, MVPHY_EADR, 2); PHY_SET(ph, MVPHY_PSC, MV_PSC_RGMII_POWER_UP); /* * Fix for signal amplitude in 10BASE-T, undocumented. * This is from the Marvell reference source code. */ phy_write(ph, MVPHY_EADR, 255); phy_write(ph, 0x18, 0xaa99); phy_write(ph, 0x17, 0x2011); if (MII_PHY_REV(ph->phy_id) == 0) { /* * EC_U: IEEE A/B 1000BASE-T symmetry failure * * EC_U is rev 0, Ultra 2 is rev 1 (at least the * unit I have), so we trigger on revid. */ phy_write(ph, 0x18, 0xa204); phy_write(ph, 0x17, 0x2002); } /* page 3 is led control */ phy_write(ph, MVPHY_EADR, 3); phy_write(ph, MVPHY_PSC, MV_PSC_LED_LOS_CTRL(1) | /* link/act */ MV_PSC_LED_INIT_CTRL(8) | /* 10 Mbps */ MV_PSC_LED_STA1_CTRL(7) | /* 100 Mbps */ MV_PSC_LED_STA0_CTRL(7)); /* 1000 Mbps */ phy_write(ph, MVPHY_INTEN, 0); phy_write(ph, MVPHY_EADR, 0); /* * Weird... undocumented logic in the Intel e1000g driver. * I'm not sure what these values really do. */ phy_write(ph, MVPHY_PAGE_ADDR, 3); phy_write(ph, MVPHY_PAGE_DATA, 0); return (rv); }
/*---------------------------------------------------------------------------- Ethernet Device initialize *----------------------------------------------------------------------------*/ int ethernet_init() { int regv, tout; char mac[ETHERNET_ADDR_SIZE]; unsigned int clock = clockselect(); LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ LPC_IOCON->P1_1 &= ~0x07; LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */ LPC_IOCON->P1_4 &= ~0x07; LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */ LPC_IOCON->P1_8 &= ~0x07; LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */ LPC_IOCON->P1_9 &= ~0x07; LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */ LPC_IOCON->P1_10 &= ~0x07; LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */ LPC_IOCON->P1_14 &= ~0x07; LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */ LPC_IOCON->P1_15 &= ~0x07; LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */ LPC_IOCON->P1_17 &= ~0x07; LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */ /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; LPC_EMAC->MAXF = ETH_MAX_FLEN; LPC_EMAC->CLRT = CLRT_DEF; LPC_EMAC->IPGR = IPGR_DEF; LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ for(tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; LPC_EMAC->MCMD = 0; LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ for (tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->SUPP = 0; phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ regv = phy_read(PHY_REG_BMCR); if(regv < 0 || tout == 0) { return -1; /* Error */ } if(!(regv & PHY_BMCR_RESET)) { break; /* Reset complete. */ } } phy_id = (phy_read(PHY_REG_IDR1) << 16); phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); } ethernet_set_link(-1, 0); /* Set the Ethernet MAC Address registers */ ethernet_address(mac); LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; txdscr_init(); /* initialize DMA TX Descriptor */ rxdscr_init(); /* initialize DMA RX Descriptor */ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; /* Receive Broadcast, Perfect Match Packets */ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ LPC_EMAC->MAC1 |= MAC1_REC_EN; #if NEW_LOGIC rx_consume_offset = -1; tx_produce_offset = -1; #else send_doff = 0; send_idx = -1; send_size = 0; receive_soff = 0; receive_idx = -1; #endif return 0; }
static int brcm_fet_config_init(struct phy_device *phydev) { int reg, err, err2, brcmtest; /* Reset the PHY to bring it to a known state. */ err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; reg = phy_read(phydev, MII_BRCM_FET_INTREG); if (reg < 0) return reg; /* Unmask events we are interested in and mask interrupts globally. */ reg = MII_BRCM_FET_IR_DUPLEX_EN | MII_BRCM_FET_IR_SPEED_EN | MII_BRCM_FET_IR_LINK_EN | MII_BRCM_FET_IR_ENABLE | MII_BRCM_FET_IR_MASK; err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); if (err < 0) return err; /* Enable shadow register access */ brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); if (brcmtest < 0) return brcmtest; reg = brcmtest | MII_BRCM_FET_BT_SRE; err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); if (err < 0) return err; /* Set the LED mode */ reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); if (reg < 0) { err = reg; goto done; } reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); if (err < 0) goto done; /* Enable auto MDIX */ err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, MII_BRCM_FET_SHDW_MC_FAME); if (err < 0) goto done; if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { /* Enable auto power down */ err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, MII_BRCM_FET_SHDW_AS2_APDE); } done: /* Disable shadow register access */ err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); if (!err) err = err2; return err; }
static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) { return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); }
static int m88e1145_config_init(struct phy_device *phydev) { int err; /* Take care of errata E0 & E1 */ err = phy_write(phydev, 0x1d, 0x001b); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x418f); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x0016); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0xa2da); if (err < 0) return err; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); if (temp < 0) return temp; temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); if (err < 0) return err; if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) { err = phy_write(phydev, 0x1d, 0x0012); if (err < 0) return err; temp = phy_read(phydev, 0x1e); if (temp < 0) return temp; temp &= 0xf03f; temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ err = phy_write(phydev, 0x1e, temp); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x3); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x8000); if (err < 0) return err; } } return 0; }
static void meson_gxl_close_banks(struct phy_device *phydev) { phy_write(phydev, TSTCNTL, 0); }
static int marvell_config_aneg(struct phy_device *phydev) { int err; /* The Marvell PHY has an errata which requires * that certain registers get written in order * to restart autonegotiation */ err = phy_write(phydev, MII_BMCR, BMCR_RESET); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x1f); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x200c); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x5); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x100); if (err < 0) return err; err = marvell_set_polarity(phydev, phydev->mdix); if (err < 0) return err; err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, MII_M1111_PHY_LED_DIRECT); if (err < 0) return err; err = genphy_config_aneg(phydev); if (err < 0) return err; if (phydev->autoneg != AUTONEG_ENABLE) { int bmcr; /* * A write to speed/duplex bits (that is performed by * genphy_config_aneg() call above) must be followed by * a software reset. Otherwise, the write has no effect. */ bmcr = phy_read(phydev, MII_BMCR); if (bmcr < 0) return bmcr; err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); if (err < 0) return err; } return 0; }
static u8 ns_exp_read(struct phy_device *phydev, u16 reg) { phy_write(phydev, NS_EXP_MEM_ADD, reg); return phy_read(phydev, NS_EXP_MEM_DATA); }
static int m88e1145_config_init(struct phy_device *phydev) { int err; int temp; /* Take care of errata E0 & E1 */ err = phy_write(phydev, 0x1d, 0x001b); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x418f); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x0016); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0xa2da); if (err < 0) return err; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); if (temp < 0) return temp; temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); if (err < 0) return err; if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { err = phy_write(phydev, 0x1d, 0x0012); if (err < 0) return err; temp = phy_read(phydev, 0x1e); if (temp < 0) return temp; temp &= 0xf03f; temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ err = phy_write(phydev, 0x1e, temp); if (err < 0) return err; err = phy_write(phydev, 0x1d, 0x3); if (err < 0) return err; err = phy_write(phydev, 0x1e, 0x8000); if (err < 0) return err; } } if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { temp = phy_read(phydev, MII_M1145_PHY_EXT_SR); if (temp < 0) return temp; temp &= ~MII_M1145_HWCFG_MODE_MASK; temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK; temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO; err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp); if (err < 0) return err; } err = marvell_of_reg_init(phydev); if (err < 0) return err; return 0; }
static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data) { phy_write(phydev, NS_EXP_MEM_ADD, reg); phy_write(phydev, NS_EXP_MEM_DATA, data); }
static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) { int ret; /* set shadow mode 2 */ ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0); if (ret < 0) return ret; /* Advertise supported modes */ ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, MII_BCM7XXX_SHD_3_AN_EEE_ADV); if (ret < 0) goto reset_shadow_mode; ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, MDIO_EEE_100TX); if (ret < 0) goto reset_shadow_mode; /* Restore Defaults */ ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, MII_BCM7XXX_SHD_3_PCS_CTRL_2); if (ret < 0) goto reset_shadow_mode; ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, MII_BCM7XXX_PCS_CTRL_2_DEF); if (ret < 0) goto reset_shadow_mode; ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, MII_BCM7XXX_SHD_3_EEE_THRESH); if (ret < 0) goto reset_shadow_mode; ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, MII_BCM7XXX_EEE_THRESH_DEF); if (ret < 0) goto reset_shadow_mode; /* Enable EEE autonegotiation */ ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, MII_BCM7XXX_SHD_3_AN_STAT); if (ret < 0) goto reset_shadow_mode; ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN)); if (ret < 0) goto reset_shadow_mode; reset_shadow_mode: /* reset shadow mode 2 */ ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); if (ret < 0) return ret; /* Restart autoneg */ phy_write(phydev, MII_BMCR, (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART)); return 0; }
static void __init lager_add_rsnd_device(void) { struct platform_device_info cardinfo = { .name = "asoc-simple-card", .id = -1, .data = &rsnd_card_info, .size_data = sizeof(struct asoc_simple_card_info), .dma_mask = DMA_BIT_MASK(32), }; i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices)); platform_device_register_resndata( NULL, "rcar_sound", -1, rsnd_resources, ARRAY_SIZE(rsnd_resources), &rsnd_info, sizeof(rsnd_info)); platform_device_register_full(&cardinfo); } /* SDHI0 */ static struct sh_mobile_sdhi_info sdhi0_info __initdata = { .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_caps2 = MMC_CAP2_NO_MULTI_READ, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, }; static struct resource sdhi0_resources[] __initdata = { DEFINE_RES_MEM(0xee100000, 0x200), DEFINE_RES_IRQ(gic_spi(165)), }; /* SDHI2 */ static struct sh_mobile_sdhi_info sdhi2_info __initdata = { .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_caps2 = MMC_CAP2_NO_MULTI_READ, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, }; static struct resource sdhi2_resources[] __initdata = { DEFINE_RES_MEM(0xee140000, 0x100), DEFINE_RES_IRQ(gic_spi(167)), }; /* Internal PCI1 */ static const struct resource pci1_resources[] __initconst = { DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */ DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */ DEFINE_RES_IRQ(gic_spi(112)), }; static const struct platform_device_info pci1_info __initconst = { .name = "pci-rcar-gen2", .id = 1, .res = pci1_resources, .num_res = ARRAY_SIZE(pci1_resources), .dma_mask = DMA_BIT_MASK(32), }; static void __init lager_add_usb1_device(void) { platform_device_register_full(&pci1_info); } /* Internal PCI2 */ static const struct resource pci2_resources[] __initconst = { DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */ DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */ DEFINE_RES_IRQ(gic_spi(113)), }; static const struct platform_device_info pci2_info __initconst = { .name = "pci-rcar-gen2", .id = 2, .res = pci2_resources, .num_res = ARRAY_SIZE(pci2_resources), .dma_mask = DMA_BIT_MASK(32), }; static void __init lager_add_usb2_device(void) { platform_device_register_full(&pci2_info); } static const struct pinctrl_map lager_pinctrl_map[] = { /* DU (CN10: ARGB0, CN13: LVDS) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", "du_rgb666", "du"), PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", "du_sync_1", "du"), PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", "du_clk_out_0", "du"), /* I2C2 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790", "i2c2", "i2c2"), /* QSPI */ PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790", "qspi_ctrl", "qspi"), PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790", "qspi_data4", "qspi"), /* SCIF0 (CN19: DEBUG SERIAL0) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", "scif0_data", "scif0"), /* SCIF1 (CN20: DEBUG SERIAL1) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", "scif1_data", "scif1"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790", "sdhi0_data4", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790", "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790", "sdhi0_cd", "sdhi0"), /* SDHI2 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790", "sdhi2_data4", "sdhi2"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790", "sdhi2_ctrl", "sdhi2"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790", "sdhi2_cd", "sdhi2"), /* SSI (CN17: sound) */ PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790", "ssi0129_ctrl", "ssi"), PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790", "ssi0_data", "ssi"), PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790", "ssi1_data", "ssi"), PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790", "audio_clk_a", "audio_clk"), /* MMCIF1 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", "mmc1_data8", "mmc1"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", "mmc1_ctrl", "mmc1"), /* Ether */ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "eth_link", "eth"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "eth_mdio", "eth"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "eth_rmii", "eth"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", "intc_irq0", "intc"), /* VIN0 */ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790", "vin0_data24", "vin0"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790", "vin0_sync", "vin0"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790", "vin0_field", "vin0"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790", "vin0_clkenb", "vin0"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790", "vin0_clk", "vin0"), /* VIN1 */ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790", "vin1_data8", "vin1"), PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790", "vin1_clk", "vin1"), /* USB0 */ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790", "usb0_ovc_vbus", "usb0"), /* USB1 */ PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.1", "pfc-r8a7790", "usb1", "usb1"), /* USB2 */ PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.2", "pfc-r8a7790", "usb2", "usb2"), }; static void __init lager_add_standard_devices(void) { int fixed_regulator_idx = 0; int gpio_regulator_idx = 0; r8a7790_clock_init(); pinctrl_register_mappings(lager_pinctrl_map, ARRAY_SIZE(lager_pinctrl_map)); r8a7790_pinmux_init(); r8a7790_add_standard_devices(); platform_device_register_data(NULL, "leds-gpio", -1, &lager_leds_pdata, sizeof(lager_leds_pdata)); platform_device_register_data(NULL, "gpio-keys", -1, &lager_keys_pdata, sizeof(lager_keys_pdata)); regulator_register_always_on(fixed_regulator_idx++, "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); platform_device_register_resndata(NULL, "sh_mmcif", 1, mmcif1_resources, ARRAY_SIZE(mmcif1_resources), &mmcif1_pdata, sizeof(mmcif1_pdata)); platform_device_register_full(ðer_info); lager_add_du_device(); platform_device_register_resndata(NULL, "qspi", 0, qspi_resources, ARRAY_SIZE(qspi_resources), &qspi_pdata, sizeof(qspi_pdata)); spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++, &vcc_sdhi0_info, sizeof(struct fixed_voltage_config)); platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++, &vcc_sdhi2_info, sizeof(struct fixed_voltage_config)); platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++, &vccq_sdhi0_info, sizeof(struct gpio_regulator_config)); platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++, &vccq_sdhi2_info, sizeof(struct gpio_regulator_config)); lager_add_camera1_device(); platform_device_register_full(&sata1_info); platform_device_register_resndata(NULL, "usb_phy_rcar_gen2", -1, usbhs_phy_resources, ARRAY_SIZE(usbhs_phy_resources), &usbhs_phy_pdata, sizeof(usbhs_phy_pdata)); lager_register_usbhs(); lager_add_usb1_device(); lager_add_usb2_device(); lager_add_rsnd_device(); platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0, sdhi0_resources, ARRAY_SIZE(sdhi0_resources), &sdhi0_info, sizeof(struct sh_mobile_sdhi_info)); platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2, sdhi2_resources, ARRAY_SIZE(sdhi2_resources), &sdhi2_info, sizeof(struct sh_mobile_sdhi_info)); } /* * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits * 14-15. We have to set them back to 01 from the default 00 value each time * the PHY is reset. It's also important because the PHY's LED0 signal is * connected to SoC's ETH_LINK signal and in the PHY's default mode it will * bounce on and off after each packet, which we apparently want to avoid. */ static int lager_ksz8041_fixup(struct phy_device *phydev) { u16 phyctrl1 = phy_read(phydev, 0x1e); phyctrl1 &= ~0xc000; phyctrl1 |= 0x4000; return phy_write(phydev, 0x1e, phyctrl1); } static void __init lager_init(void) { lager_add_standard_devices(); irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW); if (IS_ENABLED(CONFIG_PHYLIB)) phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); }
static int mx6q_seco_q7_fec_phy_init(struct phy_device *phydev) { int prod_ID; /* prefer master mode, disable 1000 Base-T capable */ //phy_write(phydev, 0x9, 0x1c00); prod_ID = phy_read(phydev, 0x3); #define KSZ9021_id 0x1611 #define KSZ9031_id_1 0x1621 #define KSZ9031_id_2 0x1622 switch (prod_ID) { case KSZ9021_id: printk("Activating ethernet physical layer Micrel KSZ9021 Gigabit PHY.\n"); /* min rx data delay */ phy_write(phydev, 0x0b, 0x8105); phy_write(phydev, 0x0c, 0x0000); /* max rx/tx clock delay, min rx/tx control delay */ phy_write(phydev, 0x0b, 0x8104); phy_write(phydev, 0x0c, 0xf0f0); // phy_write(phydev, 0x0b, 0x104); break; case KSZ9031_id_1: printk("Activating ethernet physical layer Micrel KSZ9031 Gigabit PHY.\n"); phy_write(phydev, 0x0d, 0x0002); // reg. select operation phy_write(phydev, 0x0e, 0x0008); // reg. idx address phy_write(phydev, 0x0d, 0x4002); // data operation - no autoinc. phy_write(phydev, 0x0e, 0x03FF); break; case KSZ9031_id_2: printk("Activating ethernet physical layer Micrel KSZ9031 Gigabit PHY.\n"); phy_write(phydev, 0x0d, 0x0002); // reg. select operation phy_write(phydev, 0x0e, 0x0008); // reg. idx address phy_write(phydev, 0x0d, 0x4002); // data operation - no autoinc. phy_write(phydev, 0x0e, 0x03FF); break; default: printk("Warning: Product ID of physical layer not recognized [id = 0x%04x unknown]\n", prod_ID); break; } return 0; }
/** * nic_set_phys_id - set phy identify LED. * @dev: net device * @state: LED state. * * Return 0 on success, negative on failure. */ static int hns_set_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state) { struct hns_nic_priv *priv = netdev_priv(netdev); struct hnae_handle *h = priv->ae_handle; struct phy_device *phy_dev = netdev->phydev; int ret; if (phy_dev) switch (state) { case ETHTOOL_ID_ACTIVE: ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_LED); if (ret) return ret; priv->phy_led_val = phy_read(phy_dev, HNS_LED_FC_REG); ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER); if (ret) return ret; return 2; case ETHTOOL_ID_ON: ret = hns_phy_led_set(netdev, HNS_LED_FORCE_ON); if (ret) return ret; break; case ETHTOOL_ID_OFF: ret = hns_phy_led_set(netdev, HNS_LED_FORCE_OFF); if (ret) return ret; break; case ETHTOOL_ID_INACTIVE: ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_LED); if (ret) return ret; ret = phy_write(phy_dev, HNS_LED_FC_REG, priv->phy_led_val); if (ret) return ret; ret = phy_write(phy_dev, HNS_PHY_PAGE_REG, HNS_PHY_PAGE_COPPER); if (ret) return ret; break; default: return -EINVAL; } else switch (state) { case ETHTOOL_ID_ACTIVE: return h->dev->ops->set_led_id(h, HNAE_LED_ACTIVE); case ETHTOOL_ID_ON: return h->dev->ops->set_led_id(h, HNAE_LED_ON); case ETHTOOL_ID_OFF: return h->dev->ops->set_led_id(h, HNAE_LED_OFF); case ETHTOOL_ID_INACTIVE: return h->dev->ops->set_led_id(h, HNAE_LED_INACTIVE); default: return -EINVAL; } return 0; }