static int ieee802154fake_remove(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
unregister_netdev(dev);
return 0;
}
static void pcsp_shutdown(struct platform_device *dev)
{
struct snd_pcsp *chip = platform_get_drvdata(dev);
pcsp_stop_beep(chip);
}
int nvhost_gr3d_prepare_power_off(struct platform_device *dev)
{
struct nvhost_device_data *pdata = platform_get_drvdata(dev);
return nvhost_channel_save_context(pdata->channel);
}
static int __devinit pm8058_othc_probe(struct platform_device *pd)
{
int rc;
struct pm8058_othc *dd;
struct pm8058_chip *chip;
struct resource *res;
struct pmic8058_othc_config_pdata *pdata = pd->dev.platform_data;
chip = platform_get_drvdata(pd);
if (chip == NULL) {
pr_err("Invalid driver information\n");
return -EINVAL;
}
/* Check PMIC8058 version. A0 version is not supported */
if (pm8058_rev(chip) == PM_8058_REV_1p0) {
pr_err("PMIC8058 version not supported\n");
return -ENODEV;
}
if (pdata == NULL) {
pr_err("Platform data not present\n");
return -EINVAL;
}
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
if (dd == NULL) {
pr_err("Unable to allocate memory\n");
return -ENOMEM;
}
/* Enable runtime PM ops, start in ACTIVE mode */
rc = pm_runtime_set_active(&pd->dev);
if (rc < 0)
dev_dbg(&pd->dev, "unable to set runtime pm state\n");
pm_runtime_enable(&pd->dev);
res = platform_get_resource_byname(pd, IORESOURCE_IO, "othc_base");
if (res == NULL) {
pr_err("othc resource:Base address absent\n");
rc = -ENXIO;
goto fail_get_res;
}
dd->othc_pdata = pdata;
dd->pm_chip = chip;
dd->othc_base = res->start;
platform_set_drvdata(pd, dd);
if (pdata->micbias_capability == OTHC_MICBIAS_HSED) {
/* HSED to be supported on this MICBIAS line */
if (pdata->hsed_config != NULL) {
rc = othc_configure_hsed(dd, pd);
if (rc < 0)
goto fail_get_res;
} else {
pr_err("HSED config data not present\n");
rc = -EINVAL;
goto fail_get_res;
}
}
/* Store the local driver data structure */
if (dd->othc_pdata->micbias_select < OTHC_MICBIAS_MAX)
config[dd->othc_pdata->micbias_select] = dd;
pr_debug("Device %s:%d successfully registered\n",
pd->name, pd->id);
return 0;
fail_get_res:
pm_runtime_set_suspended(&pd->dev);
pm_runtime_disable(&pd->dev);
kfree(dd);
return rc;
}
int zmii_attach(struct platform_device *ofdev, int input, int *mode)
{
struct zmii_instance *dev = platform_get_drvdata(ofdev);
struct zmii_regs __iomem *p = dev->base;
ZMII_DBG(dev, "init(%d, %d)" NL, input, *mode);
if (!zmii_valid_mode(*mode)) {
/* Probably an EMAC connected to RGMII,
* but it still may need ZMII for MDIO so
* we don't fail here.
*/
dev->users++;
return 0;
}
mutex_lock(&dev->lock);
/* Autodetect ZMII mode if not specified.
* This is only for backward compatibility with the old driver.
* Please, always specify PHY mode in your board port to avoid
* any surprises.
*/
if (dev->mode == PHY_MODE_NA) {
if (*mode == PHY_MODE_NA) {
u32 r = dev->fer_save;
ZMII_DBG(dev, "autodetecting mode, FER = 0x%08x" NL, r);
if (r & (ZMII_FER_MII(0) | ZMII_FER_MII(1)))
dev->mode = PHY_MODE_MII;
else if (r & (ZMII_FER_RMII(0) | ZMII_FER_RMII(1)))
dev->mode = PHY_MODE_RMII;
else
dev->mode = PHY_MODE_SMII;
} else
dev->mode = *mode;
printk(KERN_NOTICE "%s: bridge in %s mode\n",
ofdev->dev.of_node->full_name,
zmii_mode_name(dev->mode));
} else {
/* All inputs must use the same mode */
if (*mode != PHY_MODE_NA && *mode != dev->mode) {
printk(KERN_ERR
"%s: invalid mode %d specified for input %d\n",
ofdev->dev.of_node->full_name, *mode, input);
mutex_unlock(&dev->lock);
return -EINVAL;
}
}
/* Report back correct PHY mode,
* it may be used during PHY initialization.
*/
*mode = dev->mode;
/* Enable this input */
out_be32(&p->fer, in_be32(&p->fer) | zmii_mode_mask(dev->mode, input));
++dev->users;
mutex_unlock(&dev->lock);
return 0;
}
static int __devexit pil_q6v3_driver_exit(struct platform_device *pdev)
{
struct q6v3_data *drv = platform_get_drvdata(pdev);
msm_pil_unregister(drv->pil);
return 0;
}
int mdp4_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
int dsi_height;
int dsi_bpp;
int dsi_border_clr;
int dsi_underflow_clr;
int dsi_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
unsigned int buf_offset;
int bpp, ptype;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *pipe;
int ret = 0;
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct msm_panel_info *pinfo;
vctrl = &vsync_ctrl_db[cndx];
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return -ENODEV;
#endif
mutex_lock(&mfd->dma->ov_mutex);
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
vctrl->blt_ctrl = pinfo->lcd.blt_ctrl;
vctrl->vsync_irq_enabled = 0;
vsync_irq_cnt = 0;
/* mdp clock on */
mdp_clk_ctrl(1);
fbi = mfd->fbi;
var = &fbi->var;
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
if (vctrl->base_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return -EBUSY;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_VIDEO);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
vctrl->base_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
} else {
pipe = vctrl->base_pipe;
}
atomic_set(&vctrl->suspend, 0);
#if defined(CONFIG_FEATURE_FLIPLR)
pipe->mfd = mfd;
#endif
/* QC Patch for LCD black out Issue */
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
mdp4_dsi_video_wait4vsync(0);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mipi_dsi_controller_cfg(0);
/* Clks are enabled in probe.
Disabling clocks now */
mdp_clk_ctrl(0);
}
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
pipe->bpp = bpp;
/* there is no FB, so we need to set it until we get data from surfaceFlinger */
if (!use_frame_buffer)
pipe->solid_fill = 1;
if (mfd->display_iova)
pipe->srcp0_addr = mfd->display_iova + buf_offset;
else
pipe->srcp0_addr = (uint32)(buf + buf_offset);
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
mdp4_overlay_solidfill_init(pipe);
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mdp4_calc_blt_mdp_bw(mfd, pipe);
mdp4_overlay_dmap_xy(pipe); /* dma_p */
mdp4_overlay_dmap_cfg(mfd, 1);
mdp4_overlay_rgb_setup(pipe);
/* Solid_fill clear after booting */
if (!use_frame_buffer)
pipe->solid_fill = 0;
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_reg_flush(pipe, 1);
mdp4_mixer_stage_up(pipe, 0);
mdp4_mixer_stage_commit(pipe->mixer_num);
/*
* DSI timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
dsi_border_clr = mfd->panel_info.lcdc.border_clr;
dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
dsi_width = mfd->panel_info.xres +
mfd->panel_info.lcdc.xres_pad;
dsi_height = mfd->panel_info.yres +
mfd->panel_info.lcdc.yres_pad;
dsi_bpp = mfd->panel_info.bpp;
hsync_period = hsync_pulse_width + h_back_porch + dsi_width
+ h_front_porch;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = h_back_porch + hsync_pulse_width;
hsync_end_x = hsync_period - h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(vsync_pulse_width + v_back_porch + dsi_height + v_front_porch);
display_v_start = ((vsync_pulse_width + v_back_porch) * hsync_period)
+ dsi_hsync_skew;
display_v_end =
((vsync_period - v_front_porch) * hsync_period) + dsi_hsync_skew - 1;
if (dsi_width != var->xres) {
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl =
ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
} else {
active_hctl = 0;
}
if (dsi_height != var->yres) {
active_v_start =
display_v_start + first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
} else {
active_v_start = 0;
active_v_end = 0;
}
dsi_underflow_clr |= 0x80000000; /* enable recovery */
hsync_polarity = 0;
vsync_polarity = 0;
data_en_polarity = 0;
ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc,
vsync_pulse_width * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(TRUE);
mutex_unlock(&mfd->dma->ov_mutex);
// mdp4_overlay_dsi_video_start();
return ret;
}
int mdp4_dtv_off(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
int ret = 0;
int cndx = 0;
int undx;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
#if defined(CONFIG_VIDEO_MHL_V1) || defined(CONFIG_VIDEO_MHL_V2) || \
defined(CONFIG_VIDEO_MHL_TAB_V2)
if (hdmi_msm_state->hpd_on_offline) {
pr_info("hpd_offline is not\n");
return -ENODEV;
}
#endif
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
mdp4_dtv_wait4vsync(cndx);
atomic_set(&vctrl->vsync_resume, 0);
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
pipe = vctrl->base_pipe;
if (pipe != NULL) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (hdmi_prim_display && mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
/* pipe == rgb2 */
vctrl->base_pipe = NULL;
} else {
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
}
}
mdp4_dtv_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dtv_pipe_clean(vp);
}
ret = panel_next_off(pdev);
mdp_footswitch_ctrl(FALSE);
/* Mdp clock disable */
mdp_clk_ctrl(0);
mutex_unlock(&mfd->dma->ov_mutex);
pr_info("%s:\n", __func__);
return ret;
}
static irqreturn_t exynos4x12_tmu_irq_handler(int irq, void *id)
{
struct s5p_tmu_info *info = id;
unsigned int status;
disable_irq_nosync(irq);
status = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT) & 0x1FFFF;
pr_info("EXYNOS4x12_tmu interrupt: INTSTAT = 0x%08x\n", status);
/* To handle multiple interrupt pending,
* interrupt by high temperature are serviced with priority.
*/
#if defined(CONFIG_TC_VOLTAGE)
if (status & INTSTAT_FALL0) {
info->tmu_state = TMU_STATUS_TC;
__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
exynos_interrupt_enable(info, 0);
} else if (status & INTSTAT_RISE2) {
info->tmu_state = TMU_STATUS_TRIPPED;
__raw_writel(INTCLEAR_RISE2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
#else
if (status & INTSTAT_RISE2) {
info->tmu_state = TMU_STATUS_TRIPPED;
__raw_writel(INTCLEAR_RISE2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
#endif
} else if (status & INTSTAT_RISE1) {
info->tmu_state = TMU_STATUS_WARNING;
__raw_writel(INTCLEAR_RISE1, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
} else if (status & INTSTAT_RISE0) {
info->tmu_state = TMU_STATUS_THROTTLED;
__raw_writel(INTCLEAR_RISE0, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
} else {
pr_err("%s: interrupt error\n", __func__);
__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
queue_delayed_work_on(0, tmu_monitor_wq,
&info->polling, info->sampling_rate / 2);
return -ENODEV;
}
/* read current temperature & save */
info->last_temperature = get_curr_temp(info);
queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
info->sampling_rate);
return IRQ_HANDLED;
}
static irqreturn_t exynos4210_tmu_irq_handler(int irq, void *id)
{
struct s5p_tmu_info *info = id;
unsigned int status;
disable_irq_nosync(irq);
status = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTSTAT);
pr_info("EXYNOS4212_tmu interrupt: INTSTAT = 0x%08x\n", status);
/* To handle multiple interrupt pending,
* interrupt by high temperature are serviced with priority.
*/
if (status & TMU_INTSTAT2) {
info->tmu_state = TMU_STATUS_TRIPPED;
__raw_writel(INTCLEAR2, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
} else if (status & TMU_INTSTAT1) {
info->tmu_state = TMU_STATUS_WARNING;
__raw_writel(INTCLEAR1, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
} else if (status & TMU_INTSTAT0) {
info->tmu_state = TMU_STATUS_THROTTLED;
__raw_writel(INTCLEAR0, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
} else {
pr_err("%s: interrupt error\n", __func__);
__raw_writel(INTCLEARALL, info->tmu_base + EXYNOS4_TMU_INTCLEAR);
queue_delayed_work_on(0, tmu_monitor_wq,
&info->polling, info->sampling_rate / 2);
return -ENODEV;
}
/* read current temperature & save */
info->last_temperature = get_curr_temp(info);
queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
info->sampling_rate);
return IRQ_HANDLED;
}
#ifdef CONFIG_TMU_SYSFS
static ssize_t s5p_tmu_show_curr_temp(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct s5p_tmu_info *info = dev_get_drvdata(dev);
unsigned int curr_temp;
curr_temp = get_curr_temp(info);
curr_temp *= 10;
pr_info("curr temp = %d\n", curr_temp);
return sprintf(buf, "%d\n", curr_temp);
}
static DEVICE_ATTR(curr_temp, S_IRUGO, s5p_tmu_show_curr_temp, NULL);
#endif
static int __devinit s5p_tmu_probe(struct platform_device *pdev)
{
struct s5p_tmu_info *info;
struct s5p_platform_tmu *pdata;
struct resource *res;
unsigned int mask = (enable_mask & ENABLE_DBGMASK);
int ret = 0;
pr_debug("%s: probe=%p\n", __func__, pdev);
info = kzalloc(sizeof(struct s5p_tmu_info), GFP_KERNEL);
if (!info) {
dev_err(&pdev->dev, "failed to alloc memory!\n");
ret = -ENOMEM;
goto err_nomem;
}
platform_set_drvdata(pdev, info);
info->dev = &pdev->dev;
info->tmu_state = TMU_STATUS_INIT;
/* set cpufreq limit level at 1st_throttle & 2nd throttle */
pdata = info->dev->platform_data;
if (pdata->cpufreq.limit_1st_throttle)
exynos_cpufreq_get_level(pdata->cpufreq.limit_1st_throttle,
&info->cpufreq_level_1st_throttle);
if (pdata->cpufreq.limit_2nd_throttle)
exynos_cpufreq_get_level(pdata->cpufreq.limit_2nd_throttle,
&info->cpufreq_level_2nd_throttle);
pr_info("@@@ %s: cpufreq_limit: 1st_throttle: %u, 2nd_throttle = %u\n",
__func__, info->cpufreq_level_1st_throttle,
info->cpufreq_level_2nd_throttle);
#if defined(CONFIG_TC_VOLTAGE) /* Temperature compensated voltage */
if (exynos_find_cpufreq_level_by_volt(pdata->temp_compensate.arm_volt,
&info->cpulevel_tc) < 0) {
dev_err(&pdev->dev, "cpufreq_get_level error\n");
ret = -EINVAL;
goto err_nores;
}
#ifdef CONFIG_BUSFREQ_OPP
/* To lock bus frequency in OPP mode */
info->bus_dev = dev_get("exynos-busfreq");
if (info->bus_dev < 0) {
dev_err(&pdev->dev, "Failed to get_dev\n");
ret = -EINVAL;
goto err_nores;
}
if (exynos4x12_find_busfreq_by_volt(pdata->temp_compensate.bus_volt,
&info->busfreq_tc)) {
dev_err(&pdev->dev, "get_busfreq_value error\n");
ret = -EINVAL;
goto err_nores;
}
#endif
pr_info("%s: cpufreq_level[%u], busfreq_value[%u]\n",
__func__, info->cpulevel_tc, info->busfreq_tc);
#endif
/* Map auto_refresh_rate of normal & tq0 mode */
info->auto_refresh_tq0 =
get_refresh_interval(FREQ_IN_PLL, AUTO_REFRESH_PERIOD_TQ0);
info->auto_refresh_normal =
get_refresh_interval(FREQ_IN_PLL, AUTO_REFRESH_PERIOD_NORMAL);
/* To poll current temp, set sampling rate to ONE second sampling */
info->sampling_rate = usecs_to_jiffies(1000 * 1000);
/* 10sec monitroing */
info->monitor_period = usecs_to_jiffies(10000 * 1000);
/* support test mode */
if (mask & ENABLE_TEST_MODE)
set_temperature_params(info);
else
print_temperature_params(info);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get memory region resource\n");
ret = -ENODEV;
goto err_nores;
}
info->ioarea = request_mem_region(res->start,
res->end-res->start + 1, pdev->name);
if (!(info->ioarea)) {
dev_err(&pdev->dev, "failed to reserve memory region\n");
ret = -EBUSY;
goto err_nores;
}
info->tmu_base = ioremap(res->start, (res->end - res->start) + 1);
if (!(info->tmu_base)) {
dev_err(&pdev->dev, "failed ioremap()\n");
ret = -ENOMEM;
goto err_nomap;
}
tmu_monitor_wq = create_freezable_workqueue(dev_name(&pdev->dev));
if (!tmu_monitor_wq) {
pr_info("Creation of tmu_monitor_wq failed\n");
ret = -ENOMEM;
goto err_wq;
}
/* To support periodic temprature monitoring */
if (mask & ENABLE_TEMP_MON) {
INIT_DELAYED_WORK_DEFERRABLE(&info->monitor,
exynos4_poll_cur_temp);
queue_delayed_work_on(0, tmu_monitor_wq, &info->monitor,
info->monitor_period);
}
INIT_DELAYED_WORK_DEFERRABLE(&info->polling, exynos4_handler_tmu_state);
info->irq = platform_get_irq(pdev, 0);
if (info->irq < 0) {
dev_err(&pdev->dev, "no irq for thermal %d\n", info->irq);
ret = -EINVAL;
goto err_irq;
}
if (soc_is_exynos4210())
ret = request_irq(info->irq, exynos4210_tmu_irq_handler,
IRQF_DISABLED, "s5p-tmu interrupt", info);
else
ret = request_irq(info->irq, exynos4x12_tmu_irq_handler,
IRQF_DISABLED, "s5p-tmu interrupt", info);
if (ret) {
dev_err(&pdev->dev, "request_irq is failed. %d\n", ret);
goto err_irq;
}
ret = device_create_file(&pdev->dev, &dev_attr_temperature);
if (ret != 0) {
pr_err("Failed to create temperatue file: %d\n", ret);
goto err_sysfs_file1;
}
ret = device_create_file(&pdev->dev, &dev_attr_tmu_state);
if (ret != 0) {
pr_err("Failed to create tmu_state file: %d\n", ret);
goto err_sysfs_file2;
}
ret = device_create_file(&pdev->dev, &dev_attr_lot_id);
if (ret != 0) {
pr_err("Failed to create lot id file: %d\n", ret);
goto err_sysfs_file3;
}
ret = tmu_initialize(pdev);
if (ret)
goto err_init;
#ifdef CONFIG_TMU_SYSFS
ret = device_create_file(&pdev->dev, &dev_attr_curr_temp);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to create sysfs group\n");
goto err_init;
}
#endif
#ifdef CONFIG_TMU_DEBUG
ret = device_create_file(&pdev->dev, &dev_attr_print_state);
if (ret) {
dev_err(&pdev->dev, "Failed to create tmu sysfs group\n\n");
return ret;
}
#endif
#if defined(CONFIG_TC_VOLTAGE)
/* s/w workaround for fast service when interrupt is not occured,
* such as current temp is lower than tc interrupt temperature
* or current temp is continuosly increased.
*/
if (get_curr_temp(info) <= pdata->ts.start_tc) {
if (exynos_tc_volt(info, 1) < 0)
pr_err("TMU: lock error!\n");
}
#if defined(CONFIG_VIDEO_MALI400MP)
if (mali_voltage_lock_init())
pr_err("Failed to initialize mail voltage lock.\n");
#endif
#endif
/* initialize tmu_state */
queue_delayed_work_on(0, tmu_monitor_wq, &info->polling,
info->sampling_rate);
return ret;
err_init:
device_remove_file(&pdev->dev, &dev_attr_lot_id);
err_sysfs_file3:
device_remove_file(&pdev->dev, &dev_attr_tmu_state);
err_sysfs_file2:
device_remove_file(&pdev->dev, &dev_attr_temperature);
err_sysfs_file1:
if (info->irq >= 0)
free_irq(info->irq, info);
err_irq:
destroy_workqueue(tmu_monitor_wq);
err_wq:
iounmap(info->tmu_base);
err_nomap:
release_resource(info->ioarea);
kfree(info->ioarea);
err_nores:
kfree(info);
info = NULL;
err_nomem:
dev_err(&pdev->dev, "initialization failed.\n");
return ret;
}
static int __devinit s5p_tmu_remove(struct platform_device *pdev)
{
struct s5p_tmu_info *info = platform_get_drvdata(pdev);
cancel_delayed_work(&info->polling);
destroy_workqueue(tmu_monitor_wq);
device_remove_file(&pdev->dev, &dev_attr_temperature);
device_remove_file(&pdev->dev, &dev_attr_tmu_state);
if (info->irq >= 0)
free_irq(info->irq, info);
iounmap(info->tmu_base);
release_resource(info->ioarea);
kfree(info->ioarea);
kfree(info);
info = NULL;
pr_info("%s is removed\n", dev_name(&pdev->dev));
return 0;
}
#ifdef CONFIG_PM
static int s5p_tmu_suspend(struct platform_device *pdev, pm_message_t state)
{
struct s5p_tmu_info *info = platform_get_drvdata(pdev);
if (!info)
return -EAGAIN;
/* save register value */
info->reg_save[0] = __raw_readl(info->tmu_base + EXYNOS4_TMU_CONTROL);
info->reg_save[1] = __raw_readl(info->tmu_base + EXYNOS4_TMU_SAMPLING_INTERNAL);
info->reg_save[2] = __raw_readl(info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE0);
info->reg_save[3] = __raw_readl(info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE1);
info->reg_save[4] = __raw_readl(info->tmu_base + EXYNOS4_TMU_INTEN);
if (soc_is_exynos4210()) {
info->reg_save[5] =
__raw_readl(info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP);
info->reg_save[6] =
__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0);
info->reg_save[7] =
__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1);
info->reg_save[8] =
__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2);
info->reg_save[9] =
__raw_readl(info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3);
} else {
info->reg_save[5] =
__raw_readl(info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE);
#if defined(CONFIG_TC_VOLTAGE)
info->reg_save[6] = __raw_readl(info->tmu_base
+ EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL);
#endif
}
disable_irq(info->irq);
return 0;
}
static int s5p_tmu_resume(struct platform_device *pdev)
{
struct s5p_tmu_info *info = platform_get_drvdata(pdev);
struct s5p_platform_tmu *data;
if (!info)
return -EAGAIN;
data = info->dev->platform_data;
/* restore tmu register value */
__raw_writel(info->reg_save[0], info->tmu_base + EXYNOS4_TMU_CONTROL);
__raw_writel(info->reg_save[1],
info->tmu_base + EXYNOS4_TMU_SAMPLING_INTERNAL);
__raw_writel(info->reg_save[2],
info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE0);
__raw_writel(info->reg_save[3],
info->tmu_base + EXYNOS4_TMU_COUNTER_VALUE1);
if (soc_is_exynos4210()) {
__raw_writel(info->reg_save[5],
info->tmu_base + EXYNOS4210_TMU_THRESHOLD_TEMP);
__raw_writel(info->reg_save[6],
info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL0);
__raw_writel(info->reg_save[7],
info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL1);
__raw_writel(info->reg_save[8],
info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL2);
__raw_writel(info->reg_save[9],
info->tmu_base + EXYNOS4210_TMU_TRIG_LEVEL3);
} else {
__raw_writel(info->reg_save[5],
info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_RISE);
#if defined(CONFIG_TC_VOLTAGE)
__raw_writel(info->reg_save[6],
info->tmu_base + EXYNOS4x12_TMU_TRESHOLD_TEMP_FALL);
#endif
}
__raw_writel(info->reg_save[4],
info->tmu_base + EXYNOS4_TMU_INTEN);
#if defined(CONFIG_TC_VOLTAGE)
/* s/w workaround for fast service when interrupt is not occured,
* such as current temp is lower than tc interrupt temperature
* or current temp is continuosly increased..
*/
mdelay(1);
if (get_curr_temp(info) <= data->ts.start_tc) {
if (exynos_tc_volt(info, 1) < 0)
pr_err("TMU: lock error!\n");
}
#endif
/* Find out tmu_state after wakeup */
queue_delayed_work_on(0, tmu_monitor_wq, &info->polling, 0);
return 0;
}
#else
#define s5p_tmu_suspend NULL
#define s5p_tmu_resume NULL
#endif
static struct platform_driver s5p_tmu_driver = {
.probe = s5p_tmu_probe,
.remove = s5p_tmu_remove,
.suspend = s5p_tmu_suspend,
.resume = s5p_tmu_resume,
.driver = {
.name = "s5p-tmu",
.owner = THIS_MODULE,
},
};
static int __init s5p_tmu_driver_init(void)
{
return platform_driver_register(&s5p_tmu_driver);
}
static void __exit s5p_tmu_driver_exit(void)
{
platform_driver_unregister(&s5p_tmu_driver);
}
static int gpu_resume(struct platform_device *dev)
{
gceSTATUS status;
gckGALDEVICE device;
gctINT i;
gceCHIPPOWERSTATE statesStored;
device = platform_get_drvdata(dev);
for (i = 0; i < gcdMAX_GPU_COUNT; i++)
{
if (device->kernels[i] != gcvNULL)
{
#if gcdENABLE_VG
if (i == gcvCORE_VG)
{
status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
}
else
#endif
{
status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
}
if (gcmIS_ERROR(status))
{
return -1;
}
/* Convert global state to crossponding internal state. */
switch(device->statesStored[i])
{
case gcvPOWER_OFF:
statesStored = gcvPOWER_OFF_BROADCAST;
break;
case gcvPOWER_IDLE:
statesStored = gcvPOWER_IDLE_BROADCAST;
break;
case gcvPOWER_SUSPEND:
statesStored = gcvPOWER_SUSPEND_BROADCAST;
break;
case gcvPOWER_ON:
statesStored = gcvPOWER_ON_AUTO;
break;
default:
statesStored = device->statesStored[i];
break;
}
/* Restore states. */
#if gcdENABLE_VG
if (i == gcvCORE_VG)
{
status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
}
else
#endif
{
status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
}
if (gcmIS_ERROR(status))
{
return -1;
}
}
}
return 0;
}
static int dtv_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc;
if (pdev->id == 0) {
dtv_pdata = pdev->dev.platform_data;
#ifdef CONFIG_MSM_BUS_SCALING
if (!dtv_bus_scale_handle && dtv_pdata &&
dtv_pdata->bus_scale_table) {
dtv_bus_scale_handle =
msm_bus_scale_register_client(
dtv_pdata->bus_scale_table);
if (!dtv_bus_scale_handle) {
pr_err("%s not able to get bus scale\n",
__func__);
}
}
#else
ebi1_clk = clk_get(&pdev->dev, "mem_clk");
if (IS_ERR(ebi1_clk)) {
ebi1_clk = NULL;
pr_warning("%s: Couldn't get ebi1 clock\n", __func__);
}
#endif
tv_src_clk = clk_get(&pdev->dev, "src_clk");
if (IS_ERR(tv_src_clk)) {
pr_err("error: can't get tv_src_clk!\n");
return IS_ERR(tv_src_clk);
}
hdmi_clk = clk_get(&pdev->dev, "hdmi_clk");
if (IS_ERR(hdmi_clk)) {
pr_err("error: can't get hdmi_clk!\n");
return IS_ERR(hdmi_clk);
}
mdp_tv_clk = clk_get(&pdev->dev, "mdp_clk");
if (IS_ERR(mdp_tv_clk))
mdp_tv_clk = NULL;
return 0;
}
dtv_work_queue = create_singlethread_workqueue("dtv_work");
INIT_WORK(&dtv_off_work, dtv_off_work_func);
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
/*
* link to the latest pdev
*/
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCDC;
/*
* alloc panel device data
*/
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
pr_err("dtv_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
/*
* data chain
*/
pdata = (struct msm_fb_panel_data *)mdp_dev->dev.platform_data;
pdata->on = dtv_on;
pdata->off = dtv_off;
pdata->next = pdev;
/*
* get/set panel specific fb info
*/
mfd->panel_info = pdata->panel_info;
if (hdmi_prim_display)
mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
else
mfd->fb_imgType = MDP_RGB_565;
fbi = mfd->fbi;
fbi->var.pixclock = mfd->panel_info.clk_rate;
fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch;
fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch;
fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch;
fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width;
fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width;
/*
* set driver data
*/
platform_set_drvdata(mdp_dev, mfd);
/*
* register in mdp driver
*/
rc = platform_device_add(mdp_dev);
if (rc)
goto dtv_probe_err;
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
pdev_list[pdev_list_cnt++] = pdev;
return 0;
dtv_probe_err:
#ifdef CONFIG_MSM_BUS_SCALING
if (dtv_pdata && dtv_pdata->bus_scale_table &&
dtv_bus_scale_handle > 0)
msm_bus_scale_unregister_client(dtv_bus_scale_handle);
#endif
platform_device_put(mdp_dev);
return rc;
}
int mdp4_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
int dsi_height;
int dsi_bpp;
int dsi_border_clr;
int dsi_underflow_clr;
int dsi_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
unsigned int buf_offset;
int bpp, ptype;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *pipe;
int ret = 0;
int cndx = 0;
struct vsycn_ctrl *vctrl;
vctrl = &vsync_ctrl_db[cndx];
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
vctrl->fake_vsync = 1;
/* mdp clock on */
mdp_clk_ctrl(1);
fbi = mfd->fbi;
var = &fbi->var;
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
if (vctrl->base_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
return -EBUSY;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_VIDEO);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
vctrl->base_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
} else {
pipe = vctrl->base_pipe;
}
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
mdp4_dsi_video_wait4dmap_done(0);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mipi_dsi_controller_cfg(0);
}
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
pipe->bpp = bpp;
if (mfd->map_buffer) {
pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \
buf_offset;
pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd->
map_buffer->iova[0], pipe->srcp0_addr);
} else {
pipe->srcp0_addr = (uint32)(buf + buf_offset);
}
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
mdp4_overlay_mdp_pipe_req(pipe, mfd);
atomic_set(&vctrl->suspend, 0);
mdp4_overlay_dmap_xy(pipe); /* dma_p */
mdp4_overlay_dmap_cfg(mfd, 1);
mdp4_overlay_rgb_setup(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_reg_flush(pipe, 1);
mdp4_mixer_stage_up(pipe);
mdp4_mixer_stage_commit(pipe->mixer_num);
/*
* DSI timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
dsi_border_clr = mfd->panel_info.lcdc.border_clr;
dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
dsi_width = mfd->panel_info.xres +
mfd->panel_info.lcdc.xres_pad;
dsi_height = mfd->panel_info.yres +
mfd->panel_info.lcdc.yres_pad;
dsi_bpp = mfd->panel_info.bpp;
hsync_period = hsync_pulse_width + h_back_porch + dsi_width
+ h_front_porch;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = h_back_porch + hsync_pulse_width;
hsync_end_x = hsync_period - h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(vsync_pulse_width + v_back_porch + dsi_height + v_front_porch);
display_v_start = ((vsync_pulse_width + v_back_porch) * hsync_period)
+ dsi_hsync_skew;
display_v_end =
((vsync_period - v_front_porch) * hsync_period) + dsi_hsync_skew - 1;
if (dsi_width != var->xres) {
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl =
ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
} else {
active_hctl = 0;
}
if (dsi_height != var->yres) {
active_v_start =
display_v_start + first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
} else {
active_v_start = 0;
active_v_end = 0;
}
dsi_underflow_clr |= 0x80000000; /* enable recovery */
hsync_polarity = 0;
vsync_polarity = 0;
data_en_polarity = 0;
ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc,
vsync_pulse_width * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(TRUE);
return ret;
}
void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
{
ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
}
int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma)
{
struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev);
int ret = 0;
u8 bits;
u8 mbcs2, chgmod;
unsigned int mbcc5;
if (ma >= 1000) {
bits = PCF50633_MBCC7_USB_1000mA;
ma = 1000;
} else if (ma >= 500) {
bits = PCF50633_MBCC7_USB_500mA;
ma = 500;
} else if (ma >= 100) {
bits = PCF50633_MBCC7_USB_100mA;
ma = 100;
} else {
bits = PCF50633_MBCC7_USB_SUSPEND;
ma = 0;
}
ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
PCF50633_MBCC7_USB_MASK, bits);
if (ret)
dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma);
else
dev_info(pcf->dev, "usb curlim to %d mA\n", ma);
/*
* We limit the charging current to be the USB current limit.
* The reason is that on pcf50633, when it enters PMU Standby mode,
* which it does when the device goes "off", the USB current limit
* reverts to the variant default. In at least one common case, that
* default is 500mA. By setting the charging current to be the same
* as the USB limit we set here before PMU standby, we enforce it only
* using the correct amount of current even when the USB current limit
* gets reset to the wrong thing
*/
if (mbc->pcf->pdata->charger_reference_current_ma) {
mbcc5 = (ma << 8) / mbc->pcf->pdata->charger_reference_current_ma;
if (mbcc5 > 255)
mbcc5 = 255;
pcf50633_reg_write(mbc->pcf, PCF50633_REG_MBCC5, mbcc5);
}
mbcs2 = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCS2);
chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
/* If chgmod == BATFULL, setting chgena has no effect.
* Datasheet says we need to set resume instead but when autoresume is
* used resume doesn't work. Clear and set chgena instead.
*/
if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
PCF50633_MBCC1_CHGENA, PCF50633_MBCC1_CHGENA);
else {
pcf50633_reg_clear_bits(pcf, PCF50633_REG_MBCC1,
PCF50633_MBCC1_CHGENA);
pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
PCF50633_MBCC1_CHGENA, PCF50633_MBCC1_CHGENA);
}
power_supply_changed(mbc->usb);
return ret;
}
static ssize_t store_ehci_power(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
int power_on;
int irq;
int retval;
if (sscanf(buf, "%d", &power_on) != 1)
return -EINVAL;
device_lock(dev);
if (!power_on && s5p_ehci->power_on) {
printk(KERN_DEBUG "%s: EHCI turns off\n", __func__);
pm_runtime_forbid(dev);
s5p_ehci->power_on = 0;
usb_remove_hcd(hcd);
if (pdata && pdata->phy_exit)
pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/*HSIC IPC control the ACTIVE_STATE*/
if (pdata && pdata->noti_host_states)
pdata->noti_host_states(pdev, S5P_HOST_OFF);
#endif
} else if (power_on) {
printk(KERN_DEBUG "%s: EHCI turns on\n", __func__);
if (s5p_ehci->power_on) {
pm_runtime_forbid(dev);
usb_remove_hcd(hcd);
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/*HSIC IPC control the ACTIVE_STATE*/
if (pdata && pdata->noti_host_states)
pdata->noti_host_states(pdev, S5P_HOST_OFF);
#endif
} else
s5p_ehci_phy_init(pdev);
irq = platform_get_irq(pdev, 0);
retval = usb_add_hcd(hcd, irq,
IRQF_DISABLED | IRQF_SHARED);
if (retval < 0) {
dev_err(dev, "Power On Fail\n");
goto exit;
}
s5p_ehci->power_on = 1;
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* Sometimes XMM6262 send remote wakeup when hub enter suspend
* So, set the hub waiting 500ms autosuspend delay*/
if (hcd->self.root_hub)
pm_runtime_set_autosuspend_delay(
&hcd->self.root_hub->dev,
msecs_to_jiffies(500));
/*HSIC IPC control the ACTIVE_STATE*/
if (pdata && pdata->noti_host_states)
pdata->noti_host_states(pdev, S5P_HOST_ON);
#endif
pm_runtime_allow(dev);
}
exit:
device_unlock(dev);
return count;
}
static int __devexit rpckbd_remove(struct platform_device *dev)
{
struct serio *serio = platform_get_drvdata(dev);
serio_unregister_port(serio);
return 0;
}
static int __devexit snd_virmidi_remove(struct platform_device *devptr)
{
snd_card_free(platform_get_drvdata(devptr));
platform_set_drvdata(devptr, NULL);
return 0;
}
int mdp4_dtv_off(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
int ret = 0;
int cndx = 0;
int undx;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
int mixer = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
mdp4_dtv_wait4vsync(cndx);
wake_up_interruptible_all(&vctrl->wait_queue);
pipe = vctrl->base_pipe;
if (pipe != NULL) {
mixer = pipe->mixer_num;
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(mixer);
if (hdmi_prim_display && mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* pipe == rgb2 */
vctrl->base_pipe = NULL;
} else {
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
}
}
mdp4_dtv_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dtv_pipe_clean(vp);
}
ret = panel_next_off(pdev);
mdp_footswitch_ctrl(FALSE);
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
/* Mdp clock disable */
mdp_clk_ctrl(0);
mutex_unlock(&mfd->dma->ov_mutex);
pr_info("%s:\n", __func__);
return ret;
}
static int mddi_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc;
resource_size_t size ;
u32 clk_rate;
if ((pdev->id == 0) && (pdev->num_resources >= 0)) {
mddi_pdata = pdev->dev.platform_data;
size = resource_size(&pdev->resource[0]);
msm_pmdh_base = ioremap(pdev->resource[0].start, size);
MSM_FB_INFO("primary mddi base phy_addr = 0x%x virt = 0x%x\n",
pdev->resource[0].start, (int) msm_pmdh_base);
if (unlikely(!msm_pmdh_base))
return -ENOMEM;
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(1);
mddi_resource_initialized = 1;
return 0;
}
if (!mddi_resource_initialized)
return -EPERM;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
/*
* link to the latest pdev
*/
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCD;
/*
* alloc panel device data
*/
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "mddi_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
/*
* data chain
*/
pdata = mdp_dev->dev.platform_data;
pdata->on = mddi_on;
pdata->off = mddi_off;
pdata->next = pdev;
/*
* get/set panel specific fb info
*/
mfd->panel_info = pdata->panel_info;
if (mfd->index == 0)
mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
else
mfd->fb_imgType = MDP_RGB_565;
clk_rate = mfd->panel_info.clk_max;
if (mddi_pdata &&
mddi_pdata->mddi_sel_clk &&
mddi_pdata->mddi_sel_clk(&clk_rate))
printk(KERN_ERR
"%s: can't select mddi io clk targate rate = %d\n",
__func__, clk_rate);
if (clk_set_max_rate(mddi_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_max_rate failed\n", __func__);
mfd->panel_info.clk_rate = mfd->panel_info.clk_min;
/*
* set driver data
*/
platform_set_drvdata(mdp_dev, mfd);
/*
* register in mdp driver
*/
rc = platform_device_add(mdp_dev);
if (rc)
goto mddi_probe_err;
pdev_list[pdev_list_cnt++] = pdev;
#ifdef CONFIG_HAS_EARLYSUSPEND
mfd->mddi_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
mfd->mddi_early_suspend.suspend = mddi_early_suspend;
mfd->mddi_early_suspend.resume = mddi_early_resume;
register_early_suspend(&mfd->mddi_early_suspend);
#endif
return 0;
mddi_probe_err:
platform_device_put(mdp_dev);
return rc;
}
static int lcdc_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc;
if (pdev->id == 0) {
lcdc_pdata = pdev->dev.platform_data;
return 0;
}
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
/*
* link to the latest pdev
*/
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCDC;
/*
* alloc panel device data
*/
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "lcdc_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
/*
* data chain
*/
pdata = (struct msm_fb_panel_data *)mdp_dev->dev.platform_data;
pdata->on = lcdc_on;
pdata->off = lcdc_off;
pdata->next = pdev;
/*
* get/set panel specific fb info
*/
mfd->panel_info = pdata->panel_info;
#ifdef CONFIG_MSM_FB_RGB565
#ifdef MSMFB_FRAMEBUF_32
mfd->fb_imgType = MDP_RGBA_8888;
#else
mfd->fb_imgType = MDP_RGB_565;
#endif
#else
mfd->fb_imgType = MDP_ARGB_8888;
#endif
fbi = mfd->fbi;
fbi->var.pixclock = mfd->panel_info.clk_rate;
fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch;
fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch;
fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch;
fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width;
fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width;
/*
* set driver data
*/
platform_set_drvdata(mdp_dev, mfd);
/*
* register in mdp driver
*/
rc = platform_device_add(mdp_dev);
if (rc)
goto lcdc_probe_err;
pdev_list[pdev_list_cnt++] = pdev;
return 0;
lcdc_probe_err:
platform_device_put(mdp_dev);
return rc;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int mixer = 0;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
if (pipe == NULL)
return -EINVAL;
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
/* QC Patch for LCD black out Issue */
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
printk(KERN_EMERG "Before Sleep in mdp4_dsi_video_off \n");
msleep(20);
printk(KERN_EMERG "After Sleep in mdp4_dsi_video_off \n");
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
msleep(20);
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
/* QC Patch for LCD black out Issue */
//mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
mdp4_video_vsync_irq_ctrl(cndx, 0);
}
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
static void earjack_debugger_shutdown(struct platform_device *pdev)
{
struct earjack_debugger_device *adev = platform_get_drvdata(pdev);
disable_irq(adev->irq);
}
/* Make sure the controller is quiescent and that we're not using it
* any more. This is mainly for the benefit of programs which, like kexec,
* expect the hardware to be idle: not doing DMA or generating IRQs.
*
* This routine may be called in a damaged or failing kernel. Hence we
* do not acquire the spinlock before shutting down the controller.
*/
static void uhci_hcd_platform_shutdown(struct platform_device *op)
{
struct usb_hcd *hcd = platform_get_drvdata(op);
uhci_hc_died(hcd_to_uhci(hcd));
}
int __devinit omap_mcbsp_init(struct platform_device *pdev)
{
struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
struct resource *res;
int ret = 0;
spin_lock_init(&mcbsp->lock);
mcbsp->free = true;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
if (!res) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(mcbsp->dev, "invalid memory resource\n");
return -ENOMEM;
}
}
if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
dev_name(&pdev->dev))) {
dev_err(mcbsp->dev, "memory region already claimed\n");
return -ENODEV;
}
mcbsp->phys_base = res->start;
mcbsp->reg_cache_size = resource_size(res);
mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!mcbsp->io_base)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
if (!res)
mcbsp->phys_dma_base = mcbsp->phys_base;
else
mcbsp->phys_dma_base = res->start;
mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
if (mcbsp->tx_irq == -ENXIO) {
mcbsp->tx_irq = platform_get_irq(pdev, 0);
mcbsp->rx_irq = 0;
}
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
if (!res) {
dev_err(&pdev->dev, "invalid rx DMA channel\n");
return -ENODEV;
}
mcbsp->dma_data[1].name = "Audio Capture";
mcbsp->dma_data[1].dma_req = res->start;
mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
if (!res) {
dev_err(&pdev->dev, "invalid tx DMA channel\n");
return -ENODEV;
}
mcbsp->dma_data[0].name = "Audio Playback";
mcbsp->dma_data[0].dma_req = res->start;
mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
mcbsp->fclk = clk_get(&pdev->dev, "fck");
if (IS_ERR(mcbsp->fclk)) {
ret = PTR_ERR(mcbsp->fclk);
dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
return ret;
}
mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
if (mcbsp->pdata->buffer_size) {
mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
ret = sysfs_create_group(&mcbsp->dev->kobj,
&additional_attr_group);
if (ret) {
dev_err(mcbsp->dev,
"Unable to create additional controls\n");
goto err_thres;
}
} else {
mcbsp->max_tx_thres = -EINVAL;
mcbsp->max_rx_thres = -EINVAL;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
if (res) {
ret = omap_st_add(mcbsp, res);
if (ret) {
dev_err(mcbsp->dev,
"Unable to create sidetone controls\n");
goto err_st;
}
}
return 0;
err_st:
if (mcbsp->pdata->buffer_size)
sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
err_thres:
clk_put(mcbsp->fclk);
return ret;
}
int mdp4_dtv_on(struct platform_device *pdev)
{
int dtv_width;
int dtv_height;
int dtv_bpp;
int dtv_border_clr;
int dtv_underflow_clr;
int dtv_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
int bpp, ptype;
uint32 format;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *pipe;
int ret;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
fbi = mfd->fbi;
var = &fbi->var;
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf += fbi->var.xoffset * bpp +
fbi->var.yoffset * fbi->fix.line_length;
if (bpp == 2)
format = MDP_RGB_565;
else if (bpp == 3)
format = MDP_RGB_888;
else
format = MDP_ARGB_8888;
if (dtv_pipe == NULL) {
ptype = mdp4_overlay_format2type(format);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1, 0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
return -EBUSY;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER1;
pipe->src_format = format;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DTV);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
dtv_pipe = pipe; /* keep it */
} else {
pipe = dtv_pipe;
}
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->srcp0_addr = (uint32) buf;
pipe->srcp0_ystride = fbi->fix.line_length;
mdp4_overlay_dmae_xy(pipe); /* dma_e */
mdp4_overlay_dmae_cfg(mfd, 0);
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
/*
* DTV timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
dtv_border_clr = mfd->panel_info.lcdc.border_clr;
dtv_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
dtv_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
pr_info("%s: <ID=%d %dx%d (%d,%d,%d), (%d,%d,%d) %dMHz>\n", __func__,
var->reserved[3], var->xres, var->yres,
var->right_margin, var->hsync_len, var->left_margin,
var->lower_margin, var->vsync_len, var->upper_margin,
var->pixclock/1000/1000);
dtv_width = var->xres;
dtv_height = var->yres;
dtv_bpp = mfd->panel_info.bpp;
hsync_period =
hsync_pulse_width + h_back_porch + dtv_width + h_front_porch;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = hsync_pulse_width + h_back_porch;
hsync_end_x = hsync_period - h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(vsync_pulse_width + v_back_porch + dtv_height +
v_front_porch) * hsync_period;
display_v_start =
(vsync_pulse_width + v_back_porch) * hsync_period + dtv_hsync_skew;
display_v_end =
vsync_period - (v_front_porch * hsync_period) + dtv_hsync_skew - 1;
if (dtv_width != var->xres) {
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl =
ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
} else {
active_hctl = 0;
}
if (dtv_height != var->yres) {
active_v_start =
display_v_start + first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
} else {
active_v_start = 0;
active_v_end = 0;
}
dtv_underflow_clr |= 0x80000000; /* enable recovery */
hsync_polarity = fbi->var.yres >= 720 ? 0 : 1;
vsync_polarity = fbi->var.yres >= 720 ? 0 : 1;
data_en_polarity = 0;
ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x8, vsync_period);
MDP_OUTP(MDP_BASE + DTV_BASE + 0xc, vsync_pulse_width * hsync_period);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x18, display_hctl);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x1c, display_v_start);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x20, display_v_end);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x40, dtv_border_clr);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x44, dtv_underflow_clr);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x48, dtv_hsync_skew);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x50, ctrl_polarity);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x2c, active_hctl);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x30, active_v_start);
MDP_OUTP(MDP_BASE + DTV_BASE + 0x38, active_v_end);
/* Test pattern 8 x 8 pixel */
/* MDP_OUTP(MDP_BASE + DTV_BASE + 0x4C, 0x80000808); */
atomic_set(&dtv_on, true);
ret = panel_next_on(pdev);
if (ret == 0) {
/* enable DTV block */
MDP_OUTP(MDP_BASE + DTV_BASE, 1);
mdp_pipe_ctrl(MDP_OVERLAY1_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
dev_info(&pdev->dev, "mdp4_overlay_dtv: on");
} else {
dev_warn(&pdev->dev, "mdp4_overlay_dtv: panel_next_on failed");
}
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
static int s5p_ehci_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
unsigned long flags;
int rc = 0;
#ifdef CONFIG_MDM_HSIC_PM
/*
* check suspend returns 1 if it is possible to suspend
* otherwise, it returns 0 impossible or returns some error
*/
rc = check_udev_suspend_allowed(hsic_pm_dev);
if (rc > 0) {
set_host_stat(hsic_pm_dev, POWER_OFF);
if (wait_dev_pwr_stat(hsic_pm_dev, POWER_OFF) < 0) {
set_host_stat(hsic_pm_dev, POWER_ON);
pm_runtime_resume(&pdev->dev);
return -EBUSY;
}
} else if (rc == -ENODEV) {
/* no hsic pm driver loaded, proceed suspend */
pr_debug("%s: suspend without hsic pm\n", __func__);
} else {
pm_runtime_resume(&pdev->dev);
return -EBUSY;
}
rc = 0;
#endif
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
/* Root hub was already suspended. Disable irq emission and
* mark HW unaccessible, bail out if RH has been resumed. Use
* the spinlock to properly synchronize with possible pending
* RH suspend or resume activity.
*
* This is still racy as hcd->state is manipulated outside of
* any locks =P But that will be a different fix.
*/
spin_lock_irqsave(&ehci->lock, flags);
if (hcd->state != HC_STATE_SUSPENDED && hcd->state != HC_STATE_HALT) {
spin_unlock_irqrestore(&ehci->lock, flags);
return -EINVAL;
}
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
(void)ehci_readl(ehci, &ehci->regs->intr_enable);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
spin_unlock_irqrestore(&ehci->lock, flags);
if (pdata && pdata->phy_exit)
pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
if (pdata && pdata->noti_host_states)
pdata->noti_host_states(pdev, S5P_HOST_OFF);
#endif
clk_disable(s5p_ehci->clk);
return rc;
}
int mdp_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
int dsi_height;
int dsi_bpp;
int dsi_border_clr;
int dsi_underflow_clr;
int dsi_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
uint32 dma2_cfg_reg;
int bpp;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
int ret;
uint32 mask, curr;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
fbi = mfd->fbi;
var = &fbi->var;
vsync_cntrl.dev = mfd->fbi->dev;
atomic_set(&vsync_cntrl.suspend, 0);
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf += calc_fb_offset(mfd, fbi, bpp);
dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_DSI_VIDEO;
if (mfd->fb_imgType == MDP_BGR_565)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else if (mfd->fb_imgType == MDP_RGBA_8888)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (bpp == 2)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
else if (bpp == 3)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
else
dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;
switch (mfd->panel_info.bpp) {
case 24:
dma2_cfg_reg |= DMA_DSTC0G_8BITS |
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
break;
case 18:
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
break;
case 16:
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
break;
default:
printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
mfd->panel_info.bpp);
return -ENODEV;
}
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
/* starting address */
MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x8, (uint32) buf);
/* active window width and height */
MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x4, ((fbi->var.yres) << 16) |
(fbi->var.xres));
/* buffer ystride */
MDP_OUTP(MDP_BASE + DMA_P_BASE + 0xc, fbi->fix.line_length);
/* x/y coordinate = always 0 for lcdc */
MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x10, 0);
/* dma config */
curr = inpdw(MDP_BASE + 0x90000);
mask = 0xBFFFFFFF;
dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
MDP_OUTP(MDP_BASE + DMA_P_BASE, dma2_cfg_reg);
/*
* DSI timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
dsi_border_clr = mfd->panel_info.lcdc.border_clr;
dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
dsi_width = mfd->panel_info.xres;
dsi_height = mfd->panel_info.yres;
dsi_bpp = mfd->panel_info.bpp;
hsync_period = h_back_porch + dsi_width + h_front_porch + 1;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = h_back_porch;
hsync_end_x = dsi_width + h_back_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(v_back_porch + dsi_height + v_front_porch + 1) * hsync_period;
display_v_start = v_back_porch * hsync_period + dsi_hsync_skew;
display_v_end = (dsi_height + v_back_porch) * hsync_period;
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl = ACTIVE_START_X_EN |
(active_h_end << 16) | active_h_start;
active_v_start = display_v_start +
first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
dsi_underflow_clr |= 0x80000000; /* enable recovery */
hsync_polarity = 0;
vsync_polarity = 0;
data_en_polarity = 0;
ctrl_polarity = (data_en_polarity << 2) |
(vsync_polarity << 1) | (hsync_polarity);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc, vsync_pulse_width);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);
ret = panel_next_on(pdev);
if (ret == 0) {
/* enable DSI block */
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
/*Turning on DMA_P block*/
mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
}
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
if (!vsync_cntrl.sysfs_created) {
ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
&vsync_fs_attr_group);
if (ret) {
pr_err("%s: sysfs creation failed, ret=%d\n",
__func__, ret);
return ret;
}
kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
vsync_cntrl.sysfs_created = 1;
}
mdp_histogram_ctrl_all(TRUE);
return ret;
}
static int s5p_ehci_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
clk_enable(s5p_ehci->clk);
pm_runtime_resume(&pdev->dev);
s5p_ehci_phy_init(pdev);
/* if EHCI was off, hcd was removed */
if (!s5p_ehci->power_on) {
dev_info(dev, "Nothing to do for the device (power off)\n");
return 0;
}
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
/* Mark hardware accessible again as we are out of D3 state by now */
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
int mask = INTR_MASK;
if (!hcd->self.root_hub->do_remote_wakeup)
mask &= ~STS_PCD;
ehci_writel(ehci, mask, &ehci->regs->intr_enable);
ehci_readl(ehci, &ehci->regs->intr_enable);
return 0;
}
ehci_dbg(ehci, "lost power, restarting\n");
usb_root_hub_lost_power(hcd->self.root_hub);
(void) ehci_halt(ehci);
(void) ehci_reset(ehci);
/* emptying the schedule aborts any urbs */
spin_lock_irq(&ehci->lock);
if (ehci->reclaim)
end_unlink_async(ehci);
ehci_work(ehci);
spin_unlock_irq(&ehci->lock);
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
/* here we "know" root ports should always stay powered */
ehci_port_power(ehci, 1);
hcd->state = HC_STATE_SUSPENDED;
#ifdef CONFIG_MDM_HSIC_PM
set_host_stat(hsic_pm_dev, POWER_ON);
wait_dev_pwr_stat(hsic_pm_dev, POWER_ON);
#endif
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
s5p_wait_for_cp_resume(pdev, hcd);
#endif
return 0;
}
int mdp_lcdc_on(struct platform_device *pdev)
{
int lcdc_width;
int lcdc_height;
int lcdc_bpp;
int lcdc_border_clr;
int lcdc_underflow_clr;
int lcdc_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
int bpp;
uint32 dma2_cfg_reg;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
uint32 dma_base;
uint32 timer_base = LCDC_BASE;
uint32 block = MDP_DMA2_BLOCK;
int ret;
uint32_t mask, curr;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
fbi = mfd->fbi;
var = &fbi->var;
vsync_cntrl.dev = mfd->fbi->dev;
atomic_set(&vsync_cntrl.suspend, 0);
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf += calc_fb_offset(mfd, fbi, bpp);
dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_LCDC;
if (mfd->fb_imgType == MDP_BGR_565)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else if (mfd->fb_imgType == MDP_RGBA_8888)
dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
else
dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
if (bpp == 2)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
else if (bpp == 3)
dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
else
dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;
switch (mfd->panel_info.bpp) {
case 24:
dma2_cfg_reg |= DMA_DSTC0G_8BITS |
DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
break;
case 18:
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
break;
case 16:
dma2_cfg_reg |= DMA_DSTC0G_6BITS |
DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
break;
default:
printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
mfd->panel_info.bpp);
return -ENODEV;
}
/* DMA register config */
dma_base = DMA_P_BASE;
#ifdef CONFIG_FB_MSM_MDP40
if (mfd->panel.type == HDMI_PANEL)
dma_base = DMA_E_BASE;
#endif
/* starting address */
MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf);
/* active window width and height */
MDP_OUTP(MDP_BASE + dma_base + 0x4, ((fbi->var.yres) << 16) |
(fbi->var.xres));
/* buffer ystride */
MDP_OUTP(MDP_BASE + dma_base + 0xc, fbi->fix.line_length);
/* x/y coordinate = always 0 for lcdc */
MDP_OUTP(MDP_BASE + dma_base + 0x10, 0);
/* dma config */
curr = inpdw(MDP_BASE + DMA_P_BASE);
mask = 0x0FFFFFFF;
dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
MDP_OUTP(MDP_BASE + dma_base, dma2_cfg_reg);
/*
* LCDC timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
lcdc_border_clr = mfd->panel_info.lcdc.border_clr;
lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
lcdc_width = mfd->panel_info.xres;
lcdc_height = mfd->panel_info.yres;
lcdc_bpp = mfd->panel_info.bpp;
hsync_period =
hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = hsync_pulse_width + h_back_porch;
hsync_end_x = hsync_period - h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(vsync_pulse_width + v_back_porch + lcdc_height +
v_front_porch) * hsync_period;
display_v_start =
(vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew;
display_v_end =
vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1;
if (lcdc_width != var->xres) {
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl =
ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
} else {
active_hctl = 0;
}
if (lcdc_height != var->yres) {
active_v_start =
display_v_start + first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
} else {
active_v_start = 0;
active_v_end = 0;
}
#ifdef CONFIG_FB_MSM_MDP40
if (mfd->panel.type == HDMI_PANEL) {
block = MDP_DMA_E_BLOCK;
timer_base = DTV_BASE;
hsync_polarity = 0;
vsync_polarity = 0;
} else {
hsync_polarity = 1;
vsync_polarity = 1;
}
lcdc_underflow_clr |= 0x80000000; /* enable recovery */
#else
hsync_polarity = 0;
vsync_polarity = 0;
#endif
data_en_polarity = 0;
ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
if (!(mfd->cont_splash_done)) {
mdp_pipe_ctrl(MDP_CMD_BLOCK,
MDP_BLOCK_POWER_OFF, FALSE);
MDP_OUTP(MDP_BASE + timer_base, 0);
}
MDP_OUTP(MDP_BASE + timer_base + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + timer_base + 0x8, vsync_period);
MDP_OUTP(MDP_BASE + timer_base + 0xc, vsync_pulse_width * hsync_period);
if (timer_base == LCDC_BASE) {
MDP_OUTP(MDP_BASE + timer_base + 0x10, display_hctl);
MDP_OUTP(MDP_BASE + timer_base + 0x14, display_v_start);
MDP_OUTP(MDP_BASE + timer_base + 0x18, display_v_end);
MDP_OUTP(MDP_BASE + timer_base + 0x28, lcdc_border_clr);
MDP_OUTP(MDP_BASE + timer_base + 0x2c, lcdc_underflow_clr);
MDP_OUTP(MDP_BASE + timer_base + 0x30, lcdc_hsync_skew);
MDP_OUTP(MDP_BASE + timer_base + 0x38, ctrl_polarity);
MDP_OUTP(MDP_BASE + timer_base + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE + timer_base + 0x20, active_v_start);
MDP_OUTP(MDP_BASE + timer_base + 0x24, active_v_end);
} else {
MDP_OUTP(MDP_BASE + timer_base + 0x18, display_hctl);
MDP_OUTP(MDP_BASE + timer_base + 0x1c, display_v_start);
MDP_OUTP(MDP_BASE + timer_base + 0x20, display_v_end);
MDP_OUTP(MDP_BASE + timer_base + 0x40, lcdc_border_clr);
MDP_OUTP(MDP_BASE + timer_base + 0x44, lcdc_underflow_clr);
MDP_OUTP(MDP_BASE + timer_base + 0x48, lcdc_hsync_skew);
MDP_OUTP(MDP_BASE + timer_base + 0x50, ctrl_polarity);
MDP_OUTP(MDP_BASE + timer_base + 0x2c, active_hctl);
MDP_OUTP(MDP_BASE + timer_base + 0x30, active_v_start);
MDP_OUTP(MDP_BASE + timer_base + 0x38, active_v_end);
}
ret = panel_next_on(pdev);
if (ret == 0) {
/* enable LCDC block */
MDP_OUTP(MDP_BASE + timer_base, 1);
mdp_pipe_ctrl(block, MDP_BLOCK_POWER_ON, FALSE);
}
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
if (!vsync_cntrl.sysfs_created) {
ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
&vsync_fs_attr_group);
if (ret) {
pr_err("%s: sysfs creation failed, ret=%d\n",
__func__, ret);
return ret;
}
kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
vsync_cntrl.sysfs_created = 1;
}
return ret;
}
static int m4_keypad_led_remove(struct platform_device *pdev)
{
struct keypad_led_data *info = platform_get_drvdata(pdev);
led_classdev_unregister(&info->keypad_led_class_dev);
return 0;
}
