static int serial_omap_probe(struct platform_device *pdev) { struct uart_omap_port *up; struct resource *mem, *irq; struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; int ret; if (pdev->dev.of_node) omap_up_info = of_get_uart_port_info(&pdev->dev); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); return -ENODEV; } irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!irq) { dev_err(&pdev->dev, "no irq resource?\n"); return -ENODEV; } if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), pdev->dev.driver->name)) { dev_err(&pdev->dev, "memory region already claimed\n"); return -EBUSY; } if (gpio_is_valid(omap_up_info->DTR_gpio) && omap_up_info->DTR_present) { ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); if (ret < 0) return ret; ret = gpio_direction_output(omap_up_info->DTR_gpio, omap_up_info->DTR_inverted); if (ret < 0) return ret; } up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); if (!up) return -ENOMEM; if (gpio_is_valid(omap_up_info->DTR_gpio) && omap_up_info->DTR_present) { up->DTR_gpio = omap_up_info->DTR_gpio; up->DTR_inverted = omap_up_info->DTR_inverted; } else up->DTR_gpio = -EINVAL; up->DTR_active = 0; up->dev = &pdev->dev; up->port.dev = &pdev->dev; up->port.type = PORT_OMAP; up->port.iotype = UPIO_MEM; up->port.irq = irq->start; up->port.regshift = 2; up->port.fifosize = 64; up->port.ops = &serial_omap_pops; if (pdev->dev.of_node) up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); else up->port.line = pdev->id; if (up->port.line < 0) { dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", up->port.line); ret = -ENODEV; goto err_port_line; } up->pins = devm_pinctrl_get_select_default(&pdev->dev); if (IS_ERR(up->pins)) { dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", up->port.line, PTR_ERR(up->pins)); up->pins = NULL; } sprintf(up->name, "OMAP UART%d", up->port.line); up->port.mapbase = mem->start; up->port.membase = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); if (!up->port.membase) { dev_err(&pdev->dev, "can't ioremap UART\n"); ret = -ENOMEM; goto err_ioremap; } up->port.flags = omap_up_info->flags; up->port.uartclk = omap_up_info->uartclk; if (!up->port.uartclk) { up->port.uartclk = DEFAULT_CLK_SPEED; dev_warn(&pdev->dev, "No clock speed specified: using default:" "%d\n", DEFAULT_CLK_SPEED); } up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; pm_qos_add_request(&up->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, up->latency); serial_omap_uart_wq = create_singlethread_workqueue(up->name); INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); platform_set_drvdata(pdev, up); pm_runtime_enable(&pdev->dev); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, omap_up_info->autosuspend_timeout); pm_runtime_irq_safe(&pdev->dev); pm_runtime_get_sync(&pdev->dev); omap_serial_fill_features_erratas(up); ui[up->port.line] = up; serial_omap_add_console_port(up); ret = uart_add_one_port(&serial_omap_reg, &up->port); if (ret != 0) goto err_add_port; pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); return 0; err_add_port: pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); err_ioremap: err_port_line: dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", pdev->id, __func__, ret); return ret; }
static int serial_omap_startup(struct uart_port *port) { struct uart_omap_port *up = to_uart_omap_port(port); unsigned long flags = 0; int retval; /* * Allocate the IRQ */ retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, up->name, up); if (retval) return retval; dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); pm_runtime_get_sync(up->dev); /* * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ serial_omap_clear_fifos(up); /* For Hardware flow control */ serial_out(up, UART_MCR, UART_MCR_RTS); /* * Clear the interrupt registers. */ (void) serial_in(up, UART_LSR); if (serial_in(up, UART_LSR) & UART_LSR_DR) (void) serial_in(up, UART_RX); (void) serial_in(up, UART_IIR); (void) serial_in(up, UART_MSR); /* * Now, initialize the UART */ serial_out(up, UART_LCR, UART_LCR_WLEN8); spin_lock_irqsave(&up->port.lock, flags); /* * Most PC uarts need OUT2 raised to enable interrupts. */ up->port.mctrl |= TIOCM_OUT2; serial_omap_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); up->msr_saved_flags = 0; /* * Finally, enable interrupts. Note: Modem status interrupts * are set via set_termios(), which will be occurring imminently * anyway, so we don't enable them here. */ up->ier = UART_IER_RLSI | UART_IER_RDI; serial_out(up, UART_IER, up->ier); /* Enable module level wake up */ serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); up->port_activity = jiffies; return 0; }
/** * radeon_driver_load_kms - Main load function for KMS. * * @dev: drm dev pointer * @flags: device flags * * This is the main load function for KMS (all asics). * It calls radeon_device_init() to set up the non-display * parts of the chip (asic init, CP, writeback, etc.), and * radeon_modeset_init() to set up the display parts * (crtcs, encoders, hotplug detect, etc.). * Returns 0 on success, error on failure. */ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) { struct radeon_device *rdev; int r, acpi_status; if (!radeon_si_support) { switch (flags & RADEON_FAMILY_MASK) { case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: dev_info(dev->dev, "SI support disabled by module param\n"); return -ENODEV; } } if (!radeon_cik_support) { switch (flags & RADEON_FAMILY_MASK) { case CHIP_KAVERI: case CHIP_BONAIRE: case CHIP_HAWAII: case CHIP_KABINI: case CHIP_MULLINS: dev_info(dev->dev, "CIK support disabled by module param\n"); return -ENODEV; } } rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); if (rdev == NULL) { return -ENOMEM; } dev->dev_private = (void *)rdev; /* update BUS flag */ if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) { flags |= RADEON_IS_AGP; } else if (pci_is_pcie(dev->pdev)) { flags |= RADEON_IS_PCIE; } else { flags |= RADEON_IS_PCI; } if ((radeon_runtime_pm != 0) && radeon_has_atpx() && ((flags & RADEON_IS_IGP) == 0) && !pci_is_thunderbolt_attached(dev->pdev)) flags |= RADEON_IS_PX; /* radeon_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = radeon_device_init(rdev, dev, dev->pdev, flags); if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } /* Again modeset_init should fail only on fatal error * otherwise it should provide enough functionalities * for shadowfb to run */ r = radeon_modeset_init(rdev); if (r) dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); /* Call ACPI methods: require modeset init * but failure is not fatal */ if (!r) { acpi_status = radeon_acpi_init(rdev); if (acpi_status) dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); } if (radeon_is_px(dev)) { dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); pm_runtime_set_active(dev->dev); pm_runtime_allow(dev->dev); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); } out: if (r) radeon_driver_unload_kms(dev); return r; }
static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) { pm_runtime_mark_last_busy(mcspi->dev); pm_runtime_put_autosuspend(mcspi->dev); }
int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev) { unsigned int i; u32 val; if (!is_power_of_2(mgmtdev->max_write_request) || (mgmtdev->max_write_request < 128) || (mgmtdev->max_write_request > 1024)) { dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", mgmtdev->max_write_request); return -EINVAL; } if (!is_power_of_2(mgmtdev->max_read_request) || (mgmtdev->max_read_request < 128) || (mgmtdev->max_read_request > 1024)) { dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n", mgmtdev->max_read_request); return -EINVAL; } if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) { dev_err(&mgmtdev->pdev->dev, "max_wr_xactions cannot be bigger than %ld\n", HIDMA_MAX_WR_XACTIONS_MASK); return -EINVAL; } if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) { dev_err(&mgmtdev->pdev->dev, "max_rd_xactions cannot be bigger than %ld\n", HIDMA_MAX_RD_XACTIONS_MASK); return -EINVAL; } for (i = 0; i < mgmtdev->dma_channels; i++) { if (mgmtdev->priority[i] > 1) { dev_err(&mgmtdev->pdev->dev, "priority can be 0 or 1\n"); return -EINVAL; } if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) { dev_err(&mgmtdev->pdev->dev, "max value of weight can be %d.\n", HIDMA_MAX_CHANNEL_WEIGHT); return -EINVAL; } /* weight needs to be at least one */ if (mgmtdev->weight[i] == 0) mgmtdev->weight[i] = 1; } pm_runtime_get_sync(&mgmtdev->pdev->dev); val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS); val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS; val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK; val |= mgmtdev->max_read_request; writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS); val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS; val &= ~HIDMA_MAX_RD_XACTIONS_MASK; val |= mgmtdev->max_rd_xactions; writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); mgmtdev->hw_version = readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET); mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF; mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF; for (i = 0; i < mgmtdev->dma_channels; i++) { u32 weight = mgmtdev->weight[i]; u32 priority = mgmtdev->priority[i]; val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); val &= ~(1 << HIDMA_PRIORITY_BIT_POS); val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS; val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS); val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS; writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); } val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); val &= ~HIDMA_CHRESET_TIMEOUT_MASK; val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK; writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); pm_runtime_mark_last_busy(&mgmtdev->pdev->dev); pm_runtime_put_autosuspend(&mgmtdev->pdev->dev); return 0; }
static ssize_t boot_acl_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct tb *tb = container_of(dev, struct tb, dev); char *str, *s, *uuid_str; ssize_t ret = 0; uuid_t *acl; int i = 0; /* * Make sure the value is not bigger than tb->nboot_acl * UUID * length + commas and optional "\n". Also the smallest allowable * string is tb->nboot_acl * ",". */ if (count > (UUID_STRING_LEN + 1) * tb->nboot_acl + 1) return -EINVAL; if (count < tb->nboot_acl - 1) return -EINVAL; str = kstrdup(buf, GFP_KERNEL); if (!str) return -ENOMEM; acl = kcalloc(tb->nboot_acl, sizeof(uuid_t), GFP_KERNEL); if (!acl) { ret = -ENOMEM; goto err_free_str; } uuid_str = strim(str); while ((s = strsep(&uuid_str, ",")) != NULL && i < tb->nboot_acl) { size_t len = strlen(s); if (len) { if (len != UUID_STRING_LEN) { ret = -EINVAL; goto err_free_acl; } ret = uuid_parse(s, &acl[i]); if (ret) goto err_free_acl; } i++; } if (s || i < tb->nboot_acl) { ret = -EINVAL; goto err_free_acl; } pm_runtime_get_sync(&tb->dev); if (mutex_lock_interruptible(&tb->lock)) { ret = -ERESTARTSYS; goto err_rpm_put; } ret = tb->cm_ops->set_boot_acl(tb, acl, tb->nboot_acl); if (!ret) { /* Notify userspace about the change */ kobject_uevent(&tb->dev.kobj, KOBJ_CHANGE); } mutex_unlock(&tb->lock); err_rpm_put: pm_runtime_mark_last_busy(&tb->dev); pm_runtime_put_autosuspend(&tb->dev); err_free_acl: kfree(acl); err_free_str: kfree(str); return ret ?: count; }
static void serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { struct uart_omap_port *up = to_uart_omap_port(port); unsigned char cval = 0; unsigned long flags = 0; unsigned int baud, quot; switch (termios->c_cflag & CSIZE) { case CS5: cval = UART_LCR_WLEN5; break; case CS6: cval = UART_LCR_WLEN6; break; case CS7: cval = UART_LCR_WLEN7; break; default: case CS8: cval = UART_LCR_WLEN8; break; } if (termios->c_cflag & CSTOPB) cval |= UART_LCR_STOP; if (termios->c_cflag & PARENB) cval |= UART_LCR_PARITY; if (!(termios->c_cflag & PARODD)) cval |= UART_LCR_EPAR; if (termios->c_cflag & CMSPAR) cval |= UART_LCR_SPAR; /* * Ask the core to calculate the divisor for us. */ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); quot = serial_omap_get_divisor(port, baud); /* calculate wakeup latency constraint */ up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); up->latency = up->calc_latency; schedule_work(&up->qos_work); up->dll = quot & 0xff; up->dlh = quot >> 8; up->mdr1 = UART_OMAP_MDR1_DISABLE; up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | UART_FCR_ENABLE_FIFO; /* * Ok, we're now changing the port state. Do it with * interrupts disabled. */ pm_runtime_get_sync(up->dev); spin_lock_irqsave(&up->port.lock, flags); /* * Update the per-port timeout. */ uart_update_timeout(port, termios->c_cflag, baud); up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; if (termios->c_iflag & INPCK) up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; if (termios->c_iflag & (BRKINT | PARMRK)) up->port.read_status_mask |= UART_LSR_BI; /* * Characters to ignore */ up->port.ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; if (termios->c_iflag & IGNBRK) { up->port.ignore_status_mask |= UART_LSR_BI; /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (termios->c_iflag & IGNPAR) up->port.ignore_status_mask |= UART_LSR_OE; } /* * ignore all characters if CREAD is not set */ if ((termios->c_cflag & CREAD) == 0) up->port.ignore_status_mask |= UART_LSR_DR; /* * Modem status interrupts */ up->ier &= ~UART_IER_MSI; if (UART_ENABLE_MS(&up->port, termios->c_cflag)) up->ier |= UART_IER_MSI; serial_out(up, UART_IER, up->ier); serial_out(up, UART_LCR, cval); /* reset DLAB */ up->lcr = cval; up->scr = 0; /* FIFOs and DMA Settings */ /* FCR can be changed only when the * baud clock is not running * DLL_REG and DLH_REG set to 0. */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_DLL, 0); serial_out(up, UART_DLM, 0); serial_out(up, UART_LCR, 0); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; up->efr &= ~UART_EFR_SCD; serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); /* FIFO ENABLE, DMA MODE */ up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; /* * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK * sets Enables the granularity of 1 for TRIGGER RX * level. Along with setting RX FIFO trigger level * to 1 (as noted below, 16 characters) and TLR[3:0] * to zero this will result RX FIFO threshold level * to 1 character, instead of 16 as noted in comment * below. */ /* Set receive FIFO threshold to 16 characters and * transmit FIFO threshold to 32 spaces */ up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | UART_FCR_ENABLE_FIFO; serial_out(up, UART_FCR, up->fcr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_OMAP_SCR, up->scr); /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); /* Protocol, Baud Rate, and Interrupt Settings */ if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) serial_omap_mdr1_errataset(up, up->mdr1); else serial_out(up, UART_OMAP_MDR1, up->mdr1); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, 0); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_DLL, up->dll); /* LS of divisor */ serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, up->ier); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, cval); if (!serial_omap_baud_is_mode16(port, baud)) up->mdr1 = UART_OMAP_MDR1_13X_MODE; else up->mdr1 = UART_OMAP_MDR1_16X_MODE; if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) serial_omap_mdr1_errataset(up, up->mdr1); else serial_out(up, UART_OMAP_MDR1, up->mdr1); /* Configure flow control */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ serial_out(up, UART_XON1, termios->c_cc[VSTART]); serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); /* Enable access to TCR/TLR */ serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { /* Enable AUTORTS and AUTOCTS */ up->efr |= UART_EFR_CTS | UART_EFR_RTS; /* Ensure MCR RTS is asserted */ up->mcr |= UART_MCR_RTS; } else { /* Disable AUTORTS and AUTOCTS */ up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); } if (up->port.flags & UPF_SOFT_FLOW) { /* clear SW control mode bits */ up->efr &= OMAP_UART_SW_CLR; /* * IXON Flag: * Enable XON/XOFF flow control on input. * Receiver compares XON1, XOFF1. */ if (termios->c_iflag & IXON) up->efr |= OMAP_UART_SW_RX; /* * IXOFF Flag: * Enable XON/XOFF flow control on output. * Transmit XON1, XOFF1 */ if (termios->c_iflag & IXOFF) up->efr |= OMAP_UART_SW_TX; /* * IXANY Flag: * Enable any character to restart output. * Operation resumes after receiving any * character after recognition of the XOFF character */ if (termios->c_iflag & IXANY) up->mcr |= UART_MCR_XONANY; else up->mcr &= ~UART_MCR_XONANY; } serial_out(up, UART_MCR, up->mcr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, up->lcr); serial_omap_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); }
static int hidma_mgmt_probe(struct platform_device *pdev) { struct hidma_mgmt_dev *mgmtdev; struct resource *res; void __iomem *virtaddr; int irq; int rc; u32 val; pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); virtaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(virtaddr)) { rc = -ENOMEM; goto out; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "irq resources not found\n"); rc = irq; goto out; } mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL); if (!mgmtdev) { rc = -ENOMEM; goto out; } mgmtdev->pdev = pdev; mgmtdev->addrsize = resource_size(res); mgmtdev->virtaddr = virtaddr; rc = device_property_read_u32(&pdev->dev, "dma-channels", &mgmtdev->dma_channels); if (rc) { dev_err(&pdev->dev, "number of channels missing\n"); goto out; } rc = device_property_read_u32(&pdev->dev, "channel-reset-timeout-cycles", &mgmtdev->chreset_timeout_cycles); if (rc) { dev_err(&pdev->dev, "channel reset timeout missing\n"); goto out; } rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes", &mgmtdev->max_write_request); if (rc) { dev_err(&pdev->dev, "max-write-burst-bytes missing\n"); goto out; } if (max_write_request) { dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n", max_write_request); mgmtdev->max_write_request = max_write_request; } else max_write_request = mgmtdev->max_write_request; rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes", &mgmtdev->max_read_request); if (rc) { dev_err(&pdev->dev, "max-read-burst-bytes missing\n"); goto out; } if (max_read_request) { dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n", max_read_request); mgmtdev->max_read_request = max_read_request; } else max_read_request = mgmtdev->max_read_request; rc = device_property_read_u32(&pdev->dev, "max-write-transactions", &mgmtdev->max_wr_xactions); if (rc) { dev_err(&pdev->dev, "max-write-transactions missing\n"); goto out; } if (max_wr_xactions) { dev_info(&pdev->dev, "overriding max-write-transactions: %d\n", max_wr_xactions); mgmtdev->max_wr_xactions = max_wr_xactions; } else max_wr_xactions = mgmtdev->max_wr_xactions; rc = device_property_read_u32(&pdev->dev, "max-read-transactions", &mgmtdev->max_rd_xactions); if (rc) { dev_err(&pdev->dev, "max-read-transactions missing\n"); goto out; } if (max_rd_xactions) { dev_info(&pdev->dev, "overriding max-read-transactions: %d\n", max_rd_xactions); mgmtdev->max_rd_xactions = max_rd_xactions; } else max_rd_xactions = mgmtdev->max_rd_xactions; mgmtdev->priority = devm_kcalloc(&pdev->dev, mgmtdev->dma_channels, sizeof(*mgmtdev->priority), GFP_KERNEL); if (!mgmtdev->priority) { rc = -ENOMEM; goto out; } mgmtdev->weight = devm_kcalloc(&pdev->dev, mgmtdev->dma_channels, sizeof(*mgmtdev->weight), GFP_KERNEL); if (!mgmtdev->weight) { rc = -ENOMEM; goto out; } rc = hidma_mgmt_setup(mgmtdev); if (rc) { dev_err(&pdev->dev, "setup failed\n"); goto out; } /* start the HW */ val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET); val |= 1; writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET); rc = hidma_mgmt_init_sys(mgmtdev); if (rc) { dev_err(&pdev->dev, "sysfs setup failed\n"); goto out; } dev_info(&pdev->dev, "HW rev: %d.%d @ %pa with %d physical channels\n", mgmtdev->hw_version_major, mgmtdev->hw_version_minor, &res->start, mgmtdev->dma_channels); platform_set_drvdata(pdev, mgmtdev); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); return 0; out: pm_runtime_put_sync_suspend(&pdev->dev); pm_runtime_disable(&pdev->dev); return rc; }
static int sdhci_pxav3_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; struct sdhci_pxa *pxa = NULL; const struct of_device_id *match; int ret; struct clk *clk; pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); if (!pxa) return -ENOMEM; host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0); if (IS_ERR(host)) { kfree(pxa); return PTR_ERR(host); } pltfm_host = sdhci_priv(host); pltfm_host->priv = pxa; clk = clk_get(dev, NULL); if (IS_ERR(clk)) { dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(clk); goto err_clk_get; } pltfm_host->clk = clk; clk_prepare_enable(clk); /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); if (match) { ret = mmc_of_parse(host->mmc); if (ret) goto err_of_parse; sdhci_get_of_property(pdev); pdata = pxav3_get_mmc_pdata(dev); } else if (pdata) { /* on-chip device */ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) host->mmc->caps |= MMC_CAP_NONREMOVABLE; /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; if (pdata->quirks) host->quirks |= pdata->quirks; if (pdata->quirks2) host->quirks2 |= pdata->quirks2; if (pdata->host_caps) host->mmc->caps |= pdata->host_caps; if (pdata->host_caps2) host->mmc->caps2 |= pdata->host_caps2; if (pdata->pm_caps) host->mmc->pm_caps |= pdata->pm_caps; if (gpio_is_valid(pdata->ext_cd_gpio)) { ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, 0); if (ret) { dev_err(mmc_dev(host->mmc), "failed to allocate card detect gpio\n"); goto err_cd_req; } } } pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); pm_runtime_use_autosuspend(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, 1); ret = sdhci_add_host(host); if (ret) { dev_err(&pdev->dev, "failed to add host\n"); goto err_add_host; } platform_set_drvdata(pdev, host); if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) { device_init_wakeup(&pdev->dev, 1); host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ; } else { device_init_wakeup(&pdev->dev, 0); } pm_runtime_put_autosuspend(&pdev->dev); return 0; err_of_parse: err_cd_req: err_add_host: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); clk_disable_unprepare(clk); clk_put(clk); err_clk_get: sdhci_pltfm_free(pdev); kfree(pxa); return ret; }
static int serial_omap_probe(struct platform_device *pdev) { struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); struct uart_omap_port *up; struct resource *mem; void __iomem *base; int uartirq = 0; int wakeirq = 0; int ret; enum of_gpio_flags flags; int gpio_sel; unsigned long gpio_flags; /* The optional wakeirq may be specified in the board dts file */ if (pdev->dev.of_node) { uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); if (!uartirq) return -EPROBE_DEFER; wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); omap_up_info = of_get_uart_port_info(&pdev->dev); pdev->dev.platform_data = omap_up_info; } else { uartirq = platform_get_irq(pdev, 0); if (uartirq < 0) return -EPROBE_DEFER; } /* Check if the UART needs to be selected */ gpio_sel = of_get_gpio_flags(pdev->dev.of_node, 0, &flags); if (gpio_is_valid(gpio_sel)) { dev_dbg(&pdev->dev, "using gpio %d for uart%d_sel\n", gpio_sel, pdev->id); gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH; ret = devm_gpio_request_one(&pdev->dev, gpio_sel, gpio_flags, "uart_sel"); if (ret) { dev_err(&pdev->dev, "gpio%d request failed, ret %d\n", gpio_sel, ret); return ret; } } else if (gpio_sel == -EPROBE_DEFER) { return -EPROBE_DEFER; } up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); if (!up) return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(base)) return PTR_ERR(base); up->dev = &pdev->dev; up->port.dev = &pdev->dev; up->port.type = PORT_OMAP; up->port.iotype = UPIO_MEM; up->port.irq = uartirq; up->wakeirq = wakeirq; if (!up->wakeirq) dev_info(up->port.dev, "no wakeirq for uart%d\n", up->port.line); up->port.regshift = 2; up->port.fifosize = 64; up->port.ops = &serial_omap_pops; if (pdev->dev.of_node) up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); else up->port.line = pdev->id; if (up->port.line < 0) { dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", up->port.line); ret = -ENODEV; goto err_port_line; } if (up->port.line >= OMAP_MAX_HSUART_PORTS) { dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, OMAP_MAX_HSUART_PORTS); ret = -ENXIO; goto err_port_line; } ret = serial_omap_probe_rs485(up, pdev->dev.of_node); if (ret < 0) goto err_rs485; sprintf(up->name, "OMAP UART%d", up->port.line); up->port.mapbase = mem->start; up->port.membase = base; up->port.flags = omap_up_info->flags; up->port.uartclk = omap_up_info->uartclk; if (!up->port.uartclk) { up->port.uartclk = DEFAULT_CLK_SPEED; dev_warn(&pdev->dev, "No clock speed specified: using default: %d\n", DEFAULT_CLK_SPEED); } up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; pm_qos_add_request(&up->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, up->latency); INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); platform_set_drvdata(pdev, up); if (omap_up_info->autosuspend_timeout == 0) omap_up_info->autosuspend_timeout = -1; device_init_wakeup(up->dev, true); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, omap_up_info->autosuspend_timeout); pm_runtime_irq_safe(&pdev->dev); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); omap_serial_fill_features_erratas(up); ui[up->port.line] = up; serial_omap_add_console_port(up); ret = uart_add_one_port(&serial_omap_reg, &up->port); if (ret != 0) goto err_add_port; pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); return 0; err_add_port: pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); err_rs485: err_port_line: dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", pdev->id, __func__, ret); return ret; }
static int twl4030_usb_probe(struct platform_device *pdev) { struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev); struct twl4030_usb *twl; struct phy *phy; int status, err; struct usb_otg *otg; struct device_node *np = pdev->dev.of_node; struct phy_provider *phy_provider; twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); if (!twl) return -ENOMEM; if (np) of_property_read_u32(np, "usb_mode", (enum twl4030_usb_mode *)&twl->usb_mode); else if (pdata) { twl->usb_mode = pdata->usb_mode; } else { dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); return -EINVAL; } otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); if (!otg) return -ENOMEM; twl->dev = &pdev->dev; twl->irq = platform_get_irq(pdev, 0); twl->vbus_supplied = false; twl->linkstat = OMAP_MUSB_UNKNOWN; twl->phy.dev = twl->dev; twl->phy.label = "twl4030"; twl->phy.otg = otg; twl->phy.type = USB_PHY_TYPE_USB2; otg->usb_phy = &twl->phy; otg->set_host = twl4030_set_host; otg->set_peripheral = twl4030_set_peripheral; phy = devm_phy_create(twl->dev, NULL, &ops); if (IS_ERR(phy)) { dev_dbg(&pdev->dev, "Failed to create PHY\n"); return PTR_ERR(phy); } phy_set_drvdata(phy, twl); phy_provider = devm_of_phy_provider_register(twl->dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) return PTR_ERR(phy_provider); /* init mutex for workqueue */ mutex_init(&twl->lock); INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); err = twl4030_usb_ldo_init(twl); if (err) { dev_err(&pdev->dev, "ldo init failed\n"); return err; } usb_add_phy_dev(&twl->phy); platform_set_drvdata(pdev, twl); if (device_create_file(&pdev->dev, &dev_attr_vbus)) dev_warn(&pdev->dev, "could not create sysfs file\n"); ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); /* Our job is to use irqs and status from the power module * to keep the transceiver disabled when nothing's connected. * * FIXME we actually shouldn't start enabling it until the * USB controller drivers have said they're ready, by calling * set_host() and/or set_peripheral() ... OTG_capable boards * need both handles, otherwise just one suffices. */ status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, twl4030_usb_irq, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); if (status < 0) { dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", twl->irq, status); return status; } if (pdata) err = phy_create_lookup(phy, "usb", "musb-hdrc.0"); if (err) return err; pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(twl->dev); dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); return 0; }
static void serial_omap_stop_tx(struct uart_port *port) { struct uart_omap_port *up = to_uart_omap_port(port); int res; pm_runtime_get_sync(up->dev); /* Handle RS-485 */ if (up->rs485.flags & SER_RS485_ENABLED) { if (up->scr & OMAP_UART_SCR_TX_EMPTY) { /* THR interrupt is fired when both TX FIFO and TX * shift register are empty. This means there's nothing * left to transmit now, so make sure the THR interrupt * is fired when TX FIFO is below the trigger level, * disable THR interrupts and toggle the RS-485 GPIO * data direction pin if needed. */ up->scr &= ~OMAP_UART_SCR_TX_EMPTY; serial_out(up, UART_OMAP_SCR, up->scr); res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0; if (gpio_get_value(up->rts_gpio) != res) { if (up->rs485.delay_rts_after_send > 0) mdelay(up->rs485.delay_rts_after_send); gpio_set_value(up->rts_gpio, res); } } else { /* We're asked to stop, but there's still stuff in the * UART FIFO, so make sure the THR interrupt is fired * when both TX FIFO and TX shift register are empty. * The next THR interrupt (if no transmission is started * in the meantime) will indicate the end of a * transmission. Therefore we _don't_ disable THR * interrupts in this situation. */ up->scr |= OMAP_UART_SCR_TX_EMPTY; serial_out(up, UART_OMAP_SCR, up->scr); return; } } if (up->ier & UART_IER_THRI) { up->ier &= ~UART_IER_THRI; serial_out(up, UART_IER, up->ier); } if ((up->rs485.flags & SER_RS485_ENABLED) && !(up->rs485.flags & SER_RS485_RX_DURING_TX)) { /* * Empty the RX FIFO, we are not interested in anything * received during the half-duplex transmission. */ serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); /* Re-enable RX interrupts */ up->ier |= UART_IER_RLSI | UART_IER_RDI; up->port.read_status_mask |= UART_LSR_DR; serial_out(up, UART_IER, up->ier); } pm_runtime_mark_last_busy(up->dev); pm_runtime_put_autosuspend(up->dev); }
/** * radeon_driver_load_kms - Main load function for KMS. * * @dev: drm dev pointer * @flags: device flags * * This is the main load function for KMS (all asics). * It calls radeon_device_init() to set up the non-display * parts of the chip (asic init, CP, writeback, etc.), and * radeon_modeset_init() to set up the display parts * (crtcs, encoders, hotplug detect, etc.). * Returns 0 on success, error on failure. */ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) { struct radeon_device *rdev; int r, acpi_status; rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); if (rdev == NULL) { return -ENOMEM; } dev->dev_private = (void *)rdev; /* update BUS flag */ if (drm_pci_device_is_agp(dev)) { flags |= RADEON_IS_AGP; } else if (pci_is_pcie(dev->pdev)) { flags |= RADEON_IS_PCIE; } else { flags |= RADEON_IS_PCI; } /* radeon_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = radeon_device_init(rdev, dev, dev->pdev, flags); if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } /* Again modeset_init should fail only on fatal error * otherwise it should provide enough functionalities * for shadowfb to run */ r = radeon_modeset_init(rdev); if (r) dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); /* Call ACPI methods: require modeset init * but failure is not fatal */ if (!r) { acpi_status = radeon_acpi_init(rdev); if (acpi_status) dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); } if (radeon_runtime_pm != 0) { pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); pm_runtime_set_active(dev->dev); pm_runtime_allow(dev->dev); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); } out: if (r) radeon_driver_unload_kms(dev); return r; }
static long link_pm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int value, err = 0; struct task_struct *task = get_current(); struct link_pm_data *pm_data = file->private_data; struct usb_link_device *usb_ld = pm_data->usb_ld; char taskname[TASK_COMM_LEN]; pr_info("mif: %s: 0x%08x\n", __func__, cmd); switch (cmd) { case IOCTL_LINK_CONTROL_ACTIVE: if (copy_from_user(&value, (const void __user *)arg, sizeof(int))) return -EFAULT; gpio_set_value(pm_data->gpio_link_active, value); break; case IOCTL_LINK_GET_HOSTWAKE: return !gpio_get_value(pm_data->gpio_link_hostwake); case IOCTL_LINK_CONNECTED: return pm_data->usb_ld->if_usb_connected; case IOCTL_LINK_PORT_ON: /* hub only */ /* ignore cp host wakeup irq, set the hub_init_lock when AP try CP off and release hub_init_lock when CP boot done */ pm_data->hub_init_lock = 0; if (pm_data->root_hub) { pm_runtime_resume(pm_data->root_hub); pm_runtime_forbid(pm_data->root_hub->parent); } if (pm_data->port_enable) { err = pm_data->port_enable(2, 1); if (err < 0) { pr_err("mif: %s: hub on fail err=%d\n", __func__, err); goto exit; } pm_data->hub_status = HUB_STATE_RESUMMING; } break; case IOCTL_LINK_PORT_OFF: /* hub only */ if (pm_data->usb_ld->if_usb_connected) { struct usb_device *udev = pm_data->usb_ld->usbdev->parent; pm_runtime_get_sync(&udev->dev); if (udev->state != USB_STATE_NOTATTACHED) { usb_force_disconnect(udev); pr_info("force disconnect maybe cp-reset!!\n"); } pm_runtime_put_autosuspend(&udev->dev); } err = link_pm_hub_standby(pm_data); if (err < 0) { pr_err("mif: %s: usb3503 active fail\n", __func__); goto exit; } pm_data->hub_init_lock = 1; pm_data->hub_handshake_done = 0; break; case IOCTL_LINK_BLOCK_AUTOSUSPEND: /* block autosuspend forever */ mif_info("blocked autosuspend by `%s(%d)'\n", get_task_comm(taskname, task), task->pid); pm_data->block_autosuspend = true; if (usb_ld->usbdev) pm_runtime_forbid(&usb_ld->usbdev->dev); else { mif_err("Block autosuspend failed\n"); err = -ENODEV; } break; case IOCTL_LINK_ENABLE_AUTOSUSPEND: /* Enable autosuspend */ mif_info("autosuspend enabled by `%s(%d)'\n", get_task_comm(taskname, task), task->pid); pm_data->block_autosuspend = false; if (usb_ld->usbdev) pm_runtime_allow(&usb_ld->usbdev->dev); else { mif_err("Enable autosuspend failed\n"); err = -ENODEV; } break; default: break; } exit: return err; }
void dx_sep_pm_runtime_put(void) { pm_runtime_mark_last_busy(power_control.drvdata->dev); pm_runtime_put_autosuspend(power_control.drvdata->dev); }