static int radix__init_new_context(struct mm_struct *mm) { unsigned long rts_field; int index, max_id; max_id = (1 << mmu_pid_bits) - 1; index = alloc_context_id(mmu_base_pid, max_id); if (index < 0) return index; /* * set the process table entry, */ rts_field = radix__get_tree_size(); process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE); /* * Order the above store with subsequent update of the PID * register (at which point HW can start loading/caching * the entry) and the corresponding load by the MMU from * the L2 cache. */ asm volatile("ptesync;isync" : : : "memory"); mm->context.npu_context = NULL; return index; }
static int radix__init_new_context(struct mm_struct *mm, int index) { unsigned long rts_field; /* * set the process table entry, */ rts_field = radix__get_tree_size(); process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE); return 0; }