/*----------------------------------------------------------------------- * Write a word or halfword to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ static int write_data(flash_info_t * info, ulong dest, FPW data) { FPWV *addr = (FPWV *) dest; ulong status; int flag; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr); return (2); } /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); *addr = (FPW) 0x00400040; /* write setup */ *addr = data; /* arm simple, non interrupt dependent timer */ reset_timer_masked(); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } } *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (0); }
/* delay usec useconds */ void udelay (unsigned long usec) { ulong tmo, tmp; if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ tmo *= MS_TO_US; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * MS_TO_US; tmo /= (1000 * 1000); } tmp = get_timer (0); /* get current timestamp */ if ((tmo + tmp + 1) < tmp) /* if setting this fordward will roll time stamp */ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ else tmo += tmp; /* else, set advancing stamp wake up time */ while (get_timer_masked () < tmo) /* loop till event */ /*NOP*/; }
int timer_init (void) { /* * Set clock frequency in the system controller: * VERSATILE_REFCLK is 32KHz * VERSATILE_TIMCLK is 1MHz */ *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); /* * Now setup timer0 */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = CONFIG_SYS_TIMER_RELOAD; /* TimerLoad */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 4) = CONFIG_SYS_TIMER_RELOAD; /* TimerValue */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) |= 0x82; /* Enabled, * free running, * no interrupt, * 32-bit, * wrapping */ reset_timer_masked(); return 0; }
void udelay (unsigned long usec) { ulong tmo,tmp; /* normalize */ if (usec >= 1000) { tmo = usec / 1000; tmo *= CFG_HZ; tmo /= 1000; } else { if (usec > 1) { tmo = usec * CFG_HZ; tmo /= (1000*1000); } else tmo = 1; } /* check for rollover during this delay */ tmp = get_timer (0); if ((tmp + tmo) < tmp ) reset_timer_masked(); /* timer would roll over */ else tmo += tmp; while (get_timer_masked () < tmo); }
/* starts up a counter * - the Integrator/CP timer can be set up to issue an interrupt * - but it isn't here */ int interrupt_init (void) { /* Load timer with initial value */ *(volatile u32 *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; /* Set timer to be * enabled 1 * periodic 1 * no interrupts 0 * X 0 * clock divisor 1 00 * (if this is changed then * div_clock must be changed * accordingly) * 32 bit 1 * wrapping 0 */ *(volatile u32 *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2; div_clock = 1; /* init the timestamp */ total_count = 0UL; reset_timer_masked(); div_timer = (CONFIG_SYS_HZ_CLOCK / CFG_HZ); div_timer /= div_clock; return (0); }
/*------------------------------------------------------------------------------ * u-boot timer interface */ int timer_init(void) { if (g_inittimer) return 0; NX_TIMER_SetClockDivisorEnable(CFG_TIMER_SYS_TICK_CH, CFALSE); NX_TIMER_SetClockSource(CFG_TIMER_SYS_TICK_CH, 0, CFG_TIMER_SYS_TICK_CLKSRC); NX_TIMER_SetClockDivisor(CFG_TIMER_SYS_TICK_CH, 0, CFG_TIMER_SYS_TICK_CLKDIV); NX_TIMER_SetClockPClkMode(CFG_TIMER_SYS_TICK_CH, NX_PCLKMODE_ALWAYS); NX_TIMER_SetClockDivisorEnable(CFG_TIMER_SYS_TICK_CH, CTRUE); NX_TIMER_Stop(CFG_TIMER_SYS_TICK_CH); NX_TIMER_SetWatchDogEnable(CFG_TIMER_SYS_TICK_CH, CFALSE); NX_TIMER_SetInterruptEnableAll(CFG_TIMER_SYS_TICK_CH, CFALSE); NX_TIMER_ClearInterruptPendingAll(CFG_TIMER_SYS_TICK_CH); NX_TIMER_SetTClkDivider(CFG_TIMER_SYS_TICK_CH, NX_TIMER_CLOCK_TCLK); NX_TIMER_SetTimerCounter(CFG_TIMER_SYS_TICK_CH, 0); NX_TIMER_SetMatchCounter(CFG_TIMER_SYS_TICK_CH, CFG_TIMER_SYS_TICK_CLKFREQ); NX_TIMER_Run(CFG_TIMER_SYS_TICK_CH); reset_timer_masked(); g_inittimer = 1; return 0; }
/*----------------------------------------------------------------------- * Write a byte to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ static int write_byte(flash_info_t *info, ulong dest, uchar data) { vu_char *caddr = (vu_char *)(info->start[0]); int flag; /* Check if Flash is (sufficiently) erased */ if ((*((vu_char *) dest) & data) != data) { return (ERR_NOT_ERASED); } /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); caddr[0xAAA] = 0xAA; caddr[0x555] = 0x55; caddr[0xAAA] = 0xA0; *((vu_char *)dest) = data; /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* data polling for D7 */ reset_timer_masked(); while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { return (ERR_TIMOUT); } } return (ERR_OK); }
int timer_init (void) { ulong tmr_ctrl_val; /* 1st disable the Timer */ tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* * The Timer Control Register has one Undefined/Shouldn't Use Bit * So we should do read/modify/write Operation */ /* * Timer Mode : Free Running * Interrupt : Disabled * Prescale : 8 Stage, Clk/256 * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
static int reset_eth (void) { int pt; na_get_mac_addr (); pt = na_mii_identify_phy (); /* reset the phy */ na_mii_write (MII_PHY_CONTROL, 0x8000); reset_timer_masked (); while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { break; } } if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) printf ("phy reset timeout\n"); /* set the PCS reg */ SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); na_mii_negotiate (); na_mii_check_speed (); /* Delay 10 millisecond. (Maybe this should be 1 second.) */ udelay (10000); /* Turn receive on. Enable statistics register autozero on read. Do not insert MAC address on transmit. Do not enable special test modes. */ SET_EADDR (NETARM_ETH_STL_CFG, (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); /* Set the inter-packet gap delay to 0.96us for MII. The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); /* Add CRC to end of packets. Pad packets to minimum length of 64 bytes. Allow unlimited length transmit packets. Receive all broadcast packets. NOTE: Multicast addressing is NOT enabled here currently. */ SET_EADDR (NETARM_ETH_MAC_CFG, (NETARM_ETH_MACC_CRCEN | NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); /* enable fifos */ SET_EADDR (NETARM_ETH_GEN_CTRL, (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); return (0); }
int interrupt_init(void) { /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); reset_timer_masked(); /* init the timestamp and lastinc value */ return 0; }
static int na_mii_poll_busy (void) { /* arm simple, non interrupt dependent timer */ reset_timer_masked (); while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { return 1; } } printf ("na_mii_busy timeout\n"); return (0); }
/* nothing really to do with interrupts, just starts up a counter. */ int timer_init (void) { /* Start the decrementer ticking down from 0xffffffff */ __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), CONFIG_SYS_TIMERBASE + CNTL_TIMER); /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
void udelay_masked (unsigned long usec) { ulong tmo; tmo = usec / 1000; tmo *= CFG_HZ; tmo /= 1000; reset_timer_masked (); while (get_timer_masked () < tmo) /*NOP*/; }
int interrupt_init (void) { int i; /* setup GP Timer 1 */ TCTL1 = TCTL_SWR; for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ reset_timer_masked(); return (0); }
/* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init (void) { int32_t val; /* Start the counter ticking up */ *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ reset_timer_masked(); /* init the timestamp and lastinc value */ return(0); }
int timer_init (void) { int32_t val; /* Start the decrementer ticking down from 0xffffffff */ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT); *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
int timer_init(void) { unsigned int oscc; unsigned int cr; debug("%s()\n", __func__); /* disable timers */ writel(0, &tmr->cr); /* * use 32768Hz oscillator for RTC, WDT, TIMER */ /* enable the 32768Hz oscillator */ oscc = readl(&pmu->OSCC); oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); writel(oscc, &pmu->OSCC); /* wait until ready */ while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) ; /* select 32768Hz oscillator */ oscc = readl(&pmu->OSCC); oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; writel(oscc, &pmu->OSCC); /* setup timer */ writel(TIMER_LOAD_VAL, &tmr->timer3_load); writel(TIMER_LOAD_VAL, &tmr->timer3_counter); writel(0, &tmr->timer3_match1); writel(0, &tmr->timer3_match2); /* we don't want timer to issue interrupts */ writel(FTTMR010_TM3_MATCH1 | FTTMR010_TM3_MATCH2 | FTTMR010_TM3_OVERFLOW, &tmr->interrupt_mask); cr = readl(&tmr->cr); cr |= FTTMR010_TM3_CLOCK; /* use external clock */ cr |= FTTMR010_TM3_ENABLE; writel(cr, &tmr->cr); /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
/* * Start the timer */ int timer_init(void) { /* * Setup timer0 */ writel(SYSTIMER_RELOAD, &systimer_base->timer0load); writel(SYSTIMER_RELOAD, &systimer_base->timer0value); writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control); reset_timer_masked(); return 0; }
int timer_init(void) { dmw_timer_init(); dmw_timer_alloc(DMW96_TIMERID1 , DMW_TMR_CTRL_DIV16 | DMW_TMR_CTRL_32BIT ); dmw_timer_start(DMW96_TIMERID1,0xffffffff); gd->timer_rate_hz = dmw_get_pclk() / 16; gd->tbu = gd->timer_rate_hz / CONFIG_SYS_HZ; /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
extern void timer_init(void) { u32 ahb_hz; iowrite32(TIMER_LOAD_VAL, TIMERS_TMR0LR); ahb_hz = get_ahb_hz(); apb_hz = APB_HZ(ahb_hz); /* Set timer to be enabled, periodical, no interrupts, 1 divider */ iowrite32(0x0000018a, TIMERS_TMR0CON); /* Init the timestamp and lastdec value */ reset_timer_masked(); }
/* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); /* Enable PITC */ at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); reset_timer_masked(); return 0; }
int timer_init(void) { #if (CONFIG_RKCHIPTYPE == CONFIG_RKPX2) || (CONFIG_RKCHIPTYPE == CONFIG_RK3168) /* set count value */ g_rk30Time0Reg->TIMER_LOAD_COUNT = TIMER_LOAD_VAL; /* auto reload & enable the timer */ g_rk30Time0Reg->TIMER_CTRL_REG = 0x01; #elif (CONFIG_RKCHIPTYPE == CONFIG_RK3188 ||CONFIG_RKCHIPTYPE == CONFIG_RK3026) g_rk3188Time0Reg->TIMER_LOAD_COUNT0 = TIMER_LOAD_VAL; g_rk3188Time0Reg->TIMER_CTRL_REG = 0x01; #endif reset_timer_masked(); return 0; }
/* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { /* Load timer with initial value */ writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16); /* * Set timer to be enabled, free-running, no interrupts, 256 divider, * 32-bit, wrap-mode */ writel(0x8a, CONFIG_SYS_TIMERBASE + 24); /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }
/* delay x useconds AND perserve advance timstamp value */ void udelay (unsigned long usec) { ulong tmo, tmp; tmo = usec/1000; tmp = get_timer (0); /* get current timestamp */ if( (tmo + tmp + 1) < tmp ) /* if setting this forward will roll time stamp */ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ else tmo += tmp; /* else, set advancing stamp wake up time */ while (get_timer_masked () < tmo)/* loop till event */ /*NOP*/; }
int timer_init(void) { /* PWM Timer 4 */ pwm_init(4, MUX_DIV_4, 0); pwm_config(4, 0, 0); pwm_enable(4); /* Use this as the current monotonic time in us */ gd->timer_reset_value = 0; /* Use this as the last timer value we saw */ gd->lastinc = timer_get_us_down(); reset_timer_masked(); return 0; }
/* delay x useconds */ void __udelay(unsigned long usec) { #if 0 struct s5p_timer *const timer = s5p_get_base_timer(); unsigned long tmo, tmp, count_value; count_value = readl(&timer->tcntb4); if (usec >= 1000) { /* * if "big" number, spread normalization * to seconds * 1. start to normalize for usec to ticks per sec * 2. find number of "ticks" to wait to achieve target * 3. finish normalize. */ tmo = usec / 1000; tmo *= (CONFIG_SYS_HZ * count_value / 10); tmo /= 1000; } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ * count_value / 10; tmo /= (1000 * 1000); } /* get current timestamp */ tmp = get_timer_org(0); /* if setting this fordward will roll time stamp */ /* reset "advancing" timestamp to 0, set lastinc value */ /* else, set advancing stamp wake up time */ if ((tmo + tmp + 1) < tmp) reset_timer_masked(); else tmo += tmp; /* loop till event */ while (get_timer_masked() < tmo) ; /* nop */ #else unsigned long count_value; count_value = timer_get_us_down(); while ((int)(count_value - timer_get_us_down()) < (int)usec) ; #endif }
static void rvpb_timer_init(void) { /* * Set clock frequency in system controller: * TIMER Clock is 25MHz */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0; //disable timer *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = CONFIG_SYS_TIMER_RELOAD; /* TimerLoad */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x5; /* Enabled, * free running, * no interrupt, */ reset_timer_masked(); }
void udelay_masked (unsigned long usec) { ulong tmo; #if 0 /* doesn't work for usec < 1000 */ tmo = usec / 1000; tmo *= CFG_HZ_CLOCK; #else tmo = CFG_HZ_CLOCK / 1000; tmo *= usec; #endif tmo /= 1000; reset_timer_masked (); while (get_timer_raw () < tmo) /*NOP*/; }
/* * delay x useconds AND preserve advance timstamp value * GPTCNT is now supposed to tick 1 by 1 us. */ void __udelay(unsigned long usec) { ulong tmp; tmp = get_timer_masked(); /* get current timestamp */ /* if setting this forward will roll time stamp */ if ((usec + tmp + 1) < tmp) { /* reset "advancing" timestamp to 0, set lastinc value */ reset_timer_masked(); } else { /* else, set advancing stamp wake up time */ tmp += usec; } while (get_timer_masked() < tmp) /* loop till event */ /*NOP*/; }
int timer_init(void) { u32 val; /* * Reset Timers and Rotary Encoder module */ /* Clear SFTRST */ REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31)) ; /* Clear CLKGATE */ REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); /* Set SFTRST and wait until CLKGATE is set */ REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31); while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30))) ; /* Clear SFTRST and CLKGATE */ REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); /* * Now initialize timer */ /* Set fixed_count to 0 */ REG_WR(TIMROT_BASE + TIMCOUNT, 0); /* set UPDATE bit and 1Khz frequency */ REG_WR(TIMROT_BASE + TIMCTRL, TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ); /* Set fixed_count to maximal value */ REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL); /* init the timestamp and lastdec value */ reset_timer_masked(); return 0; }