コード例 #1
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::ASR_init()////////////初始化语音识别模式、
{
	  //添加状态标记 
	  readReg(0x06);  
//	  writeReg(0x17, 0x35); 
	  delay(10);
	  readReg(0x06);  
	  writeReg(0x89, 0x03);  
	  delay(5);
	  writeReg(0xcf, 0x43);  
	  delay(5);
	  writeReg(0xcb, 0x02);
	  writeReg(0x11, PLL_11);  
	  writeReg(0x1e,0x00);
	  writeReg(0x19, PLL_ASR_19); 
	  writeReg(0x1b, PLL_ASR_1B);	
	  writeReg(0x1d, PLL_ASR_1D);
	  delay(10);
	  writeReg(0xcd, 0x04);
	  writeReg(0x17, 0x4c); 
	  delay(5);
//	  writeReg(0xb9, 0x00);
	  writeReg(0xcf, 0x4f);  
	  writeReg(0xbd, 0x00);
	  writeReg(0x17, 0x48);
	  delay(10);
	  writeReg(0x3c, 0x80);  
	  writeReg(0x3e, 0x07);
	  writeReg(0x38, 0xff);  
	  writeReg(0x3a, 0x07);
	  writeReg(0x40, 0);   
	  writeReg(0x42, 8);
	  writeReg(0x44, 0); 
	  writeReg(0x46, 8); 
	  delay(1);
}
コード例 #2
0
ファイル: L3G4200D.cpp プロジェクト: Thomas-dot-G/Quadri
// Turns on the L3G4200D's gyro and places it in normal mode.
void L3G4200D::enableDefault(void)
{
	// 0x0F = 0b00001111
	// Normal power mode, all axes enabled
	writeReg(L3G4200D_CTRL_REG1, 0x0F);
}
コード例 #3
0
void Enc28J60Network::init(uint8_t* macaddr)
{
  // initialize I/O
  // ss as output:
  pinMode(ENC28J60_CONTROL_CS, OUTPUT);
  CSPASSIVE; // ss=0
  //
  pinMode(SPI_MOSI, OUTPUT);
  pinMode(SPI_SCK, OUTPUT);
  pinMode(SPI_MISO, INPUT);
  pinMode(SPI_SS, OUTPUT);

  digitalWrite(SPI_MOSI, LOW);
  digitalWrite(SPI_SCK, LOW);

  /*DDRB  |= 1<<PB3 | 1<<PB5; // mosi, sck output
  cbi(DDRB,PINB4); // MISO is input
  //
  cbi(PORTB,PB3); // MOSI low
  cbi(PORTB,PB5); // SCK low
  */
  //
  // initialize SPI interface
  // master mode and Fosc/2 clock:
  SPCR = (1<<SPE)|(1<<MSTR);
  SPSR |= (1<<SPI2X);
  // perform system reset
  writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
  delay(50);
  // check CLKRDY bit to see if reset is complete
  // The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
  //while(!(readReg(ESTAT) & ESTAT_CLKRDY));
  // do bank 0 stuff
  // initialize receive buffer
  // 16-bit transfers, must write low byte first
  // set receive buffer start address
  nextPacketPtr = RXSTART_INIT;
  // Rx start
  writeRegPair(ERXSTL, RXSTART_INIT);
  // set receive pointer address
  writeRegPair(ERXRDPTL, RXSTART_INIT);
  // RX end
  writeRegPair(ERXNDL, RXSTOP_INIT);
  // TX start
  //writeRegPair(ETXSTL, TXSTART_INIT);
  // TX end
  //writeRegPair(ETXNDL, TXSTOP_INIT);
  // do bank 1 stuff, packet filter:
  // For broadcast packets we allow only ARP packtets
  // All other packets should be unicast only for our mac (MAADR)
  //
  // The pattern to match on is therefore
  // Type     ETH.DST
  // ARP      BROADCAST
  // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
  // in binary these poitions are:11 0000 0011 1111
  // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
  //TODO define specific pattern to receive dhcp-broadcast packages instead of setting ERFCON_BCEN!
  writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
  writeRegPair(EPMM0, 0x303f);
  writeRegPair(EPMCSL, 0xf7f9);
  //
  //
  // do bank 2 stuff
  // enable MAC receive
  // and bring MAC out of reset (writes 0x00 to MACON2)
  writeRegPair(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
  // enable automatic padding to 60bytes and CRC operations
  writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
  // set inter-frame gap (non-back-to-back)
  writeRegPair(MAIPGL, 0x0C12);
  // set inter-frame gap (back-to-back)
  writeReg(MABBIPG, 0x12);
  // Set the maximum packet size which the controller will accept
  // Do not send packets longer than MAX_FRAMELEN:
  writeRegPair(MAMXFLL, MAX_FRAMELEN);
  // do bank 3 stuff
  // write MAC address
  // NOTE: MAC address in ENC28J60 is byte-backward
  writeReg(MAADR5, macaddr[0]);
  writeReg(MAADR4, macaddr[1]);
  writeReg(MAADR3, macaddr[2]);
  writeReg(MAADR2, macaddr[3]);
  writeReg(MAADR1, macaddr[4]);
  writeReg(MAADR0, macaddr[5]);
  // no loopback of transmitted frames
  phyWrite(PHCON2, PHCON2_HDLDIS);
  // switch to bank 0
  setBank(ECON1);
  // enable interrutps
  writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
  // enable packet reception
  writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
  //Configure leds
  phyWrite(PHLCON,0x476);
}
コード例 #4
0
ファイル: dump.c プロジェクト: pablosistemas/temp
void *dumpCounts()
{
    unsigned val;

    readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
    printf("Num pkts received on port 0:           %u\n", val);
    readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
    printf("Num pkts dropped (rx queue 0 full):    %u\n", val);
    readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
    printf("Num pkts dropped (bad fcs q 0):        %u\n", val);
    readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes received on port 0:          %u\n", val);
    readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
    printf("Num pkts sent from port 0:             %u\n", val);
    readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes sent from port 0:            %u\n\n", val);

    readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
    printf("Num pkts received on port 1:           %u\n", val);
    readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
    printf("Num pkts dropped (rx queue 1 full):    %u\n", val);
    readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
    printf("Num pkts dropped (bad fcs q 1):        %u\n", val);
    readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes received on port 1:          %u\n", val);
    readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
    printf("Num pkts sent from port 1:             %u\n", val);
    readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes sent from port 1:            %u\n\n", val);

    readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
    printf("Num pkts received on port 2:           %u\n", val);
    readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
    printf("Num pkts dropped (rx queue 2 full):    %u\n", val);
    readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
    printf("Num pkts dropped (bad fcs q 2):        %u\n", val);
    readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes received on port 2:          %u\n", val);
    readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
    printf("Num pkts sent from port 2:             %u\n", val);
    readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes sent from port 2:            %u\n\n", val);

    readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
    printf("Num pkts received on port 3:           %u\n", val);
    readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
    printf("Num pkts dropped (rx queue 3 full):    %u\n", val);
    readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
    printf("Num pkts dropped (bad fcs q 3):        %u\n", val);
    readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes received on port 3:          %u\n", val);
    readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
    printf("Num pkts sent from port 3:             %u\n", val);
    readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
    printf("Num bytes sent from port 3:            %u\n\n", val);

    /* udp header */
    uint32_t *ip = &servidor.sin_addr.s_addr;
    writeReg(&nf2,MAKER_DST_MAC_HI_REG,0x00<<24|0x00<<16|0xC8<<8|0x2A);
    writeReg(&nf2,MAKER_DST_MAC_LO_REG,0x14<<24|0x39<<16|0x71<<8|0xCD);

    writeReg(&nf2,MAKER_SRC_MAC_HI_REG,0x00<<24|0x00<<16|0xD0<<8|0x27);
    writeReg(&nf2,MAKER_SRC_MAC_LO_REG,0x88<<24|0xBC<<16|0xA8<<8|0xB9);

    writeReg(&nf2,MAKER_ETHERTYPE_REG,0x800);

    writeReg(&nf2,MAKER_IP_DST_REG,*ip);
    writeReg(&nf2,MAKER_IP_SRC_REG,127<<24|0<<16|0<<8|2);

    writeReg(&nf2,MAKER_UDP_SRC_PORT_REG,porta);
    writeReg(&nf2,MAKER_UDP_DST_PORT_REG,porta);

    writeReg(&nf2,MAKER_OUTPUT_PORT_REG,0x4);

    /* enable packets */
    writeReg(&nf2,MAKER_ENABLE_REG,1);

    pthread_exit(NULL);
}
コード例 #5
0
ファイル: RFM69.cpp プロジェクト: skatun/Openhab
bool RFM69::initialize(byte freqBand, byte nodeID, byte networkID)
{
  unsigned long start_to;
  const byte CONFIG[][2] =
  {
    /* 0x01 */ { REG_OPMODE, RF_OPMODE_SEQUENCER_ON | RF_OPMODE_LISTEN_OFF | RF_OPMODE_STANDBY },
    /* 0x02 */ { REG_DATAMODUL, RF_DATAMODUL_DATAMODE_PACKET | RF_DATAMODUL_MODULATIONTYPE_FSK | RF_DATAMODUL_MODULATIONSHAPING_00 }, //no shaping
    /* 0x03 */ { REG_BITRATEMSB, RF_BITRATEMSB_55555}, //default:4.8 KBPS
    /* 0x04 */ { REG_BITRATELSB, RF_BITRATELSB_55555},
    /* 0x05 */ { REG_FDEVMSB, RF_FDEVMSB_50000}, //default:5khz, (FDEV + BitRate/2 <= 500Khz)
    /* 0x06 */ { REG_FDEVLSB, RF_FDEVLSB_50000},

    /* 0x07 */ { REG_FRFMSB, (freqBand==RF69_315MHZ ? (const byte)RF_FRFMSB_315 : (freqBand==RF69_433MHZ ? (const byte)RF_FRFMSB_433 : (freqBand==RF69_868MHZ ? (const byte)RF_FRFMSB_868 : (const byte)RF_FRFMSB_915))) },
    /* 0x08 */ { REG_FRFMID, (freqBand==RF69_315MHZ ? (const byte)RF_FRFMID_315 : (freqBand==RF69_433MHZ ? (const byte)RF_FRFMID_433 : (freqBand==RF69_868MHZ ? (const byte)RF_FRFMID_868 : (const byte)RF_FRFMID_915))) },
    /* 0x09 */ { REG_FRFLSB, (freqBand==RF69_315MHZ ? (const byte)RF_FRFLSB_315 : (freqBand==RF69_433MHZ ? (const byte)RF_FRFLSB_433 : (freqBand==RF69_868MHZ ? (const byte)RF_FRFLSB_868 : (const byte)RF_FRFLSB_915))) },
    
    // looks like PA1 and PA2 are not implemented on RFM69W, hence the max output power is 13dBm
    // +17dBm and +20dBm are possible on RFM69HW
    // +13dBm formula: Pout=-18+OutputPower (with PA0 or PA1**)
    // +17dBm formula: Pout=-14+OutputPower (with PA1 and PA2)**
    // +20dBm formula: Pout=-11+OutputPower (with PA1 and PA2)** and high power PA settings (section 3.3.7 in datasheet)
    ///* 0x11 */ { REG_PALEVEL, RF_PALEVEL_PA0_ON | RF_PALEVEL_PA1_OFF | RF_PALEVEL_PA2_OFF | RF_PALEVEL_OUTPUTPOWER_11111},
    ///* 0x13 */ { REG_OCP, RF_OCP_ON | RF_OCP_TRIM_95 }, //over current protection (default is 95mA)
    
    // RXBW defaults are { REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_24 | RF_RXBW_EXP_5} (RxBw: 10.4khz)
    /* 0x19 */ { REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_16 | RF_RXBW_EXP_2 }, //(BitRate < 2 * RxBw)
    //for BR-19200: //* 0x19 */ { REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_24 | RF_RXBW_EXP_3 },
    /* 0x25 */ { REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_01 }, //DIO0 is the only IRQ we're using
    /* 0x29 */ { REG_RSSITHRESH, 220 }, //must be set to dBm = (-Sensitivity / 2) - default is 0xE4=228 so -114dBm
    ///* 0x2d */ { REG_PREAMBLELSB, RF_PREAMBLESIZE_LSB_VALUE } // default 3 preamble bytes 0xAAAAAA
    /* 0x2e */ { REG_SYNCCONFIG, RF_SYNC_ON | RF_SYNC_FIFOFILL_AUTO | RF_SYNC_SIZE_2 | RF_SYNC_TOL_0 },
    /* 0x2f */ { REG_SYNCVALUE1, 0x2D },      //attempt to make this compatible with sync1 byte of RFM12B lib
    /* 0x30 */ { REG_SYNCVALUE2, networkID }, //NETWORK ID
    /* 0x37 */ { REG_PACKETCONFIG1, RF_PACKET1_FORMAT_VARIABLE | RF_PACKET1_DCFREE_OFF | RF_PACKET1_CRC_ON | RF_PACKET1_CRCAUTOCLEAR_ON | RF_PACKET1_ADRSFILTERING_OFF },
    /* 0x38 */ { REG_PAYLOADLENGTH, 66 }, //in variable length mode: the max frame size, not used in TX
    //* 0x39 */ { REG_NODEADRS, nodeID }, //turned off because we're not using address filtering
    /* 0x3C */ { REG_FIFOTHRESH, RF_FIFOTHRESH_TXSTART_FIFONOTEMPTY | RF_FIFOTHRESH_VALUE }, //TX on FIFO not empty
    /* 0x3d */ { REG_PACKETCONFIG2, RF_PACKET2_RXRESTARTDELAY_2BITS | RF_PACKET2_AUTORXRESTART_ON | RF_PACKET2_AES_OFF }, //RXRESTARTDELAY must match transmitter PA ramp-down time (bitrate dependent)
    //for BR-19200: //* 0x3d */ { REG_PACKETCONFIG2, RF_PACKET2_RXRESTARTDELAY_NONE | RF_PACKET2_AUTORXRESTART_ON | RF_PACKET2_AES_OFF }, //RXRESTARTDELAY must match transmitter PA ramp-down time (bitrate dependent)
    //* 0x6F */ { REG_TESTDAGC, RF_DAGC_CONTINUOUS }, // run DAGC continuously in RX mode
    /* 0x6F */ { REG_TESTDAGC, RF_DAGC_IMPROVED_LOWBETA0 }, // run DAGC continuously in RX mode, recommended default for AfcLowBetaOn=0
    {255, 0}
  };

  pinMode(_slaveSelectPin, OUTPUT);
  SPI.begin();
  

  start_to = millis();
  do {
	  writeReg(REG_SYNCVALUE1, 0xaa);
	  yield();
  } while (readReg(REG_SYNCVALUE1) != 0xaa && millis()-start_to < TIME_OUT);

  if (millis()-start_to >= TIME_OUT) return (false);

  start_to = millis()  ;
  do {
	  writeReg(REG_SYNCVALUE1, 0x55);
	  yield();
  } while (readReg(REG_SYNCVALUE1) != 0x55 && millis()-start_to < TIME_OUT);

  if (millis()-start_to >= TIME_OUT) return (false);

  for (byte i = 0; CONFIG[i][0] != 255; i++)
    writeReg(CONFIG[i][0], CONFIG[i][1]);

  // Encryption is persistent between resets and can trip you up during debugging.
  // Disable it during initialization so we always start from a known state.
  encrypt(0);

  setHighPower(_isRFM69HW); //called regardless if it's a RFM69W or RFM69HW
  setMode(RF69_MODE_STANDBY);


  start_to = millis() ;
  while (((readReg(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00) && millis()-start_to < TIME_OUT) {
	  yield();
  } // Wait for ModeReady
  if (millis()-start_to >= TIME_OUT) return (false);

  attachInterrupt(_interruptNum, RFM69::isr0, RISING);

  selfPointer = this;
  _address = nodeID;
  return true;
}
コード例 #6
0
ファイル: Ez80.cpp プロジェクト: laulandne/src
// TODO: Doesn't handle signed offsets!
void Ez80::exec_ld(ULONG loc,unsigned int op)
{
  switch(op) {
    case 0x06: case 0x0e: case 0x16:
    case 0x1e: case 0x26: case 0x2e: case 0x3e:
      // ld r,const8
      val=map->read8(loc+1);
      reg=(op>>3)&0x7;
      writeReg(reg,val,Ez80_SIZE_BYTE);
      break;
    case 0x01: case 0x11: case 0x21: case 0x31:
      // ld rr,const16
      val=map->read16l(loc+1);
      reg=(op>>4)&0x3;
      writeReg(reg,val,Ez80_SIZE_WORD);
      break;
    case 0x7e: case 0x46: case 0x4e: case 0x56:
    case 0x5e: case 0x66: case 0x6e:
      // ld r,(hl)
      reg=(op>>3)&0x7;
      ea=readReg(Ez80_REG_HL,Ez80_SIZE_WORD);
      val=map->read8(ea);
      writeReg(reg,val,Ez80_SIZE_BYTE);
      break;
    case 0x7f: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d:
    case 0x4f: case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d:
    case 0x5f: case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d:
    case 0x6f: case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d:
    case 0x47: case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
    case 0x57: case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55:
    case 0x67: case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65:
      // ld r,r
      reg=(op>>3)&0x7;
      ea=op&0x7; // actually not an ea, but a 2nd register
      val=readReg(ea,Ez80_SIZE_BYTE);
      writeReg(reg,val,Ez80_SIZE_BYTE);
      break;
    case 0x02:
      // ld (bc),a
      ea=readReg(Ez80_REG_BC,Ez80_SIZE_WORD);
      map->write8(ea,a);
      break;
    case 0x12:
      // ld (de),a
      ea=readReg(Ez80_REG_DE,Ez80_SIZE_WORD);
      map->write8(ea,a);
      break;
    case 0x36:
      // ld (hl),const8
      ea=readReg(Ez80_REG_HL,Ez80_SIZE_WORD);
      val=map->read8(loc+1);
      map->write8(ea,val);
      break;
    case 0x77: case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75:
      // ld (hl),r
      reg=op&0x7;
      val=readReg(reg,Ez80_SIZE_BYTE);
      ea=readReg(Ez80_REG_HL,Ez80_SIZE_WORD);
      map->write8(ea,val);
      break;
    case 0xdd:
      // ld r,(ix+const8)
      // ld (ix+const8),const8
      // ld (ix+const8),r
      // ld (const16),ix
      // ld ix,const16
      // ld ix,(const16)
      // ld sp,ix
      // ldd
      debugger("Unimplemented ld opcode!");
      break;
    case 0xfd:
      // ld r,(iy+const8)
      // ld (iy+const8),const8
      // ld (iy+const8),r
      // ld (const16),iy
      // ld iy,const16
      // ld iy,(const16)
      // ld sp,iy
      debugger("Unimplemented ld opcode!");
      break;
    case 0xed:
      // ld (const16),rr
      // ld a,I
      // ld I,a
      // ld a,R
      // ld R,a
      // lddr
      // ldi
      // ldir
      debugger("Unimplemented ld opcode!");
      break;
    case 0x3a:
      // ld a,(const16)
      ea=map->read16l(loc+1);
      val=map->read8(ea);
      a=val;
      break;
    case 0x0a:
      // ld a,(bc)
      ea=readReg(Ez80_REG_BC,Ez80_SIZE_WORD);
      val=map->read8(ea);
      a=val;
      break;
    case 0x32:
      // ld (const16),a
      ea=map->read16l(loc+1);
      map->write8(ea,a);
      break;
    case 0x22:
      // ld (const16),hl
      ea=map->read16l(loc+1);
      val=readReg(Ez80_REG_HL,Ez80_SIZE_WORD);
      map->write8(ea,val);
      break;
    case 0x1a:
      // ld a,(de)
      ea=readReg(Ez80_REG_DE,Ez80_SIZE_WORD);
      val=map->read8(ea);
      a=val;
      break;
    case 0x2a:
      // ld hl,(const16)
      ea=map->read16l(loc+1);
      val=map->read16l(ea);
      writeReg(Ez80_REG_HL,val,Ez80_SIZE_WORD);
      break;
    case 0xf9:
      // ld sp,hl
      val=readReg(Ez80_REG_HL,Ez80_SIZE_WORD);
      sp=val;
      break;
    default:
      debugger("Unimplemented ld opcode!");
      break;
  }
#ifdef DEBUG_EXEC
  DEBUG_OUT<<"ld op="<<op<<" reg="<<reg<<" ea="<<ea<<" val="<<val<<"\n";
#endif
}
コード例 #7
0
//set the 10-bit acceleration offset in a given direction
void MMA7455::setOffset(uint8_t d, uint16_t offset)
{
	writeReg(d + XOFFL, offset & 0xFF);
	writeReg(d + XOFFH, offset >> 8);
}
コード例 #8
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::voiceMaxLength(uint8_t voice_max_length_)//最长语音段时间,参数(0x00~0xC3,单位100MS);
{
	voice_max_length=voice_max_length_;
	writeReg(0xb6, voice_max_length);//语音
}
コード例 #9
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::noiseTime(uint8_t noise_time_)//上电噪声略过,参数(0x00~0xff,单位20MS);
{
	noise_time=noise_time_;
	writeReg(0xb7, noise_time);//噪声时间
}
コード例 #10
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::speechStartTime(uint8_t speech_start_time_)//调整语音端点起始时间,参数(0x00~0x30,单位10MS);
{
	speech_start_time=speech_start_time_;
	writeReg(0xb4, speech_start_time);//语音端点起始时间
}
コード例 #11
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::speechEndTime(uint8_t speech_end_time_)//调整语音端点结束时间(吐字间隔时间),参数(0x00~0xC3,单位10MS);
{
	speech_end_time=speech_end_time_;
	writeReg(0xb5, speech_end_time);//语音结束时间
}
コード例 #12
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::speechEndpoint(uint8_t speech_endpoint_)//调整语音端点检测,参数(0x00~0xFF,建议10-40);
{
	speech_endpoint=speech_endpoint_;
	writeReg(0xb3, speech_endpoint);//语音端点检测控制
}
コード例 #13
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void VoiceRecognition::micVol(uint8_t vol)//调整ADC增益,参数(0x00~0xFF,建议10-60);
{
	MIC_VOL=vol;
	writeReg(0x35, MIC_VOL);////adc增益;会影响识别范围即噪声
}
コード例 #14
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
unsigned char VoiceRecognition::start()//////开始识别
{
	writeReg(0x35, MIC_VOL);////adc增益;会影响识别范围即噪声
	
	writeReg(0xb3, speech_endpoint);//语音端点检测控制

	writeReg(0xb4, speech_start_time);//语音端点起始时间
	
	writeReg(0xb5, speech_end_time);//语音结束时间

	writeReg(0xb6, voice_max_length);//语音结束时间
	
	writeReg(0xb7, noise_time);//噪声时间
	
	writeReg(0x1c, 0x09);////////麦克风设置保留

	writeReg(0xbd, 0x20);/////////保留设置
	writeReg(0x08, 0x01);///////////→清除FIFO_DATA
	delay( 1);
	writeReg(0x08, 0x00);////////////清除指定FIFO后再写入一次00H
	delay( 1);
	if(check_b2() == 0)////////读取0xB2寄存器函数如果DSP没在闲状态则RETURN 0
	{
		return 0;
	}
	writeReg(0xb2, 0xff);////////给0xB2写FF

	writeReg(0x37, 0x06);////////开始识别
	delay( 5 );
	writeReg(0x1c, g_Mic);////////选择麦克风
	writeReg(0x29, 0x10);////////开同步中断
	writeReg(0xbd, 0x00);/////////启动为语音识别

	return 1;////返回1
}
コード例 #15
0
int main(int argc, char *argv[])
{
	int ret = 0;
	int fd;
	int sysfs_fd;

	int no_tty = !isatty( fileno(stdout) );

	fd = open(device, O_RDWR);
	if (fd < 0)
		pabort("can't open device");

	/*
	 * spi mode
	 */
	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
	if (ret == -1)
		pabort("can't set spi mode");

	ret = ioctl(fd, SPI_IOC_RD_MODE, &mode);
	if (ret == -1)
		pabort("can't get spi mode");

	/*
	 * bits per word
	 */
	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
	if (ret == -1)
		pabort("can't set bits per word");

	ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
	if (ret == -1)
		pabort("can't get bits per word");

	fprintf(stderr, "spi mode: %d\n", mode);
	fprintf(stderr, "bits per word: %d\n", bits);

	// enable master clock for the AD
	// divisor results in roughly 4.9MHz
	// this also inits the general purpose IO
	gz_clock_ena(GZ_CLK_5MHz,5);

	// enables sysfs entry for the GPIO pin
	gpio_export(drdy_GPIO);
	// set to input
	gpio_set_dir(drdy_GPIO,0);
	// set interrupt detection to falling edge
	gpio_set_edge(drdy_GPIO,"falling");
	// get a file descriptor for the GPIO pin
	sysfs_fd = gpio_fd_open(drdy_GPIO);

	// resets the AD7705 so that it expects a write to the communication register
        printf("sending reset\n");
	writeReset(fd);

	// tell the AD7705 that the next write will be to the clock register
	writeReg(fd,0x20);
	// write 00001100 : CLOCKDIV=1,CLK=1,expects 4.9152MHz input clock
	writeReg(fd,0x0C);

	// tell the AD7705 that the next write will be the setup register
	writeReg(fd,0x10);
	// intiates a self calibration and then after that starts converting
	writeReg(fd,0x40);

	// we read data in an endless loop and display it
	// this needs to run in a thread ideally
	int comReg, clkReg, setReg;
	// tell the AD7705 to read the communication register (8 bits)
	writeReg(fd,0x08);
	// read the data register by performing two 8 bit reads
	comReg = (int) readReg(fd);
	printf("communication register: %d/n",comReg);
	// tell the AD7705 to read the clock register (8 bits)
	writeReg(fd,0x28);
	// read the data register by performing two 8 bit reads
	clkReg = (int) readReg(fd);
	printf("clock register: %d/n",comReg);
	// tell the AD7705 to read the setup register (8 bits)
	writeReg(fd,0x18);
	// read the data register by performing two 8 bit reads
	setReg = (int) readReg(fd);
	printf("se-tup register: %d/n",comReg);
	// tell the AD7705 to read the clock register (8 bits)
	
	
	
	  


	close(fd);
	gpio_fd_close(sysfs_fd);

	return ret;
}
コード例 #16
0
ファイル: ld3320.cpp プロジェクト: xbed/Mixly_Company_Extend
void update()//中断服务函数
{ 
	uint8_t Asr_Count=0;
	if((readReg(0x2b) & 0x10) && readReg(0xb2)==0x21 && readReg(0xbf)==0x35)//如果有语音识别中断、DSP闲、ASR正常结束
	{
		writeReg(0x29,0) ;///////////关中断
		writeReg(0x02,0) ;/////////////关FIFO中断
		Asr_Count = readReg(0xba);//读中断辅助信息
		if(Asr_Count>0 && Asr_Count<4) //////如果有识别结果
		{
			readnum=readReg(0xc5);
			readflag=1;
		}	
		writeReg(0x2b,0);//////清楚中断编号
		writeReg(0x1C,0);////////貌似关麦克风
	}
	readReg(0x06);  
	delay(10);
	readReg(0x06);  
	writeReg(0x89, 0x03);  
	delay(5);
	writeReg(0xcf, 0x43);  
	delay(5);
	writeReg(0xcb, 0x02);
	writeReg(0x11, PLL_11);  
	writeReg(0x1e,0x00);
	writeReg(0x19, PLL_ASR_19); 
	writeReg(0x1b, PLL_ASR_1B);	
	writeReg(0x1d, PLL_ASR_1D);
	delay(10);
	writeReg(0xcd, 0x04);
	writeReg(0x17, 0x4c); 
	delay(5);
	writeReg(0xcf, 0x4f);  
	writeReg(0xbd, 0x00);
	writeReg(0x17, 0x48);
	delay(10);
	writeReg(0x3c, 0x80);  
	writeReg(0x3e, 0x07);
	writeReg(0x38, 0xff);  
	writeReg(0x3a, 0x07);
	writeReg(0x40, 0);   
	writeReg(0x42, 8);
	writeReg(0x44, 0); 
	writeReg(0x46, 8); 
	delay(1);	
	writeReg(0x1c, 0x09);////////麦克风设置保留
	writeReg(0xbd, 0x20);/////////保留设置
	writeReg(0x08, 0x01);///////////→清除FIFO_DATA
	delay( 1);
	writeReg(0x08, 0x00);////////////清除指定FIFO后再写入一次00H
	delay( 1);
	writeReg(0xb2, 0xff);////////给0xB2写FF
	writeReg(0x37, 0x06);////////开始识别
	delay( 5 );
	writeReg(0x1c, g_Mic);////////选择麦克风
	writeReg(0x29, 0x10);////////开同步中断
	writeReg(0xbd, 0x00);/////////启动为语音识别
}	
コード例 #17
0
void Si7020::resetSettings()
{
	//Reset user resister
	writeReg(RESET_SI);
}
コード例 #18
0
void toggleLedForever()
{   
    volatile int num = 0;
    
    writeReg(IODIRA, 0x00);
   // writeReg(GPPUA, 0xff);
        
    writeReg(IODIRB, 0x00);
    //writeReg(GPPUB, 0xff);
    
    DRV_ADC_Open();
    DRV_ADC_ChannelScanInputsAdd(DRV_ADC_INPUT_POSITIVE_AN11);
    DRV_ADC_Start();
    
    /* Open the Device Layer */
    
    LATF = 0;
    volatile int i = 0;
    while(1)
    {

        if(num%256 ==0)
            LATFINV = 0x00000002;
    
        for(i = 0; i < 0x3fff; i++);
        
        num++;
        
        static int adcVal = 0x1234;
        
        if((num%256 == 0))
        {   
            adcVal++;
            if(DRV_ADC_SamplesAvailable())
            {
                adcVal = DRV_ADC_SamplesRead(0);
                DRV_ADC_Start();
            }
        }
        
        writeReg(GPIOA, 0x0F);
        
        char adcHexDigit = (adcVal >> (4*(num%4))) & 0xf;
        
        int voltage = (adcVal*3300) / 1024;
        
        int temp = (voltage - 500) / 10;
        
        int digit = 16;
        
        int nDigit = (num%4);
        
        if (nDigit == 1)
            digit = abs(temp) / 10;
        else if(nDigit == 0)
            digit = abs(temp) % 10;
        else if(nDigit == 2 && temp < 0)
            digit = 18;
        
        writeReg(GPIOB, ~(numberPattern[digit]));  
        
        writeReg(GPIOA, 0x0F & (~(1 << (num%4))));
      
    }
}
コード例 #19
0
ファイル: show_stats.c プロジェクト: 1573472562/netfpga
void show_stats(void) {
   unsigned val;
   unsigned lo_addr[8], hi_addr[8];
   unsigned i;

   while (1) {

      move(5,0);

      readReg(&nf2, MAC_GRP_0_CONTROL_REG, &val);
      printw("MAC 0 Control: 0x%08x ", val);
      if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
         printw("TX disabled, ");
      }
      else {
         printw("TX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
         printw("RX disabled, ");
      }
      else {
         printw("RX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
         printw("reset on,    ");
      }
      else {
         printw("reset off,   ");
      }
      printw("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);

      readReg(&nf2, MAC_GRP_1_CONTROL_REG, &val);
      printw("MAC 1 Control: 0x%08x ", val);
      if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
         printw("TX disabled, ");
      }
      else {
         printw("TX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
         printw("RX disabled, ");
      }
      else {
         printw("RX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
         printw("reset on,    ");
      }
      else {
         printw("reset off,   ");
      }
      printw("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);

      readReg(&nf2, MAC_GRP_2_CONTROL_REG, &val);
      printw("MAC 2 Control: 0x%08x ", val);
      if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
         printw("TX disabled, ");
      }
      else {
         printw("TX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
         printw("RX disabled, ");
      }
      else {
         printw("RX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
         printw("reset on,    ");
      }
      else {
         printw("reset off,   ");
      }
      printw("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);

      readReg(&nf2, MAC_GRP_3_CONTROL_REG, &val);
      printw("MAC 3 Control: 0x%08x ", val);
      if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
         printw("TX disabled, ");
      }
      else {
         printw("TX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
         printw("RX disabled, ");
      }
      else {
         printw("RX enabled,  ");
      }
      if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
         printw("reset on,    ");
      }
      else {
         printw("reset off,   ");
      }
      printw("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);

      move (12,0);
      printw("                   Port 0    CPU 0   Port 1    CPU 1   Port 2    CPU 2   Port 3    CPU 3\n");
      printw("Packets Lost:\n");
      printw("Packets Stored:\n");
      printw("Packets Removed:\n");
      printw("Bytes Stored:\n");
      printw("Bytes Removed:\n");
      printw("Low address:\n");
      printw("High address:\n");
      printw("Write address:\n");
      printw("Read address:\n");

      move (13,17);
      readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_DROPPED_REG, &val); lost[0] = val;
      printw("%8i", lost[0]);
      readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_DROPPED_REG, &val);lost[1] = val;
      printw(" %8i", lost[1]);
      readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_DROPPED_REG, &val);lost[2] = val;
      printw(" %8i", lost[2]);
      readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_DROPPED_REG, &val);lost[3] = val;
      printw(" %8i", lost[3]);
      readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_DROPPED_REG, &val);lost[4] = val;
      printw(" %8i", lost[4]);
      readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_DROPPED_REG, &val);lost[5] = val;
      printw(" %8i", lost[5]);
      readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_DROPPED_REG, &val);lost[6] = val;
      printw(" %8i", lost[6]);
      readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_DROPPED_REG, &val);lost[7] = val;
      printw(" %8i", lost[7]);

      move (14,17);
      readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_STORED_REG, &val);stored[0] = val;
      printw("%8i", stored[0]);
      readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_STORED_REG, &val);stored[1] = val;
      printw(" %8i", stored[1]);
      readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_STORED_REG, &val);stored[2] = val;
      printw(" %8i", stored[2]);
      readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_STORED_REG, &val);stored[3] = val;
      printw(" %8i", stored[3]);
      readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_STORED_REG, &val);stored[4] = val;
      printw(" %8i", stored[4]);
      readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_STORED_REG, &val);stored[5] = val;
      printw(" %8i", stored[5]);
      readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_STORED_REG, &val);stored[6] = val;
      printw(" %8i", stored[6]);
      readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_STORED_REG, &val);stored[7] = val;
      printw(" %8i", stored[7]);

      move (15,17);
      readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_REMOVED_REG, &val);removed[0] = val;
      printw("%8i", removed[0]);
      readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_REMOVED_REG, &val);removed[1] = val;
      printw(" %8i", removed[1]);
      readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_REMOVED_REG, &val);removed[2] = val;
      printw(" %8i", removed[2]);
      readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_REMOVED_REG, &val);removed[3] = val;
      printw(" %8i", removed[3]);
      readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_REMOVED_REG, &val);removed[4] = val;
      printw(" %8i", removed[4]);
      readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_REMOVED_REG, &val);removed[5] = val;
      printw(" %8i", removed[5]);
      readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_REMOVED_REG, &val);removed[6] = val;
      printw(" %8i", removed[6]);
      readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_REMOVED_REG, &val);removed[7] = val;
      printw(" %8i", removed[7]);

      move (16,17);
      readReg(&nf2, OQ_QUEUE_0_NUM_PKT_BYTES_STORED_REG, &val);
      printw("%8i", val);
      readReg(&nf2, OQ_QUEUE_1_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_2_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_3_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_4_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_5_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_6_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_7_NUM_PKT_BYTES_STORED_REG, &val);
      printw(" %8i", val);

      move (17,17);
      readReg(&nf2, OQ_QUEUE_0_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw("%8i", val);
      readReg(&nf2, OQ_QUEUE_1_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_2_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_3_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_4_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_5_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_6_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);
      readReg(&nf2, OQ_QUEUE_7_NUM_PKT_BYTES_REMOVED_REG, &val);
      printw(" %8i", val);

      move (18,17);
      readReg(&nf2, OQ_QUEUE_0_ADDR_LO_REG, &val);lo_addr[0] = val;
      printw("%8x", lo_addr[0]<<3);
      readReg(&nf2, OQ_QUEUE_1_ADDR_LO_REG, &val);lo_addr[1] = val;
      printw(" %8x", lo_addr[1]<<3);
      readReg(&nf2, OQ_QUEUE_2_ADDR_LO_REG, &val);lo_addr[2] = val;
      printw(" %8x", lo_addr[2]<<3);
      readReg(&nf2, OQ_QUEUE_3_ADDR_LO_REG, &val);lo_addr[3] = val;
      printw(" %8x", lo_addr[3]<<3);
      readReg(&nf2, OQ_QUEUE_4_ADDR_LO_REG, &val);lo_addr[4] = val;
      printw(" %8x", lo_addr[4]<<3);
      readReg(&nf2, OQ_QUEUE_5_ADDR_LO_REG, &val);lo_addr[5] = val;
      printw(" %8x", lo_addr[5]<<3);
      readReg(&nf2, OQ_QUEUE_6_ADDR_LO_REG, &val);lo_addr[6] = val;
      printw(" %8x", lo_addr[6]<<3);
      readReg(&nf2, OQ_QUEUE_7_ADDR_LO_REG, &val);lo_addr[7] = val;
      printw(" %8x", lo_addr[7]<<3);

      move (19,17);
      readReg(&nf2, OQ_QUEUE_0_ADDR_HI_REG, &val);hi_addr[0] = val;
      printw("%8x", hi_addr[0]<<3);
      readReg(&nf2, OQ_QUEUE_1_ADDR_HI_REG, &val);hi_addr[1] = val;
      printw(" %8x", hi_addr[1]<<3);
      readReg(&nf2, OQ_QUEUE_2_ADDR_HI_REG, &val);hi_addr[2] = val;
      printw(" %8x", hi_addr[2]<<3);
      readReg(&nf2, OQ_QUEUE_3_ADDR_HI_REG, &val);hi_addr[3] = val;
      printw(" %8x", hi_addr[3]<<3);
      readReg(&nf2, OQ_QUEUE_4_ADDR_HI_REG, &val);hi_addr[4] = val;
      printw(" %8x", hi_addr[4]<<3);
      readReg(&nf2, OQ_QUEUE_5_ADDR_HI_REG, &val);hi_addr[5] = val;
      printw(" %8x", hi_addr[5]<<3);
      readReg(&nf2, OQ_QUEUE_6_ADDR_HI_REG, &val);hi_addr[6] = val;
      printw(" %8x", hi_addr[6]<<3);
      readReg(&nf2, OQ_QUEUE_7_ADDR_HI_REG, &val);hi_addr[7] = val;
      printw(" %8x", hi_addr[7]<<3);

      move (20,17);
      readReg(&nf2, OQ_QUEUE_0_WR_ADDR_REG, &val);
      printw("%8x", val<<3);
      readReg(&nf2, OQ_QUEUE_1_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_2_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_3_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_4_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_5_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_6_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_7_WR_ADDR_REG, &val);
      printw(" %8x", val<<3);

      move (21,17);
      readReg(&nf2, OQ_QUEUE_0_RD_ADDR_REG, &val);
      printw("%8x", val<<3);
      readReg(&nf2, OQ_QUEUE_1_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_2_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_3_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_4_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_5_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_6_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);
      readReg(&nf2, OQ_QUEUE_7_RD_ADDR_REG, &val);
      printw(" %8x", val<<3);

      move (22,0);
      printw("Size:");
      move (22,16);
      for (i=0;i<8;i++) {
	 printw(" %6iKB", ((hi_addr[i]-lo_addr[i])/128));
      }

	move (24,0);
	readReg(&nf2, SWITCH_OP_LUT_NUM_HITS_REG, &val);
	printw("MAC lut num hits:              %u\n", val);
	readReg(&nf2, SWITCH_OP_LUT_NUM_MISSES_REG, &val);
	printw("MAC lut num misses:            %u\n\n", val);
	for(i=0; i<16; i=i+1){
	  writeReg(&nf2, SWITCH_OP_LUT_MAC_LUT_RD_ADDR_REG, i);
	  readReg(&nf2, SWITCH_OP_LUT_PORTS_MAC_HI_REG, &val);
	  printw("   CAM table entry %02u: wr_protect: %u, ports: 0x%04x, mac: 0x%04x", i, val>>31, (val&0x7fff0000)>>16, (val&0xffff));
	  readReg(&nf2, SWITCH_OP_LUT_MAC_LO_REG, &val);
	  printw("%08x\n", val);
	}


      refresh();

      sleep(1);

   }

}
コード例 #20
0
// Put the FXAS21002C into standby mode.
// It must be in standby for modifying most registers
void FXAS21002C::standby()
{
	byte c = readReg(FXAS21002C_H_CTRL_REG1);
	writeReg(FXAS21002C_H_CTRL_REG1, c & ~(0x03));// Clear bits 0 and 1; standby mode
}
コード例 #21
0
//configure the MODE register of the MMA7455
void MMA7455::setMode(uint8_t mode)
{
	writeReg(MCTL, mode);
}
コード例 #22
0
// Sets the FXAS21000 to active mode.
// Needs to be in this mode to output data
void FXAS21002C::ready()
{
  byte c = readReg(FXAS21002C_H_CTRL_REG1);
  writeReg(FXAS21002C_H_CTRL_REG1, c & ~(0x03));  // Clear bits 0 and 1; standby mode
  writeReg(FXAS21002C_H_CTRL_REG1, c |   0x01);   // Set bit 0 to 1, ready mode; no data acquisition yet
}
コード例 #23
0
/*
  Checks for commandline args, intializes globals, then  begins code download.
*/
int download_very_fast(int frequency) {

   nf2.device_name = DEFAULT_IFACE;
   struct in_addr ip[32], mask[32], gw[32], gw_arp[32], ip_filter[32];
   unsigned int mac_hi[32];
   unsigned int mac_lo[32];
   unsigned int mac0_hi,mac0_lo;
   unsigned int mac1_hi,mac1_lo;
   unsigned int mac2_hi,mac2_lo;
   unsigned int mac3_hi,mac3_lo;

   /*if(argc<2) {
	printf("run <command> <0/1> (0 down; 1 up)\n");
	exit(1);
   }*/
   freq = frequency;
   if(freq!=0 && freq!=1) {
	printf("argument must be either 0 or 1!!!\n");
	exit(1);
   }

   if (check_iface(&nf2))
   {
	   exit(1);
   }
   if (openDescriptor(&nf2))
   {
      exit(1);
   }

   int i;
   char iface;
   unsigned int port[32];
 
   readReg(&nf2,ROUTER_OP_LUT_MAC_0_HI_REG,&mac0_hi);
   readReg(&nf2,ROUTER_OP_LUT_MAC_1_HI_REG,&mac1_hi);
   readReg(&nf2,ROUTER_OP_LUT_MAC_2_HI_REG,&mac2_hi);
   readReg(&nf2,ROUTER_OP_LUT_MAC_3_HI_REG,&mac3_hi);
   readReg(&nf2,ROUTER_OP_LUT_MAC_0_LO_REG,&mac0_lo);
   readReg(&nf2,ROUTER_OP_LUT_MAC_1_LO_REG,&mac1_lo);
   readReg(&nf2,ROUTER_OP_LUT_MAC_2_LO_REG,&mac2_lo);
   readReg(&nf2,ROUTER_OP_LUT_MAC_3_LO_REG,&mac3_lo);

   for(i=0; i<32;i++) {
	bzero(&ip_filter[i], sizeof(struct in_addr));
	writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR_REG, i);
        readReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP_REG, &ip_filter[i].s_addr);

        bzero(&gw_arp[i], sizeof(struct in_addr));
        /* write the row number */
        writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_RD_ADDR_REG, i);

        /* read the four-touple (mac hi, mac lo, gw, num of misses) */
        readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI_REG, &mac_hi[i]);
        readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO_REG, &mac_lo[i]);
        readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP_REG, &gw_arp[i].s_addr);

        bzero(&ip[i], sizeof(struct in_addr));
        bzero(&mask[i], sizeof(struct in_addr));
        bzero(&gw[i], sizeof(struct in_addr));

        /* write the row number */
        writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR_REG, i);

        /* read the four-tuple (ip, gw, mask, iface) from the hw registers */
        readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP_REG, &ip[i].s_addr);
        readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK_REG, &mask[i].s_addr);
        readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP_REG, &gw[i].s_addr);
        readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT_REG, &port[i]);

       }


      ResetDevice();

      writeReg(&nf2,ROUTER_OP_LUT_MAC_0_HI_REG,mac0_hi);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_1_HI_REG,mac1_hi);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_2_HI_REG,mac2_hi);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_3_HI_REG,mac3_hi);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_0_LO_REG,mac0_lo);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_1_LO_REG,mac1_lo);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_2_LO_REG,mac2_lo);
      writeReg(&nf2,ROUTER_OP_LUT_MAC_3_LO_REG,mac3_lo);
      for(i=0; i<32;i++) {
      	    writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP_REG, ip_filter[i].s_addr);
            writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR_REG, i);

	    /* read the four-tuple (ip, gw, mask, iface) from the hw registers */
            writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI_REG, mac_hi[i]);
            writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO_REG, mac_lo[i]);
            writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP_REG, gw_arp[i].s_addr);

            /* write the row number */
            writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_WR_ADDR_REG, i);

            /* read the four-tuple (ip, gw, mask, iface) from the hw registers */
            writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP_REG, ip[i].s_addr);
            writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK_REG, mask[i].s_addr);
            writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP_REG, gw[i].s_addr);
            writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT_REG, port[i]);

            /* write the row number */
            writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR_REG, i);
        
   }

   /* wait until the resets have been completed */
   usleep(1);

   closeDescriptor(&nf2);

   return SUCCESS;
}
コード例 #24
0
// Put the FXAS21002C into active mode.
// Needs to be in this mode to output data.
void FXAS21002C::active()
{
	byte c = readReg(FXAS21002C_H_CTRL_REG1);
	writeReg(FXAS21002C_H_CTRL_REG1, c & ~(0x03));  // Clear bits 0 and 1; standby mode
  	writeReg(FXAS21002C_H_CTRL_REG1, c |   0x02);   // Set bit 1 to 1, active mode; data acquisition enabled
}
コード例 #25
0
ファイル: regdump.c プロジェクト: 1573472562/netfpga
void print(void) {
	unsigned val, val2;
	int i;

	//	readReg(&nf2, UNET_ID, &val);
	//	printf("Board ID: Version %i, Device %i\n", GET_VERSION(val), GET_DEVICE(val));
	readReg(&nf2, MAC_GRP_0_CONTROL_REG, &val);
	printf("MAC 0 Control: 0x%08x ", val);
	if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("TX disabled, ");
	}
	else {
	  printf("TX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("RX disabled, ");
	}
	else {
	  printf("RX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
	  printf("reset on\n");
	}
	else {
	  printf("reset off\n");
	}
	printf("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);

	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
	printf("Num pkts enqueued to rx queue 0:      %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
	printf("Num pkts dropped (rx queue 0 full): %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
	printf("Num pkts dropped (bad fcs q 0):     %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of rx queue 0: %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of rx queue 0: %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_DEQUEUED_REG, &val);
	printf("Num pkts dequeued from rx queue 0: %u\n", val);
	readReg(&nf2, MAC_GRP_0_RX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in rx queue 0: %u\n\n", val);

	readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in tx queue 0:             %u\n", val);
	readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
	printf("Num pkts dequeued from tx queue 0:           %u\n", val);
	readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of tx queue 0: %u\n", val);
	readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of tx queue 0: %u\n", val);
	readReg(&nf2, MAC_GRP_0_TX_QUEUE_NUM_PKTS_ENQUEUED_REG, &val);
	printf("Num pkts enqueued to tx queue 0: %u\n\n", val);

	readReg(&nf2, MAC_GRP_1_CONTROL_REG, &val);
	printf("MAC 1 Control: 0x%08x ", val);
	if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("TX disabled, ");
	}
	else {
	  printf("TX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("RX disabled, ");
	}
	else {
	  printf("RX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
	  printf("reset on\n");
	}
	else {
	  printf("reset off\n");
	}
	printf("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
	printf("Num pkts enqueued to rx queue 1:      %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
	printf("Num pkts dropped (rx queue 1 full): %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
	printf("Num pkts dropped (bad fcs q 1):     %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of rx queue 1: %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of rx queue 1: %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_DEQUEUED_REG, &val);
	printf("Num pkts dequeued from rx queue 1: %u\n", val);
	readReg(&nf2, MAC_GRP_1_RX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in rx queue 1: %u\n\n", val);

	readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in tx queue 1:             %u\n", val);
	readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
	printf("Num pkts dequeued from tx queue 1:           %u\n", val);
	readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of tx queue 1: %u\n", val);
	readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of tx queue 1: %u\n", val);
        readReg(&nf2, MAC_GRP_1_TX_QUEUE_NUM_PKTS_ENQUEUED_REG, &val);
        printf("Num pkts enqueued to tx queue 1: %u\n\n", val);

	readReg(&nf2, MAC_GRP_2_CONTROL_REG, &val);
	printf("MAC 2 Control: 0x%08x ", val);
	if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("TX disabled, ");
	}
	else {
	  printf("TX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("RX disabled, ");
	}
	else {
	  printf("RX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
	  printf("reset on\n");
	}
	else {
	  printf("reset off\n");
	}
	printf("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
	printf("Num pkts enqueued to rx queue 2:      %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
	printf("Num pkts dropped (rx queue 2 full): %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
	printf("Num pkts dropped (bad fcs q 2):     %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of rx queue 2: %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of rx queue 2: %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_DEQUEUED_REG, &val);
	printf("Num pkts dequeued from rx queue 2: %u\n", val);
	readReg(&nf2, MAC_GRP_2_RX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in rx queue 2: %u\n\n", val);

	readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in tx queue 2:             %u\n", val);
	readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
	printf("Num pkts dequeued from tx queue 2:           %u\n", val);
	readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of tx queue 2: %u\n", val);
	readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of tx queue 2: %u\n", val);
        readReg(&nf2, MAC_GRP_2_TX_QUEUE_NUM_PKTS_ENQUEUED_REG, &val);
        printf("Num pkts enqueued to tx queue 2: %u\n\n", val);

	readReg(&nf2, MAC_GRP_3_CONTROL_REG, &val);
	printf("MAC 3 Control: 0x%08x ", val);
	if(val&(1<<MAC_GRP_TX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("TX disabled, ");
	}
	else {
	  printf("TX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RX_QUEUE_DISABLE_BIT_NUM)) {
	  printf("RX disabled, ");
	}
	else {
	  printf("RX enabled,  ");
	}
	if(val&(1<<MAC_GRP_RESET_MAC_BIT_NUM)) {
	  printf("reset on\n");
	}
	else {
	  printf("reset off\n");
	}
        printf("mac config 0x%02x\n", val>>MAC_GRP_MAC_DISABLE_TX_BIT_NUM);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_STORED_REG, &val);
	printf("Num pkts enqueued to rx queue 3:      %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_DROPPED_FULL_REG, &val);
	printf("Num pkts dropped (rx queue 3 full): %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_DROPPED_BAD_REG, &val);
	printf("Num pkts dropped (bad fcs q 3):     %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of rx queue 3: %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of rx queue 3: %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_DEQUEUED_REG, &val);
	printf("Num pkts dequeued from rx queue 3: %u\n", val);
	readReg(&nf2, MAC_GRP_3_RX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in rx queue 3: %u\n\n", val);

	readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_PKTS_IN_QUEUE_REG, &val);
	printf("Num pkts in tx queue 3:             %u\n", val);
	readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_PKTS_SENT_REG, &val);
	printf("Num pkts dequeued from tx queue 3:           %u\n", val);
	readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_WORDS_PUSHED_REG, &val);
	printf("Num words pushed out of tx queue 3: %u\n", val);
	readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_BYTES_PUSHED_REG, &val);
	printf("Num bytes pushed out of tx queue 3: %u\n", val);
        readReg(&nf2, MAC_GRP_3_TX_QUEUE_NUM_PKTS_ENQUEUED_REG, &val);
        printf("Num pkts enqueued to tx queue 3: %u\n\n", val);
/*
	readReg(&nf2, CPU_REG_Q_0_WR_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_0_WR_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_0_WR_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_0_WR_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_0_WR_NUM_WORDS_LEFT_REG, &val);
	printf("CPU_REG_Q_0_WR_NUM_WORDS_LEFT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_WR_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_0_WR_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_RD_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_0_RD_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_0_RD_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_0_RD_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_0_RD_NUM_WORDS_AVAIL_REG, &val);
	printf("CPU_REG_Q_0_RD_NUM_WORDS_AVAIL_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_RD_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_0_RD_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_RX_NUM_PKTS_RCVD_REG, &val);
	printf("CPU_REG_Q_0_RX_NUM_PKTS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_TX_NUM_PKTS_SENT_REG, &val);
	printf("CPU_REG_Q_0_TX_NUM_PKTS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_RX_NUM_WORDS_RCVD_REG, &val);
	printf("CPU_REG_Q_0_RX_NUM_WORDS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_TX_NUM_WORDS_SENT_REG, &val);
	printf("CPU_REG_Q_0_TX_NUM_WORDS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_RX_NUM_BYTES_RCVD_REG, &val);
	printf("CPU_REG_Q_0_RX_NUM_BYTES_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_0_TX_NUM_BYTES_SENT_REG, &val);
	printf("CPU_REG_Q_0_TX_NUM_BYTES_SENT_REG: %u\n\n", val);

	readReg(&nf2, CPU_REG_Q_1_WR_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_1_WR_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_1_WR_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_1_WR_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_1_WR_NUM_WORDS_LEFT_REG, &val);
	printf("CPU_REG_Q_1_WR_NUM_WORDS_LEFT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_WR_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_1_WR_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_RD_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_1_RD_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_1_RD_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_1_RD_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_1_RD_NUM_WORDS_AVAIL_REG, &val);
	printf("CPU_REG_Q_1_RD_NUM_WORDS_AVAIL_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_RD_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_1_RD_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_RX_NUM_PKTS_RCVD_REG, &val);
	printf("CPU_REG_Q_1_RX_NUM_PKTS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_TX_NUM_PKTS_SENT_REG, &val);
	printf("CPU_REG_Q_1_TX_NUM_PKTS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_RX_NUM_WORDS_RCVD_REG, &val);
	printf("CPU_REG_Q_1_RX_NUM_WORDS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_TX_NUM_WORDS_SENT_REG, &val);
	printf("CPU_REG_Q_1_TX_NUM_WORDS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_RX_NUM_BYTES_RCVD_REG, &val);
	printf("CPU_REG_Q_1_RX_NUM_BYTES_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_1_TX_NUM_BYTES_SENT_REG, &val);
	printf("CPU_REG_Q_1_TX_NUM_BYTES_SENT_REG: %u\n\n", val);

	readReg(&nf2, CPU_REG_Q_2_WR_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_2_WR_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_2_WR_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_2_WR_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_2_WR_NUM_WORDS_LEFT_REG, &val);
	printf("CPU_REG_Q_2_WR_NUM_WORDS_LEFT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_WR_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_2_WR_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_RD_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_2_RD_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_2_RD_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_2_RD_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_2_RD_NUM_WORDS_AVAIL_REG, &val);
	printf("CPU_REG_Q_2_RD_NUM_WORDS_AVAIL_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_RD_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_2_RD_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_RX_NUM_PKTS_RCVD_REG, &val);
	printf("CPU_REG_Q_2_RX_NUM_PKTS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_TX_NUM_PKTS_SENT_REG, &val);
	printf("CPU_REG_Q_2_TX_NUM_PKTS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_RX_NUM_WORDS_RCVD_REG, &val);
	printf("CPU_REG_Q_2_RX_NUM_WORDS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_TX_NUM_WORDS_SENT_REG, &val);
	printf("CPU_REG_Q_2_TX_NUM_WORDS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_RX_NUM_BYTES_RCVD_REG, &val);
	printf("CPU_REG_Q_2_RX_NUM_BYTES_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_2_TX_NUM_BYTES_SENT_REG, &val);
	printf("CPU_REG_Q_2_TX_NUM_BYTES_SENT_REG: %u\n\n", val);

	readReg(&nf2, CPU_REG_Q_3_WR_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_3_WR_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_3_WR_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_3_WR_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_3_WR_NUM_WORDS_LEFT_REG, &val);
	printf("CPU_REG_Q_3_WR_NUM_WORDS_LEFT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_WR_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_3_WR_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_RD_DATA_WORD_REG, &val);
	printf("CPU_REG_Q_3_RD_DATA_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_3_RD_CTRL_WORD_REG, &val);
	printf("CPU_REG_Q_3_RD_CTRL_WORD_REG: 0x%08x\n", val);
	readReg(&nf2, CPU_REG_Q_3_RD_NUM_WORDS_AVAIL_REG, &val);
	printf("CPU_REG_Q_3_RD_NUM_WORDS_AVAIL_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_RD_NUM_PKTS_IN_Q_REG, &val);
	printf("CPU_REG_Q_3_RD_NUM_PKTS_IN_Q_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_RX_NUM_PKTS_RCVD_REG, &val);
	printf("CPU_REG_Q_3_RX_NUM_PKTS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_TX_NUM_PKTS_SENT_REG, &val);
	printf("CPU_REG_Q_3_TX_NUM_PKTS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_RX_NUM_WORDS_RCVD_REG, &val);
	printf("CPU_REG_Q_3_RX_NUM_WORDS_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_TX_NUM_WORDS_SENT_REG, &val);
	printf("CPU_REG_Q_3_TX_NUM_WORDS_SENT_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_RX_NUM_BYTES_RCVD_REG, &val);
	printf("CPU_REG_Q_3_RX_NUM_BYTES_RCVD_REG: %u\n", val);
	readReg(&nf2, CPU_REG_Q_3_TX_NUM_BYTES_SENT_REG, &val);
	printf("CPU_REG_Q_3_TX_NUM_BYTES_SENT_REG: %u\n\n", val);
*/
	for(i=0; i<ROUTER_OP_LUT_ARP_TABLE_DEPTH; i=i+1){
	  writeReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_RD_ADDR_REG, i);
	  printf("   ARP table entry %02u: mac: ", i);
	  readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI_REG, &val);
	  readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO_REG, &val2);
	  printMAC(val, val2);
	  printf(" ip: ");
	  readReg(&nf2, ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP_REG, &val);
	  printIP(val);
	  printf("\n", val);
	}
	printf("\n");

	for(i=0; i<ROUTER_OP_LUT_ROUTE_TABLE_DEPTH; i=i+1){
	  writeReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR_REG, i);
	  readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP_REG, &val);
	  printf("   IP table entry %02u: ip: ", i);
	  printIP(val);
	  readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK_REG, &val);
	  printf(" mask: 0x%08x", val);
	  readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP_REG, &val);
	  printf(" next hop: ");
	  printIP(val);
	  readReg(&nf2, ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT_REG, &val);
	  printf(" output port: 0x%04x\n", val);
	}
	printf("\n");

	for(i=0; i<ROUTER_OP_LUT_DST_IP_FILTER_TABLE_DEPTH; i=i+1){
	  writeReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR_REG, i);
	  readReg(&nf2, ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP_REG, &val);
	  printf("   Dst IP Filter table entry %02u: ", i);
	  printIP(val);
	  printf("\n");
	}
	printf("\n");

	readReg(&nf2, ROUTER_OP_LUT_ARP_NUM_MISSES_REG, &val);
	printf("ROUTER_OP_LUT_ARP_NUM_MISSES: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_LPM_NUM_MISSES_REG, &val);
	printf("ROUTER_OP_LUT_LPM_NUM_MISSES: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_CPU_PKTS_SENT_REG, &val);
	printf("ROUTER_OP_LUT_NUM_CPU_PKTS_SENT: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_BAD_OPTS_VER_REG, &val);
	printf("ROUTER_OP_LUT_NUM_BAD_OPTS_VER: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_BAD_CHKSUMS_REG, &val);
	printf("ROUTER_OP_LUT_NUM_BAD_CHKSUMS: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_BAD_TTLS_REG, &val);
	printf("ROUTER_OP_LUT_NUM_BAD_TTLS: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_NON_IP_RCVD_REG, &val);
	printf("ROUTER_OP_LUT_NUM_NON_IP_RCVD: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_PKTS_FORWARDED_REG, &val);
	printf("ROUTER_OP_LUT_NUM_PKTS_FORWARDED: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_WRONG_DEST_REG, &val);
	printf("ROUTER_OP_LUT_NUM_WRONG_DEST: %u\n", val);
	readReg(&nf2, ROUTER_OP_LUT_NUM_FILTERED_PKTS_REG, &val);
	printf("ROUTER_OP_LUT_NUM_FILTERED_PKTS: %u\n", val);
	printf("\n");

	readReg(&nf2, ROUTER_OP_LUT_MAC_0_HI_REG, &val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_0_LO_REG, &val2);
	printf("ROUTER_OP_LUT_MAC_0: ");
	printMAC(val, val2);
	printf("\n");
	readReg(&nf2, ROUTER_OP_LUT_MAC_1_HI_REG, &val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_1_LO_REG, &val2);
	printf("ROUTER_OP_LUT_MAC_1: ");
	printMAC(val, val2);
	printf("\n");
	readReg(&nf2, ROUTER_OP_LUT_MAC_2_HI_REG, &val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_2_LO_REG, &val2);
	printf("ROUTER_OP_LUT_MAC_2: ");
	printMAC(val, val2);
	printf("\n");
	readReg(&nf2, ROUTER_OP_LUT_MAC_3_HI_REG, &val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_3_LO_REG, &val2);
	printf("ROUTER_OP_LUT_MAC_3: ");
	printMAC(val, val2);
	printf("\n");

	/*
	readReg(&nf2, ROUTER_OP_LUT_MAC_0_HI_REG, &val);
	printf("ROUTER_OP_LUT_MAC_0_HI: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_0_LO_REG, &val);
	printf("ROUTER_OP_LUT_MAC_0_LO: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_1_HI_REG, &val);
	printf("ROUTER_OP_LUT_MAC_1_HI: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_1_LO_REG, &val);
	printf("ROUTER_OP_LUT_MAC_1_LO: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_2_HI_REG, &val);
	printf("ROUTER_OP_LUT_MAC_2_HI: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_2_LO_REG, &val);
	printf("ROUTER_OP_LUT_MAC_2_LO: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_3_HI_REG, &val);
	printf("ROUTER_OP_LUT_MAC_3_HI: 0x%08x\n", val);
	readReg(&nf2, ROUTER_OP_LUT_MAC_3_LO_REG, &val);
	printf("ROUTER_OP_LUT_MAC_3_LO: 0x%08x\n\n", val);
	*/

	readReg(&nf2, IN_ARB_NUM_PKTS_SENT_REG, &val);
	printf("IN_ARB_NUM_PKTS_SENT                  %u\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_WORD_0_LO_REG, &val);
	printf("IN_ARB_LAST_PKT_WORD_0_LO             0x%08x\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_WORD_0_HI_REG, &val);
	printf("IN_ARB_LAST_PKT_WORD_0_HI             0x%08x\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_CTRL_0_REG, &val);
	printf("IN_ARB_LAST_PKT_CTRL_0                0x%02x\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_WORD_1_LO_REG, &val);
	printf("IN_ARB_LAST_PKT_WORD_1_LO             0x%08x\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_WORD_1_HI_REG, &val);
	printf("IN_ARB_LAST_PKT_WORD_1_HI             0x%08x\n", val);
	readReg(&nf2, IN_ARB_LAST_PKT_CTRL_1_REG, &val);
	printf("IN_ARB_LAST_PKT_CTRL_1                0x%02x\n", val);
	readReg(&nf2, IN_ARB_STATE_REG, &val);
	printf("IN_ARB_STATE                          %u\n\n", val);

	readReg(&nf2, OQ_QUEUE_0_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_0_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_0_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_0_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_0_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_0_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_0_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_0_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_0_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_0_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_0_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_0_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_0_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_0_CTRL_REG, &val);
	printf("OQ_QUEUE_0_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_1_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_1_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_1_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_1_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_1_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_1_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_1_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_1_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_1_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_1_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_1_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_1_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_1_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_1_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_1_CTRL_REG, &val);
	printf("OQ_QUEUE_1_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_2_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_2_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_2_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_2_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_2_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_2_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_2_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_2_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_2_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_2_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_2_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_2_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_2_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_2_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_2_CTRL_REG, &val);
	printf("OQ_QUEUE_2_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_3_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_3_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_3_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_3_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_3_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_3_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_3_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_3_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_3_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_3_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_3_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_3_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_3_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_3_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_3_CTRL_REG, &val);
	printf("OQ_QUEUE_3_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_4_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_4_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_4_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_4_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_4_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_4_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_4_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_4_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_4_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_4_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_4_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_4_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_4_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_4_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_4_CTRL_REG, &val);
	printf("OQ_QUEUE_4_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_5_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_5_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_5_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_5_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_5_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_5_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_5_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_5_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_5_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_5_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_5_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_5_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_5_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_5_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_5_CTRL_REG, &val);
	printf("OQ_QUEUE_5_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_6_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_6_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_6_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_6_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_6_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_6_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_6_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_6_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_6_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_6_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_6_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_6_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_6_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_6_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_6_CTRL_REG, &val);
	printf("OQ_QUEUE_6_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_7_NUM_WORDS_LEFT_REG, &val);
	printf("OQ_QUEUE_7_NUM_WORDS_LEFT                   %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKT_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKT_BYTES_STORED             %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_OVERHEAD_BYTES_STORED_REG, &val);
	printf("OQ_QUEUE_7_NUM_OVERHEAD_BYTES_STORED        %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_STORED_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKTS_STORED                  %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_DROPPED_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKTS_DROPPED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKT_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKT_BYTES_REMOVED            %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_OVERHEAD_BYTES_REMOVED_REG, &val);
	printf("OQ_QUEUE_7_NUM_OVERHEAD_BYTES_REMOVED       %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_REMOVED_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKTS_REMOVED                 %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_ADDR_LO_REG, &val);
	printf("OQ_QUEUE_7_ADDR_LO                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_7_ADDR_HI_REG, &val);
	printf("OQ_QUEUE_7_ADDR_HI                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_7_WR_ADDR_REG, &val);
	printf("OQ_QUEUE_7_WR_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_7_RD_ADDR_REG, &val);
	printf("OQ_QUEUE_7_RD_ADDR                       0x%08x\n", val);
	readReg(&nf2, OQ_QUEUE_7_NUM_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_7_NUM_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_MAX_PKTS_IN_Q_REG, &val);
	printf("OQ_QUEUE_7_MAX_PKTS_IN_Q                    %u\n", val);
	readReg(&nf2, OQ_QUEUE_7_CTRL_REG, &val);
	printf("OQ_QUEUE_7_CTRL                          0x%08x\n\n", val);

	readReg(&nf2, OQ_QUEUE_0_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_0_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_1_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_1_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_2_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_2_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_3_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_3_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_4_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_4_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_5_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_5_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_6_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_6_FULL_THRESH                      %u\n",val);
	readReg(&nf2, OQ_QUEUE_7_FULL_THRESH_REG, &val);
	printf("OQ_QUEUE_7_FULL_THRESH                      %u\n\n",val);
/*
	readReg(&nf2, DELAY_ENABLE_REG, &val);
	printf("DELAY_ENABLE_REG                          0x%08x\n",val);
	readReg(&nf2, DELAY_1ST_WORD_HI_REG, &val);
	printf("DELAY_1ST_WORD_HI_REG                     0x%08x\n",val);
	readReg(&nf2, DELAY_1ST_WORD_LO_REG, &val);
	printf("DELAY_1ST_WORD_LO_REG                     0x%08x\n",val);
	readReg(&nf2, DELAY_LENGTH_REG, &val);
	printf("DELAY_LENGTH_REG                          0x%08x\n\n",val);

	readReg(&nf2, RATE_LIMIT_ENABLE_REG, &val);
	printf("RATE_LIMIT_ENABLE_REG                     0x%08x\n",val);
	readReg(&nf2, RATE_LIMIT_SHIFT_REG, &val);
	printf("RATE_LIMIT_SHIFT_REG                      0x%08x\n\n",val);
*/

}
コード例 #26
0
// Put the FXOS8700CQ into standby mode.
// It must be in standby for modifying most registers
void FXOS8700CQ::standby()
{
	byte c = readReg(FXOS8700CQ_CTRL_REG1);
	writeReg(FXOS8700CQ_CTRL_REG1, c & ~(0x01));
}
コード例 #27
0
ファイル: pkt_gen.c プロジェクト: AndreMantas/oflops
int 
main() {
  unsigned val;
  int i;
  uint32_t queue_addr_offset = OQ_QUEUE_1_ADDR_LO_REG - OQ_QUEUE_0_ADDR_LO_REG;
  uint32_t curr_addr = 0;
  uint32_t rx_queue_size = (MEM_SIZE - 4*XMIT_QUEUE_SIZE)/8;

  uint32_t src_port = 0, dst_port = 0x100;
  uint32_t word_len = 0, len = 0x100;
  uint32_t queue_base_addr[] = {0,0,0,0};

  char *data;
  uint32_t data_len, rate_limit_offset;
  uint32_t pointer = 0, pkt_pointer = 0;
  uint32_t drop;

  nf2.device_name = DEFAULT_IFACE;
  if (check_iface(&nf2)) 
    exit(1);

  if (openDescriptor(&nf2))
    exit(1);

  // Disable the output queues by writing 0x0 to the enable register
  writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG,  0x00);

  //generate the data we want to send
  init_data(&det);
  innitialize_generator_packet(&state, &det);

  // Disable output queues
  // Note: 3 queues per port -- rx, tx and tx-during-setup
  for (i = 0; i < 3 * NUM_PORTS; i++) {
    writeReg (&nf2, (OQ_QUEUE_0_CTRL_REG + i*queue_addr_offset), 0x00);
  }

  //Set queue sizes thourght the relevant registers
  for (i = 0; i<NUM_PORTS; i++) {
    //set queue sizes for tx-during-setup
    writeReg (&nf2, (OQ_QUEUE_0_ADDR_LO_REG + (i*2)*queue_addr_offset), curr_addr);
    writeReg (&nf2, (OQ_QUEUE_0_ADDR_HI_REG + (i*2)*queue_addr_offset), curr_addr + XMIT_QUEUE_SIZE - 1);
    writeReg (&nf2, (OQ_QUEUE_0_CTRL_REG + (i*2)*queue_addr_offset), 0x02);
    curr_addr += XMIT_QUEUE_SIZE;

    //Set queue sizes for RX queues
    writeReg (&nf2,OQ_QUEUE_0_ADDR_LO_REG + (i*2+1)*queue_addr_offset, curr_addr);
    writeReg (&nf2,OQ_QUEUE_0_ADDR_HI_REG + (i*2+1)*queue_addr_offset, curr_addr+rx_queue_size-1);
    writeReg (&nf2,OQ_QUEUE_0_CTRL_REG + (i*2+1)*queue_addr_offset, 0x02);
    curr_addr += rx_queue_size;

  }
  
  for (i = 0; i < NUM_PORTS; i++) {
    //Set queue sizes for TX queues
    writeReg (&nf2, OQ_QUEUE_0_ADDR_LO_REG + (i + 2*NUM_PORTS)*queue_addr_offset, curr_addr);
    writeReg (&nf2, OQ_QUEUE_0_ADDR_HI_REG + (i + 2*NUM_PORTS)*queue_addr_offset, curr_addr + ((i == 3)?  
											       det.pkt_size + ceil(det.pkt_size/8) + 1:1) - 1);
    writeReg (&nf2,OQ_QUEUE_0_CTRL_REG + (i+2*NUM_PORTS)*queue_addr_offset,  0x02);
    queue_base_addr[i] = curr_addr;
    curr_addr += ((i == 3)? det.pkt_size + ceil(det.pkt_size/8) + 1:1);

    //$queue_base_addr[$i] = $curr_addr;
    //$curr_addr += $queue_size;
  }

  //data + netfpga packet length + 1 byte for the ctrl part for each word
  data_len = state.data_len + 9 + ceil((float)state.data_len/8);
  data = malloc(data_len);
  bzero(data, data_len);
  pointer = 0;
  pkt_pointer = 0;

  //append netfpga header
  data[pointer] = IO_QUEUE_STAGE_NUM;
  pointer++;
  *(uint16_t *)(data + pointer ) = 0x0;
  pointer+=2;
  *(uint16_t *)(data + pointer ) = (uint16_t)ceil((float)state.data_len/8);
  pointer+=2;
  *(uint16_t *)(data + pointer ) = (uint16_t)(0x100 << 3);
  pointer+=2;
  *(uint16_t *)(data + pointer ) = (uint16_t)state.data_len;
  pointer+=2;

  printf("size: %d %d output: %d\n", (uint16_t)ceil((float)state.data_len/8), state.data_len, (uint16_t)(0x100 << 3));
  
  //put data
  queue_addr_offset = OQ_QUEUE_GROUP_INST_OFFSET;

  for(i = 0; i < floor((float)state.data_len/8); i++) {
    data[pointer] = 0x0;
    pointer++;
    memcpy(data+pointer, state.data + pkt_pointer, 8);
    pkt_pointer += 8;
    pointer += 8;
  }
  data[pointer] = state.data_len - pkt_pointer;
  pointer++;
  memcpy(data+pointer, state.data + pkt_pointer, state.data_len - pkt_pointer); 
  pointer+= state.data_len - pkt_pointer;
  

  uint32_t sram_addr = SRAM_BASE_ADDR + queue_base_addr[3]*16;
  
  //finally copy data on the SRAM
  for (i = 0; i < data_len; i+=3) {
    writeReg (&nf2,sram_addr + 0x0, *((uint32_t *)(data + 4*i)));
    writeReg (&nf2,sram_addr + 0x4, *((uint32_t *)(data + 4*(i + 1))));
    writeReg (&nf2,sram_addr + 0x8, *((uint32_t *)(data + 4*(i + 2))));
    int j;
    if (4*i < 64) {
      for (j = 4*i; (j < 4*i+16); j+=4) {
	printf("%02x%02x%02x%02x ", (uint8_t)data[j], (uint8_t)data[j+1], (uint8_t)data[j+2], (uint8_t)data[j+3]);
      }
      printf("\n");
    }
    sram_addr += 12;
  }

  //ff 0000 af00 0008 7805 0000 15

  // Set the rate limiter for CPU queues
/*   for (i = 0; i < 4; i++) { */
/*     rate_limiter_set(i * 2 + 1, 200000); */
/*   } */

  queue_addr_offset = OQ_QUEUE_GROUP_INST_OFFSET;
  // Set the number of iterations for the queues with pcap files
  for (i = 0; i < NUM_PORTS; i++) {
    // rate_limiter_disable($i * 2);
    rate_limit_offset = RATE_LIMIT_1_CTRL_REG - RATE_LIMIT_0_CTRL_REG;

    //disable repetition
    writeReg(&nf2, OQ_QUEUE_0_CTRL_REG + (i + 2 * NUM_PORTS) * queue_addr_offset, 0x0);
    //
    writeReg (&nf2, RATE_LIMIT_0_CTRL_REG + 2 * i * rate_limit_offset, 0x0);
    // disable rate limit on CPU queues
    writeReg (&nf2, RATE_LIMIT_0_CTRL_REG + (2*i + 1) * rate_limit_offset, 0x0);
  }

  //set queue 3 to repeat once
  writeReg(&nf2, OQ_QUEUE_0_CTRL_REG + (3 + 2 * NUM_PORTS) * queue_addr_offset, 0x1);
  writeReg(&nf2, OQ_QUEUE_0_MAX_ITER_REG + (3 + 2 * NUM_PORTS) * queue_addr_offset, 1);


  //Enable the packet generator hardware to send the packets
  drop = 0;
/*   for (i = 0; i < NUM_PORTS; i++) { */
/*       drop = drop | (1 << i); */
    
/*     drop = drop << 8; */
/*   } */
  printf("drop 0x%X...\n", drop | 0xF);
  //packet_generator_enable (drop | 0xF);
  writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG,  drop | 0xF);

  sleep(10);

  //Finish up
  writeReg(&nf2, PKT_GEN_CTRL_ENABLE_REG, 0x0);
  for (i = 0; i < 1024; i++) {
    //    reset_delay();
    writeReg(&nf2, DELAY_RESET_REG, 1);
  }

  //display_xmit_metrics();
  printf("Transmit statistics:\n");
  printf("====================\n\n");

  for (i = 0; i < NUM_PORTS; i++) {
    uint32_t pkt_cnt, iter_cnt;
    readReg(&nf2, OQ_QUEUE_0_NUM_PKTS_REMOVED_REG + (i + 8) * queue_addr_offset, &pkt_cnt);
    readReg(&nf2, OQ_QUEUE_0_CURR_ITER_REG + (i + 8) * queue_addr_offset, &iter_cnt);
      
      printf("%d:\n", i + 8);
      printf("\tPackets: %u\n", pkt_cnt);
      printf("\tCompleted iterations: %u\n", iter_cnt);
  }
  printf("\n\n");

  //display_capture_metrics();
  
  printf("sending packet completed...");
  
  closeDescriptor(&nf2);
  
  printf("Test successful\n");  
  
}
コード例 #28
0
// Put the FXOS8700CQ into active mode.
// Needs to be in this mode to output data.
void FXOS8700CQ::active()
{
	byte c = readReg(FXOS8700CQ_CTRL_REG1);
	writeReg(FXOS8700CQ_CTRL_REG1, c | 0x01);
}
コード例 #29
0
ファイル: reg_proxy_server.c プロジェクト: ahirOrg/ahir
/* Implements the register protocol:
 * - Read which device
 * - Read request (struct reg_request)
 * - Return result
 */
int parse_request(int socket_to_client, struct nf2device **nf2devices,
		int num_netfpgas) {
	int nread;
	struct reg_request req;

	/* Read the request struct */
	while ( (nread=readn(socket_to_client, (char *)&req,
			sizeof(struct reg_request))) == sizeof(struct reg_request)) {
		DPRINTF("Received reg_request:\n");
		dprint_req(&req);

		/* execute request */
		if (req.device_num < num_netfpgas) {
			DPRINTF("Device num checks out.\n");
			if (req.type == READ_REQ) {
				DPRINTF("Executing read.\n");
				readReg(nf2devices[req.device_num], req.address, &req.data);
			} else if (req.type == WRITE_REQ) {
				DPRINTF("Executing write.\n");
				writeReg(nf2devices[req.device_num], req.address, req.data);
			} else if (req.type == CHECK_REQ) {
				DPRINTF("Executing check.\n");
				req.data = 1;
			} else if (req.type == OPEN_REQ) {
				DPRINTF("Executing open.\n");
				req.data = 1;
			} else if (req.type == CLOSE_REQ) {
				DPRINTF("Executing close.\n");
				DPRINTF("Sending response:\n");
				dprint_req(&req);
				if (writen(socket_to_client, (const char *)&req,
						sizeof(struct reg_request))
						< sizeof(struct reg_request)) {
					fprintf(stderr, "Error: could not write to client.\n");
					return -1;
				}
				return 0;
			} else {
				fprintf(stderr, "Error: Unknown request type %u.\n", req.type);
				req.error = -1;
			}
		} else {
			DPRINTF("Device number bad.\n");
			if (req.type == CHECK_REQ) {
				DPRINTF("Executing check_req.\n");
				req.data = 0;
			} else {
				DPRINTF("Executing else.\n");
				req.error = -1;
			}
		}

		/* send response */
		DPRINTF("Sending response:\n");
		dprint_req(&req);
		if (writen(socket_to_client, (const char *)&req,
				sizeof(struct reg_request)) < sizeof(struct reg_request)) {
			fprintf(stderr, "Error: could not write to client.\n");
			return -1;
		}
	}

	if (nread == 0) {
		return 0;
	} else if (nread < 0) {
		fprintf(stderr, "Error reading the reg_request struct.\n");
		return -1;
	} else if (nread < sizeof(struct reg_request)) {
		fprintf(stderr, "Error: Did not read full reg_request struct.\n");
		return -1;
	}
}
コード例 #30
0
ファイル: mips_instr.c プロジェクト: brunsgaard/ark2012
void add_instr (int rd, int rs, int rt)
{
    writeReg(rd, rs + rt);
}