void rx_init() { writeregs( bbcal , sizeof(bbcal) ); writeregs( rfcal , sizeof(rfcal) ); writeregs( demodcal , sizeof(demodcal) ); int rxaddress[5] = {0xCC,0xCC,0xCC,0xCC,0xCC}; xn_writerxaddress( rxaddress); xn_writetxaddress( rxaddress); xn_writereg( EN_AA , 0 ); // aa disabled xn_writereg( EN_RXADDR , 1 ); // pipe 0 only // xn_writereg( RF_SETUP , B00000001); // lna high current on ( better performance ) xn_writereg( RF_SETUP , B00000111); xn_writereg( RX_PW_P0 , PAYLOAD_LENGHT ); // payload size xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?) xn_writereg( SETUP_AW , 3 ); // address size (5 bits) xn_command( FLUSH_RX); xn_writereg( RF_CH , 2 ); // bind channel xn_writereg( 0 , B00001111 ); // power up, crc enabled }
void rx_init() { uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 }; writeregs( bbcal , sizeof(bbcal) ); uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0x80 , 0x61 , 0xbb , 0xab , 0x9c }; writeregs( rfcal , sizeof(rfcal) ); uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03}; writeregs( demodcal , sizeof(demodcal) ); int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 }; xn_writerxaddress( rxaddress); xn_writereg( EN_AA , 0 ); // aa disabled xn_writereg( EN_RXADDR , 1 ); // pipe 0 only xn_writereg( RF_SETUP , B00000001); // lna high current on ( better performance ) xn_writereg( RX_PW_P0 , 15 ); // payload size xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?) xn_writereg( SETUP_AW , 3 ); // address size (5 bits) xn_command( FLUSH_RX); xn_writereg( RF_CH , 0 ); // bind on channel 0 xn_writereg( 0 , B00001111 ); // power up, crc enabled #ifdef RADIO_CHECK void check_radio(void); check_radio(); #endif }
void ega_hwterm(void) { setmode(MODE_SET); /* Copy character table from ROM back into bit plane 2 before turning * off graphics. */ out_word(SEQREG, 0x0100); /* syn reset */ out_word(SEQREG, 0x0402); /* cpu writes only to map 2 */ out_word(SEQREG, 0x0704); /* sequential addressing */ out_word(SEQREG, 0x0300); /* clear synchronous reset */ out_word(GRREG, 0x0204); /* select map 2 for CPU reads */ out_word(GRREG, 0x0005); /* disable odd-even addressing */ #if ROMFONT { FARADDR srcoffset; FARADDR destoffset; int data; int ch; int row; srcoffset = rom_char_addr; destoffset = EGA_BASE; for (ch = 0; ch < FONT_CHARS; ch++) { for(row = 0; row < ROM_CHAR_HEIGHT; row++) { data = GETBYTE_FP(srcoffset++); PUTBYTE_FP(destoffset++, data); } destoffset += (RAM_SCAN_LINES - ROM_CHAR_HEIGHT); } } #endif /* Finally set the registers back for text mode. */ writeregs(graph_off); }
void rx_init() { // always on (CH_ON) channel set 1 aux[AUXNUMBER - 2] = 1; // always off (CH_OFF) channel set 0 aux[AUXNUMBER - 1] = 0; #ifdef AUX1_START_ON aux[CH_AUX1] = 1; #endif #ifdef RADIO_XN297L #define XN_TO_RX B10001111 #define XN_TO_TX B10000010 #define XN_POWER B00111111 #endif #ifdef RADIO_XN297 static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 }; writeregs( bbcal , sizeof(bbcal) ); // new values static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c }; writeregs( rfcal , sizeof(rfcal) ); static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03}; writeregs( demodcal , sizeof(demodcal) ); #define XN_TO_RX B00001111 #define XN_TO_TX B00000010 #define XN_POWER B00000111 #endif bleinit(); delay(100); int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 }; xn_writerxaddress( rxaddress); xn_writereg( EN_AA , 0 ); // aa disabled xn_writereg( EN_RXADDR , 1 ); // pipe 0 only xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance ) xn_writereg( RX_PW_P0 , 15 ); // payload size xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?) xn_writereg( SETUP_AW , 3 ); // address size (5 bits) xn_command( FLUSH_RX); xn_writereg( RF_CH , 0 ); // bind on channel 0 // set above // xn_writereg( 29 , 32); // feture reg , CE mode (software controlled) #ifdef RADIO_XN297L xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce spi_cson(); spi_sendbyte( 0xFD); // internal CE high command spi_sendbyte( 0); // required for above spi_csoff(); #endif #ifdef RADIO_XN297 xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce #endif xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode #ifdef RADIO_CHECK void check_radio(void); check_radio(); #endif }
void ega_hwinit(void) { writeregs(graphics_on); }
void rx_init() { // always on (CH_ON) channel set 1 aux[AUXNUMBER - 2] = 1; // always off (CH_OFF) channel set 0 aux[AUXNUMBER - 1] = 0; #ifdef AUX1_START_ON aux[CH_AUX1] = 1; #endif #ifdef AUX4_START_ON aux[CH_AUX4] = 1; #endif #ifdef RADIO_XN297L #define XN_TO_RX B10001111 #define XN_TO_TX B10000010 #define XN_POWER B00111111 #endif #ifdef RADIO_XN297 static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 }; writeregs( bbcal , sizeof(bbcal) ); // new values static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c }; writeregs( rfcal , sizeof(rfcal) ); static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03}; //static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , B00100111 , B00000000}; writeregs( demodcal , sizeof(demodcal) ); #define XN_TO_RX B00001111 #define XN_TO_TX B00000010 //#define XN_POWER B00000111 // disabled by silverAG for SilverVISE - value is added from config.h // SilverVISE - start: #ifdef TX_POWER_GENERAL // use value from config.h #define XN_POWER TX_POWER_GENERAL #else #define XN_POWER B00000111 #endif // SilverVISE - end #endif bleinit(); delay(100); int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 }; xn_writerxaddress( rxaddress); xn_writereg( EN_AA , 0 ); // aa disabled xn_writereg( EN_RXADDR , 1 ); // pipe 0 only xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance ) xn_writereg( RX_PW_P0 , 15 ); // payload size xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?) xn_writereg( SETUP_AW , 3 ); // address size (5 bits) xn_command( FLUSH_RX); xn_writereg( RF_CH , 0 ); // bind on channel 0 #ifdef RADIO_XN297L xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce spi_cson(); spi_sendbyte( 0xFD); // internal CE high command spi_sendbyte( 0); // required for above spi_csoff(); #endif #ifdef RADIO_XN297 xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce #endif xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode #ifdef RADIO_CHECK int rxcheck = xn_readreg( 0x0f); // rx address pipe 5 // should be 0xc6 extern void failloop( int); if ( rxcheck != 0xc6) failloop(3); #endif }