// allocate PRegs that are used & defined solely within this BB void BB::slowAllocateTempRegisters(BitVector** hardwired, PRegBList* tempRegs, BitVectorBList* lives) { // clear temporary data structures tempRegs->clear(); lives->clear(); fint i; for (i = 0; i < NumTempRegs; i++) { hardwired[i]->setLength(nnodes); hardwired[i]->clear(); } for (i = 0; i < duInfo.info->length(); i++) { // collect temp regs and hardwired temp regs PReg* r = duInfo.info->nth(i)->reg; if (r->isLocalTo(this)) { assert(r->dus.first()->index == i, "should be the same"); if (r->isUnused()) { // unused register - ignore } else { DUInfo* info = duInfo.info->nth(r->dus.first()->index); tempRegs->append(r); BitVector* bv = new BitVector(nnodes); lives->append(bv); fint firstUse = 0, lastUse = nnodes - 1; duInfo.info->nth(i)->getLiveRange(firstUse, lastUse); bv->addFromTo(firstUse, lastUse); } } else if (isTempReg(r->loc)) { fint firstUse = 0, lastUse = nnodes - 1; if (!r->incorrectDU()) { duInfo.info->nth(i)->getLiveRange(firstUse, lastUse); } else { // can't really compute live range since the temp might be non-local // so assume it's live from first node til the end } hardwired[RegToTempNo[r->loc]]->addFromTo(firstUse, lastUse); } } // now, tempRegs holds all temp regs, and lives contains each register's // live range (one bit per node, 1 = reg is live); hardwired contains // the ranges where temp regs are already taken (e.g. for NLR, calls, etc) // cycle through the temp registers to (hopefully) allow more optimizations // later (e.g. scheduling) fint lastTemp = 0; # define nextTemp(n) (n == NumTempRegs - 1) ? 0 : n + 1 for (i = 0; i < tempRegs->length(); i++) { // try to allocate tempRegs[i] to a temp register PReg* r = tempRegs->nth(i); if (r->loc != UnAllocated) { assert(r->regClass == 0, "should have been cleared"); continue; } BitVector* liveRange = lives->nth(i); for (fint tempNo = lastTemp, ntries = 0; ntries < NumTempRegs; tempNo = nextTemp(tempNo), ntries++) { if (liveRange->isDisjointFrom(hardwired[tempNo])) { Location temp = TempRegs[tempNo]; doAlloc(r, temp); hardwired[tempNo]->unionWith(liveRange); lastTemp = nextTemp(tempNo); break; } } if ( r->loc == UnAllocated && (PrintSICTempRegisterAllocation || WizardMode && TARGET_ARCH != I386_ARCH /* happens normally in I386; few regs */ )) { lprintf("*could NOT find temp assignment for local %s in BB%ld\n", r->name(), (void*)id()); } else if (r->loc == UnAllocated) { if (PrintSICTempRegisterAllocation) lprintf("out of temp regs"); } r->regClass = 0; } }