/// This function inserts clones of Filler into predecessor blocks. static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) { MachineFunction *MF = Filler->getParent()->getParent(); for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) { if (I->second) { MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler)); ++UsefulSlots; } else { I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler)); } } }
bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** Register Stackifying **********\n" "********** Function: " << MF.getName() << '\n'); bool Changed = false; MachineRegisterInfo &MRI = MF.getRegInfo(); WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>(); // Walk the instructions from the bottom up. Currently we don't look past // block boundaries, and the blocks aren't ordered so the block visitation // order isn't significant, but we may want to change this in the future. for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : reverse(MBB)) { MachineInstr *Insert = &MI; // Don't nest anything inside a phi. if (Insert->getOpcode() == TargetOpcode::PHI) break; // Iterate through the inputs in reverse order, since we'll be pulling // operands off the stack in FIFO order. for (MachineOperand &Op : reverse(Insert->uses())) { // We're only interested in explicit virtual register operands. if (!Op.isReg() || Op.isImplicit()) continue; unsigned Reg = Op.getReg(); if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; // Only consider registers with a single definition. // TODO: Eventually we may relax this, to stackify phi transfers. MachineInstr *Def = MRI.getVRegDef(Reg); if (!Def) continue; // There's no use in nesting implicit defs inside anything. if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF) continue; // Argument instructions represent live-in registers and not real // instructions. if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 || Def->getOpcode() == WebAssembly::ARGUMENT_I64 || Def->getOpcode() == WebAssembly::ARGUMENT_F32 || Def->getOpcode() == WebAssembly::ARGUMENT_F64) continue; // Single-use expression trees require defs that have one use, or that // they be trivially clonable. // TODO: Eventually we'll relax this, to take advantage of set_local // returning its result. bool OneUse = MRI.hasOneUse(Reg); if (!OneUse && !Def->isMoveImmediate()) continue; // For now, be conservative and don't look across block boundaries, // unless we have something trivially clonable. // TODO: Be more aggressive. if (Def->getParent() != &MBB && !Def->isMoveImmediate()) continue; // For now, be simple and don't reorder loads, stores, or side effects. // TODO: Be more aggressive. if ((Def->mayLoad() || Def->mayStore() || Def->hasUnmodeledSideEffects())) continue; Changed = true; if (OneUse) { // Move the def down and nest it in the current instruction. MBB.insert(MachineBasicBlock::instr_iterator(Insert), Def->removeFromParent()); MFI.stackifyVReg(Reg); Insert = Def; } else { // Clone the def down and nest it in the current instruction. MachineInstr *Clone = MF.CloneMachineInstr(Def); unsigned OldReg = Def->getOperand(0).getReg(); unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); assert(Op.getReg() == OldReg); assert(Clone->getOperand(0).getReg() == OldReg); Op.setReg(NewReg); Clone->getOperand(0).setReg(NewReg); MBB.insert(MachineBasicBlock::instr_iterator(Insert), Clone); MFI.stackifyVReg(Reg); Insert = Clone; } } } } return Changed; }