MachineBasicBlock::iterator MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) { iterator E = end(); while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue())) ++I; // FIXME: This needs to change if we wish to bundle labels / dbg_values // inside the bundle. assert((I == E || !I->isInsideBundle()) && "First non-phi / non-label instruction is inside a bundle!"); return I; }
bool Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const { while (MBBI->isDebugValue()) { ++MBBI; if (MBBI == MBB.end()) return false; } unsigned PredReg = 0; return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; }
/// saveScavengerRegister - Spill the register so it can be used by the /// register scavenger. Return true. bool ThumbRegisterInfo::saveScavengerRegister( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const { const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>(); if (!STI.isThumb1Only()) return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg); // Thumb1 can't use the emergency spill slot on the stack because // ldr/str immediate offsets must be positive, and if we're referencing // off the frame pointer (if, for example, there are alloca() calls in // the function, the offset will be negative. Use R12 instead since that's // a call clobbered register that we know won't be used in Thumb1 mode. const TargetInstrInfo &TII = *STI.getInstrInfo(); DebugLoc DL; AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr)) .addReg(ARM::R12, RegState::Define) .addReg(Reg, RegState::Kill)); // The UseMI is where we would like to restore the register. If there's // interference with R12 before then, however, we'll need to restore it // before that instead and adjust the UseMI. bool done = false; for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { if (II->isDebugValue()) continue; // If this instruction affects R12, adjust our restore point. for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { const MachineOperand &MO = II->getOperand(i); if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { UseMI = II; done = true; break; } if (!MO.isReg() || MO.isUndef() || !MO.getReg() || TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue; if (MO.getReg() == ARM::R12) { UseMI = II; done = true; break; } } } // Restore the register from R12 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)). addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); return true; }
/// runOnMachineFunction - Loop over all of the basic blocks, inserting /// NOOP instructions before early exits. bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) { const AttributeSet &FnAttrs = MF.getFunction()->getAttributes(); if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) || FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize)) { return false; } TM = &MF.getTarget(); if (!TM->getSubtarget<X86Subtarget>().padShortFunctions()) return false; TII = TM->getInstrInfo(); // Search through basic blocks and mark the ones that have early returns ReturnBBs.clear(); VisitedBBs.clear(); findReturns(MF.begin()); bool MadeChange = false; MachineBasicBlock *MBB; unsigned int Cycles = 0; // Pad the identified basic blocks with NOOPs for (DenseMap<MachineBasicBlock*, unsigned int>::iterator I = ReturnBBs.begin(); I != ReturnBBs.end(); ++I) { MBB = I->first; Cycles = I->second; if (Cycles < Threshold) { // BB ends in a return. Skip over any DBG_VALUE instructions // trailing the terminator. assert(MBB->size() > 0 && "Basic block should contain at least a RET but is empty"); MachineBasicBlock::iterator ReturnLoc = --MBB->end(); while (ReturnLoc->isDebugValue()) --ReturnLoc; assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && "Basic block does not end with RET"); addPadding(MBB, ReturnLoc, Threshold - Cycles); NumBBsPadded++; MadeChange = true; } } return MadeChange; }
/// isSimpleBB - True if this BB has only one unconditional jump. bool TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) { if (TailBB->succ_size() != 1) return false; if (TailBB->pred_empty()) return false; MachineBasicBlock::iterator I = TailBB->begin(); MachineBasicBlock::iterator E = TailBB->end(); while (I != E && I->isDebugValue()) ++I; if (I == E) return true; return I->isUnconditionalBranch(); }
void Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const { MachineBasicBlock *MBB = Tail->getParent(); ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); if (!AFI->hasITBlocks()) { TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); return; } // If the first instruction of Tail is predicated, we may have to update // the IT instruction. unsigned PredReg = 0; ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); MachineBasicBlock::iterator MBBI = Tail; if (CC != ARMCC::AL) // Expecting at least the t2IT instruction before it. --MBBI; // Actually replace the tail. TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); // Fix up IT. if (CC != ARMCC::AL) { MachineBasicBlock::iterator E = MBB->begin(); unsigned Count = 4; // At most 4 instructions in an IT block. while (Count && MBBI != E) { if (MBBI->isDebugValue()) { --MBBI; continue; } if (MBBI->getOpcode() == ARM::t2IT) { unsigned Mask = MBBI->getOperand(1).getImm(); if (Count == 4) MBBI->eraseFromParent(); else { unsigned MaskOn = 1 << Count; unsigned MaskOff = ~(MaskOn - 1); MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); } return; } --MBBI; --Count; } // Ctrl flow can reach here if branch folding is run before IT block // formation pass. } }
unsigned PatmosInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; if (!I->isBranch()) break; // Not a branch // Remove the branch. I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
/// collectDebgValues - Scan instructions following MI and collect any /// matching DBG_VALUEs. static void collectDebugValues(MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DbgValues) { DbgValues.clear(); if (!MI->getOperand(0).isReg()) return; MachineBasicBlock::iterator DI = MI; ++DI; for (MachineBasicBlock::iterator DE = MI->getParent()->end(); DI != DE; ++DI) { if (!DI->isDebugValue()) return; if (DI->getOperand(0).isReg() && DI->getOperand(0).getReg() == MI->getOperand(0).getReg()) DbgValues.push_back(DI); } }
unsigned BPFInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; if (I->getOpcode() != BPF::JMP) break; // Remove the branch. I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; if (I != MBB.end() && !I->isDebugValue()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = *MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FrameIndex), MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), MFI.getObjectAlignment(FrameIndex)); BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) .addFrameIndex(FrameIndex) .addImm(0) .addMemOperand(MMO); }
// Fill MBBs and Terminators, setting the addresses on the assumption // that no branches need relaxation. Return the size of the function under // this assumption. uint64_t SystemZLongBranch::initMBBInfo() { MF->RenumberBlocks(); unsigned NumBlocks = MF->size(); MBBs.clear(); MBBs.resize(NumBlocks); Terminators.clear(); Terminators.reserve(NumBlocks); BlockPosition Position(MF->getAlignment()); for (unsigned I = 0; I < NumBlocks; ++I) { MachineBasicBlock *MBB = MF->getBlockNumbered(I); MBBInfo &Block = MBBs[I]; // Record the alignment, for quick access. Block.Alignment = MBB->getAlignment(); // Calculate the size of the fixed part of the block. MachineBasicBlock::iterator MI = MBB->begin(); MachineBasicBlock::iterator End = MBB->end(); while (MI != End && !MI->isTerminator()) { Block.Size += TII->getInstSizeInBytes(*MI); ++MI; } skipNonTerminators(Position, Block); // Add the terminators. while (MI != End) { if (!MI->isDebugValue()) { assert(MI->isTerminator() && "Terminator followed by non-terminator"); Terminators.push_back(describeTerminator(*MI)); skipTerminator(Position, Terminators.back(), false); ++Block.NumTerminators; } ++MI; } } return Position.Address; }
unsigned LanaiInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::iterator Instruction = MBB.end(); unsigned Count = 0; while (Instruction != MBB.begin()) { --Instruction; if (Instruction->isDebugValue()) continue; if (Instruction->getOpcode() != Lanai::BT && Instruction->getOpcode() != Lanai::BRCC) { break; } // Remove the branch. Instruction->eraseFromParent(); Instruction = MBB.end(); ++Count; } return Count; }
unsigned Mos6502InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; if (I->getOpcode() != M6502::BA && I->getOpcode() != M6502::BCOND && I->getOpcode() != M6502::FBCOND) break; // Not a branch I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; if (I->getOpcode() != BPF::JMP) break; // Remove the branch. I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; if (I != MBB.end() && !I->isDebugValue()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = *MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FrameIndex), MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), MFI.getObjectAlignment(FrameIndex)); BuildMI(MBB, I, DL, get(XCore::STWFI)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) .addImm(0) .addMemOperand(MMO); }
void Thumb2HazardRecognizer::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); unsigned Opcode = MI->getOpcode(); if (ITBlockSize) { --ITBlockSize; } else if (Opcode == ARM::t2IT) { unsigned Mask = MI->getOperand(1).getImm(); unsigned NumTZ = CountTrailingZeros_32(Mask); assert(NumTZ <= 3 && "Invalid IT mask!"); ITBlockSize = 4 - NumTZ; MachineBasicBlock::iterator I = MI; for (unsigned i = 0; i < ITBlockSize; ++i) { // Advance to the next instruction, skipping any dbg_value instructions. do { ++I; } while (I->isDebugValue()); ITBlockMIs[ITBlockSize-1-i] = &*I; } } PostRAHazardRecognizer::EmitInstruction(SU); }
unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { // Most of the code and comments here are boilerplate. MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; unsigned Cond; const MachineOperand *Target; if (!isBranch(I, Cond, Target)) break; if (!Target->isMBB()) break; // Remove the branch. I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator Instruction = MBB.end(); unsigned Count = 0; while (Instruction != MBB.begin()) { --Instruction; if (Instruction->isDebugValue()) continue; if (Instruction->getOpcode() != Lanai::BT && Instruction->getOpcode() != Lanai::BRCC) { break; } // Remove the branch. Instruction->eraseFromParent(); Instruction = MBB.end(); ++Count; } return Count; }
unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { --I; if (I->isDebugValue()) { continue; } //:TODO: add here the missing jmp instructions once they are implemented // like jmp, {e}ijmp, and other cond branches, ... if (I->getOpcode() != AVR::RJMPk && getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) { break; } // Remove the branch. I->eraseFromParent(); I = MBB.end(); ++Count; } return Count; }
bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) { MF = &mf; TII = MF->getTarget().getInstrInfo(); TRI = MF->getTarget().getRegisterInfo(); LiveRegs = 0; assert(NumRegs == RC->getNumRegs() && "Bad regclass"); DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: " << RC->getName() << " **********\n"); // If no relevant registers are used in the function, we can skip it // completely. bool anyregs = false; for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); I != E; ++I) if (MF->getRegInfo().isPhysRegUsed(*I)) { anyregs = true; break; } if (!anyregs) return false; // Initialize the AliasMap on the first use. if (AliasMap.empty()) { // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC, // or -1. AliasMap.resize(TRI->getNumRegs(), -1); for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid(); ++AI) AliasMap[*AI] = i; } MachineBasicBlock *Entry = MF->begin(); ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry); SmallVector<MachineBasicBlock*, 16> Loops; for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { MachineBasicBlock *MBB = *MBBI; enterBasicBlock(MBB); if (SeenUnknownBackEdge) Loops.push_back(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) visitInstr(I); leaveBasicBlock(MBB); } // Visit all the loop blocks again in order to merge DomainValues from // back-edges. for (unsigned i = 0, e = Loops.size(); i != e; ++i) { MachineBasicBlock *MBB = Loops[i]; enterBasicBlock(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) if (!I->isDebugValue()) processDefs(I, false); leaveBasicBlock(MBB); } // Clear the LiveOuts vectors and collapse any remaining DomainValues. for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI); if (FI == LiveOuts.end() || !FI->second) continue; for (unsigned i = 0, e = NumRegs; i != e; ++i) if (FI->second[i].Value) release(FI->second[i].Value); delete[] FI->second; } LiveOuts.clear(); Avail.clear(); Allocator.DestroyAll(); return false; }
/// findSurvivorReg - Return the candidate register that is unused for the /// longest after StargMII. UseMI is set to the instruction where the search /// stopped. /// /// No more than InstrLimit instructions are inspected. /// unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI, BitVector &Candidates, unsigned InstrLimit, MachineBasicBlock::iterator &UseMI) { int Survivor = Candidates.find_first(); assert(Survivor > 0 && "No candidates for scavenging"); MachineBasicBlock::iterator ME = MBB->getFirstTerminator(); assert(StartMI != ME && "MI already at terminator"); MachineBasicBlock::iterator RestorePointMI = StartMI; MachineBasicBlock::iterator MI = StartMI; bool inVirtLiveRange = false; for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) { if (MI->isDebugValue()) { ++InstrLimit; // Don't count debug instructions continue; } bool isVirtKillInsn = false; bool isVirtDefInsn = false; // Remove any candidates touched by instruction. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (MO.isRegMask()) Candidates.clearBitsNotInMask(MO.getRegMask()); if (!MO.isReg() || MO.isUndef() || !MO.getReg()) continue; if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { if (MO.isDef()) isVirtDefInsn = true; else if (MO.isKill()) isVirtKillInsn = true; continue; } for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI) Candidates.reset(*AI); } // If we're not in a virtual reg's live range, this is a valid // restore point. if (!inVirtLiveRange) RestorePointMI = MI; // Update whether we're in the live range of a virtual register if (isVirtKillInsn) inVirtLiveRange = false; if (isVirtDefInsn) inVirtLiveRange = true; // Was our survivor untouched by this instruction? if (Candidates.test(Survivor)) continue; // All candidates gone? if (Candidates.none()) break; Survivor = Candidates.find_first(); } // If we ran off the end, that's where we want to restore. if (MI == ME) RestorePointMI = ME; assert (RestorePointMI != StartMI && "No available scavenger restore location!"); // We ran out of candidates, so stop the search. UseMI = RestorePointMI; return Survivor; }
bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) { bool Modified = false; SmallSet<unsigned, 4> Defs; SmallSet<unsigned, 4> Uses; MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); while (MBBI != E) { MachineInstr *MI = &*MBBI; DebugLoc dl = MI->getDebugLoc(); unsigned PredReg = 0; ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg); if (CC == ARMCC::AL) { ++MBBI; continue; } Defs.clear(); Uses.clear(); TrackDefUses(MI, Defs, Uses, TRI); // Insert an IT instruction. MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) .addImm(CC); // Add implicit use of ITSTATE to IT block instructions. MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, true/*isImp*/, false/*isKill*/)); MachineInstr *LastITMI = MI; MachineBasicBlock::iterator InsertPos = MIB; ++MBBI; // Form IT block. ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); unsigned Mask = 0, Pos = 3; // Branches, including tricky ones like LDM_RET, need to end an IT // block so check the instruction we just put in the block. for (; MBBI != E && Pos && (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { if (MBBI->isDebugValue()) continue; MachineInstr *NMI = &*MBBI; MI = NMI; unsigned NPredReg = 0; ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg); if (NCC == CC || NCC == OCC) { Mask |= (NCC & 1) << Pos; // Add implicit use of ITSTATE. NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, true/*isImp*/, false/*isKill*/)); LastITMI = NMI; } else { if (NCC == ARMCC::AL && MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { --MBBI; MBB.remove(NMI); MBB.insert(InsertPos, NMI); ++NumMovedInsts; continue; } break; } TrackDefUses(NMI, Defs, Uses, TRI); --Pos; } // Finalize IT mask. Mask |= (1 << Pos); // Tag along (firstcond[0] << 4) with the mask. Mask |= (CC & 1) << 4; MIB.addImm(Mask); // Last instruction in IT block kills ITSTATE. LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill(); Modified = true; ++NumITs; } return Modified; }
/// LowerPHINode - Lower the PHI node at the top of the specified block, /// void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt) { ++NumLowered; MachineBasicBlock::iterator AfterPHIsIt = llvm::next(LastPHIIt); // Unlink the PHI node from the basic block, but don't delete the PHI yet. MachineInstr *MPhi = MBB.remove(MBB.begin()); unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; unsigned DestReg = MPhi->getOperand(0).getReg(); assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); bool isDead = MPhi->getOperand(0).isDead(); // Create a new register for the incoming PHI arguments. MachineFunction &MF = *MBB.getParent(); unsigned IncomingReg = 0; bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI? // Insert a register to register copy at the top of the current block (but // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); if (isSourceDefinedByImplicitDef(MPhi, MRI)) // If all sources of a PHI node are implicit_def, just emit an // implicit_def instead of a copy. BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); else { // Can we reuse an earlier PHI node? This only happens for critical edges, // typically those created by tail duplication. unsigned &entry = LoweredPHIs[MPhi]; if (entry) { // An identical PHI node was already lowered. Reuse the incoming register. IncomingReg = entry; reusedIncoming = true; ++NumReused; DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); } else { const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); } BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), TII->get(TargetOpcode::COPY), DestReg) .addReg(IncomingReg); } // Update live variable information if there is any. if (LV) { MachineInstr *PHICopy = prior(AfterPHIsIt); if (IncomingReg) { LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg); // Increment use count of the newly created virtual register. LV->setPHIJoin(IncomingReg); // When we are reusing the incoming register, it may already have been // killed in this block. The old kill will also have been inserted at // AfterPHIsIt, so it appears before the current PHICopy. if (reusedIncoming) if (MachineInstr *OldKill = VI.findKill(&MBB)) { DEBUG(dbgs() << "Remove old kill from " << *OldKill); LV->removeVirtualRegisterKilled(IncomingReg, OldKill); DEBUG(MBB.dump()); } // Add information to LiveVariables to know that the incoming value is // killed. Note that because the value is defined in several places (once // each for each incoming block), the "def" block and instruction fields // for the VarInfo is not filled in. LV->addVirtualRegisterKilled(IncomingReg, PHICopy); } // Since we are going to be deleting the PHI node, if it is the last use of // any registers, or if the value itself is dead, we need to move this // information over to the new copy we just inserted. LV->removeVirtualRegistersKilled(MPhi); // If the result is dead, update LV. if (isDead) { LV->addVirtualRegisterDead(DestReg, PHICopy); LV->removeVirtualRegisterDead(DestReg, MPhi); } } // Update LiveIntervals for the new copy or implicit def. if (LIS) { MachineInstr *NewInstr = prior(AfterPHIsIt); SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr); SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB); if (IncomingReg) { // Add the region from the beginning of MBB to the copy instruction to // IncomingReg's live interval. LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg); VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex); if (!IncomingVNI) IncomingVNI = IncomingLI.getNextValue(MBBStartIndex, LIS->getVNInfoAllocator()); IncomingLI.addRange(LiveRange(MBBStartIndex, DestCopyIndex.getRegSlot(), IncomingVNI)); } LiveInterval &DestLI = LIS->getInterval(DestReg); assert(DestLI.begin() != DestLI.end() && "PHIs should have nonempty LiveIntervals."); if (DestLI.endIndex().isDead()) { // A dead PHI's live range begins and ends at the start of the MBB, but // the lowered copy, which will still be dead, needs to begin and end at // the copy instruction. VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex); assert(OrigDestVNI && "PHI destination should be live at block entry."); DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot()); DestLI.createDeadDef(DestCopyIndex.getRegSlot(), LIS->getVNInfoAllocator()); DestLI.removeValNo(OrigDestVNI); } else { // Otherwise, remove the region from the beginning of MBB to the copy // instruction from DestReg's live interval. DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot()); VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot()); assert(DestVNI && "PHI destination should be live at its definition."); DestVNI->def = DestCopyIndex.getRegSlot(); } } // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(), MPhi->getOperand(i).getReg())]; // Now loop over all of the incoming arguments, changing them to copy into the // IncomingReg register in the corresponding predecessor basic block. SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; for (int i = NumSrcs - 1; i >= 0; --i) { unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() || isImplicitlyDefined(SrcReg, MRI); assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && "Machine PHI Operands must all be virtual registers!"); // Get the MachineBasicBlock equivalent of the BasicBlock that is the source // path the PHI. MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); // Check to make sure we haven't already emitted the copy for this block. // This can happen because PHI nodes may have multiple entries for the same // basic block. if (!MBBsInsertedInto.insert(&opBlock)) continue; // If the copy has already been emitted, we're done. // Find a safe location to insert the copy, this may be the first terminator // in the block (or end()). MachineBasicBlock::iterator InsertPos = findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); // Insert the copy. MachineInstr *NewSrcInstr = 0; if (!reusedIncoming && IncomingReg) { if (SrcUndef) { // The source register is undefined, so there is no need for a real // COPY, but we still need to ensure joint dominance by defs. // Insert an IMPLICIT_DEF instruction. NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF), IncomingReg); // Clean up the old implicit-def, if there even was one. if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) if (DefMI->isImplicitDef()) ImpDefs.insert(DefMI); } else { NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), TII->get(TargetOpcode::COPY), IncomingReg) .addReg(SrcReg, 0, SrcSubReg); } } // We only need to update the LiveVariables kill of SrcReg if this was the // last PHI use of SrcReg to be lowered on this CFG edge and it is not live // out of the predecessor. We can also ignore undef sources. if (LV && !SrcUndef && !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && !LV->isLiveOut(SrcReg, opBlock)) { // We want to be able to insert a kill of the register if this PHI (aka, // the copy we just inserted) is the last use of the source value. Live // variable analysis conservatively handles this by saying that the value // is live until the end of the block the PHI entry lives in. If the value // really is dead at the PHI copy, there will be no successor blocks which // have the value live-in. // Okay, if we now know that the value is not live out of the block, we // can add a kill marker in this block saying that it kills the incoming // value! // In our final twist, we have to decide which instruction kills the // register. In most cases this is the copy, however, terminator // instructions at the end of the block may also use the value. In this // case, we should mark the last such terminator as being the killing // block, not the copy. MachineBasicBlock::iterator KillInst = opBlock.end(); MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); for (MachineBasicBlock::iterator Term = FirstTerm; Term != opBlock.end(); ++Term) { if (Term->readsRegister(SrcReg)) KillInst = Term; } if (KillInst == opBlock.end()) { // No terminator uses the register. if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't insert a copy this time. KillInst = FirstTerm; while (KillInst != opBlock.begin()) { --KillInst; if (KillInst->isDebugValue()) continue; if (KillInst->readsRegister(SrcReg)) break; } } else { // We just inserted this copy. KillInst = prior(InsertPos); } } assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); // Finally, mark it killed. LV->addVirtualRegisterKilled(SrcReg, KillInst); // This vreg no longer lives all of the way through opBlock. unsigned opBlockNum = opBlock.getNumber(); LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); } if (LIS) { if (NewSrcInstr) { LIS->InsertMachineInstrInMaps(NewSrcInstr); LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr); } if (!SrcUndef && !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) { LiveInterval &SrcLI = LIS->getInterval(SrcReg); bool isLiveOut = false; for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), SE = opBlock.succ_end(); SI != SE; ++SI) { SlotIndex startIdx = LIS->getMBBStartIdx(*SI); VNInfo *VNI = SrcLI.getVNInfoAt(startIdx); // Definitions by other PHIs are not truly live-in for our purposes. if (VNI && VNI->def != startIdx) { isLiveOut = true; break; } } if (!isLiveOut) { MachineBasicBlock::iterator KillInst = opBlock.end(); MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); for (MachineBasicBlock::iterator Term = FirstTerm; Term != opBlock.end(); ++Term) { if (Term->readsRegister(SrcReg)) KillInst = Term; } if (KillInst == opBlock.end()) { // No terminator uses the register. if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't just insert a copy. KillInst = FirstTerm; while (KillInst != opBlock.begin()) { --KillInst; if (KillInst->isDebugValue()) continue; if (KillInst->readsRegister(SrcReg)) break; } } else { // We just inserted this copy. KillInst = prior(InsertPos); } } assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst); SrcLI.removeRange(LastUseIndex.getRegSlot(), LIS->getMBBEndIdx(&opBlock)); } } } } // Really delete the PHI instruction now, if it is not in the LoweredPHIs map. if (reusedIncoming || !IncomingReg) { if (LIS) LIS->RemoveMachineInstrFromMaps(MPhi); MF.DeleteMachineInstr(MPhi); } }
// AnalyzeBranch returns a Boolean value and takes four parameters: // MachineBasicBlock &MBB — The incoming block to be examined. // MachineBasicBlock *&TBB — A destination block that is returned. For // a conditional branch that evaluates to true, TBB is the destination. // MachineBasicBlock *&FBB — For a conditional branch that evaluates to // false, FBB is returned as the destination. // std::vector<MachineOperand> &Cond — List of operands to evaluate a // condition for a conditional branch. // Return false if the branch is sucessfully analyzed, true otherwise. // // Note that Cond appears to be only used by the target specific code. The // generic code just checks if Cond is empty or not. bool LM32InstrInfo:: AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { // The Cond parameters need to be fixed - disable this for now. return true; DEBUG(dbgs() << "AnalyzeBranch: blocks:\n"); DEBUG(MBB.dump()); DEBUG(dbgs() << "AnalyzeBranch: end blocks:\n"); // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin()) return false; --I; while (I->isDebugValue()) { if (I == MBB.begin()) return false; --I; } if (!isUnpredicatedTerminator(I)) { DEBUG(dbgs() << "AnalyzeBranch:predicated Terminator\n"); DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n"); return false; } // Get the last instruction in the block. MachineInstr *LastInst = I; // If there is only one terminator instruction, process it. unsigned LastOpc = LastInst->getOpcode(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { if (LM32::isUncondBranchOpcode(LastOpc)) { DEBUG(dbgs() << "AnalyzeBranch:one terminator instruction\n"); TBB = LastInst->getOperand(0).getMBB(); DEBUG(dbgs() << "AnalyzeBranch: instruction: " << *LastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: opcode: " << LastInst->getOpcode() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB->getName().str() << "\n"); return false; } if (LM32::isCondBranchOpcode(LastOpc)) { // Block ends with fall-through condbranch. DEBUG(dbgs() << "AnalyzeBranch:Block ends with fall-through condbranch\n"); DEBUG(dbgs() << "AnalyzeBranch: instruction: " << *LastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: opcode: " << LastOpc << "\n"); DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n"); TBB = GetBranchTarget(*LastInst); Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); Cond.push_back(LastInst->getOperand(0)); DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB->getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: Cond[0]:" << Cond[0] << "\n"); DEBUG(dbgs() << "AnalyzeBranch: Cond[1]:" << Cond[1] << "\n"); return false; } // Otherwise, don't know what this is. return true; } // Get the instruction before it if it's a terminator. MachineInstr *SecondLastInst = I; // If there are three terminators, we don't know what sort of block this is. if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) return true; // The block ends with both a conditional branch and an ensuing // unconditional branch. if (LM32::isCondBranchOpcode(SecondLastInst->getOpcode()) && LM32::isUncondBranchOpcode(LastInst->getOpcode())) { DEBUG(dbgs() << "AnalyzeBranch:Conditional branch and ensuing unconditional\n"); TBB = GetBranchTarget(*SecondLastInst); Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); Cond.push_back(SecondLastInst->getOperand(0)); FBB = GetBranchTarget(*LastInst); DEBUG(dbgs() << "AnalyzeBranch: 2nd instr: " << *SecondLastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: last instr: " << *LastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: 2nd opcode: " << SecondLastInst->getOpcode() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: last opcode: " << LastInst->getOpcode() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB->getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: FBB: " << FBB->getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: Cond[0]:" << Cond[0] << "\n"); DEBUG(dbgs() << "AnalyzeBranch: Cond[1]:" << Cond[1] << "\n"); return false; } // If the block ends with two unconditional branches, handle it. // The second one is not executed, so remove it. if (LM32::isUncondBranchOpcode(SecondLastInst->getOpcode()) && LM32::isUncondBranchOpcode(LastInst->getOpcode())) { TBB = GetBranchTarget(*SecondLastInst); I = LastInst; if (AllowModify) I->eraseFromParent(); DEBUG(dbgs() << "AnalyzeBranch:two unconditional branches\n"); DEBUG(dbgs() << "AnalyzeBranch: instruction: " << *LastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: 2nd instr: " << *SecondLastInst << "\n"); DEBUG(dbgs() << "AnalyzeBranch: opcode: " << LastInst->getOpcode() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: 2nd opcode: " << SecondLastInst->getOpcode() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB->getName().str() << "\n"); return false; } // Otherwise, can't handle this. return true; }
/// shouldTailDuplicate - Determine if it is profitable to duplicate this block. bool TailDuplicatePass::shouldTailDuplicate(const MachineFunction &MF, bool IsSimple, MachineBasicBlock &TailBB) { // Only duplicate blocks that end with unconditional branches. if (TailBB.canFallThrough()) return false; // Don't try to tail-duplicate single-block loops. if (TailBB.isSuccessor(&TailBB)) return false; // Set the limit on the cost to duplicate. When optimizing for size, // duplicate only one, because one branch instruction can be eliminated to // compensate for the duplication. unsigned MaxDuplicateCount; if (TailDuplicateSize.getNumOccurrences() == 0 && MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize)) MaxDuplicateCount = 1; else MaxDuplicateCount = TailDuplicateSize; // If the target has hardware branch prediction that can handle indirect // branches, duplicating them can often make them predictable when there // are common paths through the code. The limit needs to be high enough // to allow undoing the effects of tail merging and other optimizations // that rearrange the predecessors of the indirect branch. bool HasIndirectbr = false; if (!TailBB.empty()) HasIndirectbr = TailBB.back().isIndirectBranch(); if (HasIndirectbr && PreRegAlloc) MaxDuplicateCount = 20; // Check the instructions in the block to determine whether tail-duplication // is invalid or unlikely to be profitable. unsigned InstrCount = 0; for (MachineBasicBlock::iterator I = TailBB.begin(); I != TailBB.end(); ++I) { // Non-duplicable things shouldn't be tail-duplicated. if (I->isNotDuplicable()) return false; // Do not duplicate 'return' instructions if this is a pre-regalloc run. // A return may expand into a lot more instructions (e.g. reload of callee // saved registers) after PEI. if (PreRegAlloc && I->isReturn()) return false; // Avoid duplicating calls before register allocation. Calls presents a // barrier to register allocation so duplicating them may end up increasing // spills. if (PreRegAlloc && I->isCall()) return false; if (!I->isPHI() && !I->isDebugValue()) InstrCount += 1; if (InstrCount > MaxDuplicateCount) return false; } if (HasIndirectbr && PreRegAlloc) return true; if (IsSimple) return true; if (!PreRegAlloc) return true; return canCompletelyDuplicateBB(TailBB); }
/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, /// under the assuption that it needs to be lowered in a way that supports /// atomic execution of PHIs. This lowering method is always correct all of the /// time. /// void PHIElimination::LowerAtomicPHINode( MachineBasicBlock &MBB, MachineBasicBlock::iterator AfterPHIsIt) { ++NumAtomic; // Unlink the PHI node from the basic block, but don't delete the PHI yet. MachineInstr *MPhi = MBB.remove(MBB.begin()); unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; unsigned DestReg = MPhi->getOperand(0).getReg(); assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); bool isDead = MPhi->getOperand(0).isDead(); // Create a new register for the incoming PHI arguments. MachineFunction &MF = *MBB.getParent(); unsigned IncomingReg = 0; bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI? // Insert a register to register copy at the top of the current block (but // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); if (isSourceDefinedByImplicitDef(MPhi, MRI)) // If all sources of a PHI node are implicit_def, just emit an // implicit_def instead of a copy. BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); else { // Can we reuse an earlier PHI node? This only happens for critical edges, // typically those created by tail duplication. unsigned &entry = LoweredPHIs[MPhi]; if (entry) { // An identical PHI node was already lowered. Reuse the incoming register. IncomingReg = entry; reusedIncoming = true; ++NumReused; DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); } else { const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); } BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), TII->get(TargetOpcode::COPY), DestReg) .addReg(IncomingReg); } // Update live variable information if there is any. LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>(); if (LV) { MachineInstr *PHICopy = prior(AfterPHIsIt); if (IncomingReg) { LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg); // Increment use count of the newly created virtual register. VI.NumUses++; LV->setPHIJoin(IncomingReg); // When we are reusing the incoming register, it may already have been // killed in this block. The old kill will also have been inserted at // AfterPHIsIt, so it appears before the current PHICopy. if (reusedIncoming) if (MachineInstr *OldKill = VI.findKill(&MBB)) { DEBUG(dbgs() << "Remove old kill from " << *OldKill); LV->removeVirtualRegisterKilled(IncomingReg, OldKill); DEBUG(MBB.dump()); } // Add information to LiveVariables to know that the incoming value is // killed. Note that because the value is defined in several places (once // each for each incoming block), the "def" block and instruction fields // for the VarInfo is not filled in. LV->addVirtualRegisterKilled(IncomingReg, PHICopy); } // Since we are going to be deleting the PHI node, if it is the last use of // any registers, or if the value itself is dead, we need to move this // information over to the new copy we just inserted. LV->removeVirtualRegistersKilled(MPhi); // If the result is dead, update LV. if (isDead) { LV->addVirtualRegisterDead(DestReg, PHICopy); LV->removeVirtualRegisterDead(DestReg, MPhi); } } // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(), MPhi->getOperand(i).getReg())]; // Now loop over all of the incoming arguments, changing them to copy into the // IncomingReg register in the corresponding predecessor basic block. SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; for (int i = NumSrcs - 1; i >= 0; --i) { unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && "Machine PHI Operands must all be virtual registers!"); // Get the MachineBasicBlock equivalent of the BasicBlock that is the source // path the PHI. MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); // If source is defined by an implicit def, there is no need to insert a // copy. MachineInstr *DefMI = MRI->getVRegDef(SrcReg); if (DefMI->isImplicitDef()) { ImpDefs.insert(DefMI); continue; } // Check to make sure we haven't already emitted the copy for this block. // This can happen because PHI nodes may have multiple entries for the same // basic block. if (!MBBsInsertedInto.insert(&opBlock)) continue; // If the copy has already been emitted, we're done. // Find a safe location to insert the copy, this may be the first terminator // in the block (or end()). MachineBasicBlock::iterator InsertPos = findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); // Insert the copy. if (!reusedIncoming && IncomingReg) BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg); // Now update live variable information if we have it. Otherwise we're done if (!LV) continue; // We want to be able to insert a kill of the register if this PHI (aka, the // copy we just inserted) is the last use of the source value. Live // variable analysis conservatively handles this by saying that the value is // live until the end of the block the PHI entry lives in. If the value // really is dead at the PHI copy, there will be no successor blocks which // have the value live-in. // Also check to see if this register is in use by another PHI node which // has not yet been eliminated. If so, it will be killed at an appropriate // point later. // Is it used by any PHI instructions in this block? bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]; // Okay, if we now know that the value is not live out of the block, we can // add a kill marker in this block saying that it kills the incoming value! if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) { // In our final twist, we have to decide which instruction kills the // register. In most cases this is the copy, however, the first // terminator instruction at the end of the block may also use the value. // In this case, we should mark *it* as being the killing block, not the // copy. MachineBasicBlock::iterator KillInst; MachineBasicBlock::iterator Term = opBlock.getFirstTerminator(); if (Term != opBlock.end() && Term->readsRegister(SrcReg)) { KillInst = Term; // Check that no other terminators use values. #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { if (TI->isDebugValue()) continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); } #endif } else if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't insert a copy this time. KillInst = Term; while (KillInst != opBlock.begin()) { --KillInst; if (KillInst->isDebugValue()) continue; if (KillInst->readsRegister(SrcReg)) break; } } else { // We just inserted this copy. KillInst = prior(InsertPos); } assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); // Finally, mark it killed. LV->addVirtualRegisterKilled(SrcReg, KillInst); // This vreg no longer lives all of the way through opBlock. unsigned opBlockNum = opBlock.getNumber(); LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); } } // Really delete the PHI instruction now, if it is not in the LoweredPHIs map. if (reusedIncoming || !IncomingReg) MF.DeleteMachineInstr(MPhi); }
// The AnalyzeBranch function is used to examine conditional instructions and // remove unnecessary instructions. This method is used by BranchFolder and // IfConverter machine function passes to improve the CFG. // - TrueBlock is set to the destination if condition evaluates true (it is the // nullptr if the destination is the fall-through branch); // - FalseBlock is set to the destination if condition evaluates to false (it // is the nullptr if the branch is unconditional); // - condition is populated with machine operands needed to generate the branch // to insert in InsertBranch; // Returns: false if branch could successfully be analyzed. bool LanaiInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl<MachineOperand> &Condition, bool AllowModify) const { // Iterator to current instruction being considered. MachineBasicBlock::iterator Instruction = MBB.end(); // Start from the bottom of the block and work up, examining the // terminator instructions. while (Instruction != MBB.begin()) { --Instruction; // Skip over debug values. if (Instruction->isDebugValue()) continue; // Working from the bottom, when we see a non-terminator // instruction, we're done. if (!isUnpredicatedTerminator(*Instruction)) break; // A terminator that isn't a branch can't easily be handled // by this analysis. if (!Instruction->isBranch()) return true; // Handle unconditional branches. if (Instruction->getOpcode() == Lanai::BT) { if (!AllowModify) { TrueBlock = Instruction->getOperand(0).getMBB(); continue; } // If the block has any instructions after a branch, delete them. while (std::next(Instruction) != MBB.end()) { std::next(Instruction)->eraseFromParent(); } Condition.clear(); FalseBlock = nullptr; // Delete the jump if it's equivalent to a fall-through. if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) { TrueBlock = nullptr; Instruction->eraseFromParent(); Instruction = MBB.end(); continue; } // TrueBlock is used to indicate the unconditional destination. TrueBlock = Instruction->getOperand(0).getMBB(); continue; } // Handle conditional branches unsigned Opcode = Instruction->getOpcode(); if (Opcode != Lanai::BRCC) return true; // Unknown opcode. // Multiple conditional branches are not handled here so only proceed if // there are no conditions enqueued. if (Condition.empty()) { LPCC::CondCode BranchCond = static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm()); // TrueBlock is the target of the previously seen unconditional branch. FalseBlock = TrueBlock; TrueBlock = Instruction->getOperand(0).getMBB(); Condition.push_back(MachineOperand::CreateImm(BranchCond)); continue; } // Multiple conditional branches are not handled. return true; } // Return false indicating branch successfully analyzed. return false; }
bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { // Start from the bottom of the block and work up, examining the // terminator instructions. MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; if (I->isDebugValue()) continue; // Working from the bottom, when we see a non-terminator // instruction, we're done. if (!isUnpredicatedTerminator(I)) break; // A terminator that isn't a branch can't easily be handled // by this analysis. if (!I->isBranch()) return true; // Cannot handle indirect branches. if (I->getOpcode() == MSP430::Br || I->getOpcode() == MSP430::Bm) return true; // Handle unconditional branches. if (I->getOpcode() == MSP430::JMP) { if (!AllowModify) { TBB = I->getOperand(0).getMBB(); continue; } // If the block has any instructions after a JMP, delete them. while (std::next(I) != MBB.end()) std::next(I)->eraseFromParent(); Cond.clear(); FBB = nullptr; // Delete the JMP if it's equivalent to a fall-through. if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { TBB = nullptr; I->eraseFromParent(); I = MBB.end(); continue; } // TBB is used to indicate the unconditinal destination. TBB = I->getOperand(0).getMBB(); continue; } // Handle conditional branches. assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); MSP430CC::CondCodes BranchCode = static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); if (BranchCode == MSP430CC::COND_INVALID) return true; // Can't handle weird stuff. // Working from the bottom, handle the first conditional branch. if (Cond.empty()) { FBB = TBB; TBB = I->getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(BranchCode)); continue; } // Handle subsequent conditional branches. Only handle the case where all // conditional branches branch to the same destination. assert(Cond.size() == 1); assert(TBB); // Only handle the case where all conditional branches branch to // the same destination. if (TBB != I->getOperand(0).getMBB()) return true; MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); // If the conditions are the same, we can leave them alone. if (OldBranchCode == BranchCode) continue; return true; } return false; }
/// canSpeculateInstrs - Returns true if all the instructions in MBB can safely /// be speculated. The terminators are not considered. /// /// If instructions use any values that are defined in the head basic block, /// the defining instructions are added to InsertAfter. /// /// Any clobbered regunits are added to ClobberedRegUnits. /// bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to // get right. if (!MBB->livein_empty()) { DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n"); return false; } unsigned InstrCount = 0; // Check all instructions, except the terminators. It is assumed that // terminators never have side effects or define any used register values. for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->getFirstTerminator(); I != E; ++I) { if (I->isDebugValue()) continue; if (++InstrCount > BlockInstrLimit && !Stress) { DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than " << BlockInstrLimit << " instructions.\n"); return false; } // There shouldn't normally be any phis in a single-predecessor block. if (I->isPHI()) { DEBUG(dbgs() << "Can't hoist: " << *I); return false; } // Don't speculate loads. Note that it may be possible and desirable to // speculate GOT or constant pool loads that are guaranteed not to trap, // but we don't support that for now. if (I->mayLoad()) { DEBUG(dbgs() << "Won't speculate load: " << *I); return false; } // We never speculate stores, so an AA pointer isn't necessary. bool DontMoveAcrossStore = true; if (!I->isSafeToMove(nullptr, DontMoveAcrossStore)) { DEBUG(dbgs() << "Can't speculate: " << *I); return false; } // Check for any dependencies on Head instructions. for (MIOperands MO(I); MO.isValid(); ++MO) { if (MO->isRegMask()) { DEBUG(dbgs() << "Won't speculate regmask: " << *I); return false; } if (!MO->isReg()) continue; unsigned Reg = MO->getReg(); // Remember clobbered regunits. if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg)) for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) ClobberedRegUnits.set(*Units); if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg)) continue; MachineInstr *DefMI = MRI->getVRegDef(Reg); if (!DefMI || DefMI->getParent() != Head) continue; if (InsertAfter.insert(DefMI).second) DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); if (DefMI->isTerminator()) { DEBUG(dbgs() << "Can't insert instructions below terminator.\n"); return false; } } } return true; }
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin()) return false; --I; while (I->isDebugValue()) { if (I == MBB.begin()) return false; --I; } if (!isUnpredicatedTerminator(I)) return false; // Get the last instruction in the block. MachineInstr *LastInst = I; // If there is only one terminator instruction, process it. unsigned LastOpc = LastInst->getOpcode(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { if (!LastInst->getDesc().isBranch()) return true; // Unconditional branch if (LastOpc == Mips::J) { TBB = LastInst->getOperand(0).getMBB(); return false; } Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); if (BranchCode == Mips::COND_INVALID) return true; // Can't handle indirect branch. // Conditional branch // Block ends with fall-through condbranch. if (LastOpc != Mips::COND_INVALID) { int LastNumOp = LastInst->getNumOperands(); TBB = LastInst->getOperand(LastNumOp-1).getMBB(); Cond.push_back(MachineOperand::CreateImm(BranchCode)); for (int i=0; i<LastNumOp-1; i++) { Cond.push_back(LastInst->getOperand(i)); } return false; } } // Get the instruction before it if it is a terminator. MachineInstr *SecondLastInst = I; // If there are three terminators, we don't know what sort of block this is. if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) return true; // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it. unsigned SecondLastOpc = SecondLastInst->getOpcode(); Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) { int SecondNumOp = SecondLastInst->getNumOperands(); TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB(); Cond.push_back(MachineOperand::CreateImm(BranchCode)); for (int i=0; i<SecondNumOp-1; i++) { Cond.push_back(SecondLastInst->getOperand(i)); } FBB = LastInst->getOperand(0).getMBB(); return false; } // If the block ends with two unconditional branches, handle it. The last // one is not executed, so remove it. if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) { TBB = SecondLastInst->getOperand(0).getMBB(); I = LastInst; if (AllowModify) I->eraseFromParent(); return false; } // Otherwise, can't handle this. return true; }