Pipelined-VLIW-MIPS-processor

The implementation includes my own (fully working) design of a multilevel adaptive branch predictor as well. The final processor can be found under the "assignment 2" folder.

Name		Name	Last commit message	Last commit date
Latest commit History 98 Commits
PLProcessor		PLProcessor
assignment2		assignment2
driver		driver
exercise1_mux_work		exercise1_mux_work
exersise1		exersise1
exersise2		exersise2
exersise2experiment		exersise2experiment
exersise2experiment2		exersise2experiment2
exersise2experiment3		exersise2experiment3
exersise2failed		exersise2failed
exersise2version1		exersise2version1
hardware		hardware
ALUop.vhd		ALUop.vhd
FPGA_TB.png		FPGA_TB.png
FPGA_TB_EXPECTED.png		FPGA_TB_EXPECTED.png
PC		PC
PC.vhd		PC.vhd
README.md		README.md
Vliw_alu.vhd		Vliw_alu.vhd
alu.vhd		alu.vhd
alu_control.vhd		alu_control.vhd
branchpredictiontb.png		branchpredictiontb.png
branchpredictor.png		branchpredictor.png
branchpredmappingrelations.png		branchpredmappingrelations.png
control.vhd		control.vhd
control.vhdPreview		control.vhdPreview
controlcirtest.vhd		controlcirtest.vhd
controlpath.vhd		controlpath.vhd
controltest.vhd		controltest.vhd
criticalpath.png		criticalpath.png
dualportram.png		dualportram.png
fail.vhd		fail.vhd
flow chart predictor algorithm.png		flow chart predictor algorithm.png
konst.vhd		konst.vhd
mux.vhd		mux.vhd
predictor2.png		predictor2.png
processor.vhd		processor.vhd
registertest.vhd		registertest.vhd
tbmultiply.png		tbmultiply.png
testcontrol.vhd		testcontrol.vhd
testcounter.vhd		testcounter.vhd
topschematic.png		topschematic.png

eiriklf/Pipelined-VLIW-MIPS-processor

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