Cycle accurate co-simulation model of a reconfigurable CPU
License
plessl/zippy
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
Name | Name | Last commit message | Last commit date | |
---|---|---|---|---|
Repository files navigation
Zippy is a detailed simulation model for a reconfigurable CPU architecture that has been developed in the Zippy Research Project at ETH Zurich. Zippy consists of a CPU that is interfaced to a coarse-grained, dynamically reconfigurable array. The CPU is simulated with the SimpleScalar CPU simulator, the reconfigurable array is specified as cycle accurate VHDL model. These models are integrated with a co-simulation environment into a cycle-accurate, system-level co-simulation framework.
About
Cycle accurate co-simulation model of a reconfigurable CPU
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published