Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
FPGA		FPGA
ipcore_dir		ipcore_dir
isim		isim
planAhead_run_1		planAhead_run_1
planAhead_run_2		planAhead_run_2
.gitignore		.gitignore
ALU.v		ALU.v
BCDto7Seg.v		BCDto7Seg.v
Constraints.ucf		Constraints.ucf
ControlUnit.v		ControlUnit.v
DIP_Driver.v		DIP_Driver.v
DIP_TO_LED.v		DIP_TO_LED.v
Debouncer.v		Debouncer.v
Debouncer_tb.v		Debouncer_tb.v
FPGA.xise		FPGA.xise
JCController.v		JCController.v
Key_Driver.v		Key_Driver.v
LED_Driver.spl		LED_Driver.spl
LED_Driver.sym		LED_Driver.sym
LED_Driver.tfi		LED_Driver.tfi
LED_Driver.v		LED_Driver.v
OneOneOhOneDetector.v		OneOneOhOneDetector.v
PISO.v		PISO.v
Processor.v		Processor.v
README.md		README.md
RegisterBank.v		RegisterBank.v
SEG_Driver.v		SEG_Driver.v
SIPO.v		SIPO.v
Sbu_Computer_Report.docx		Sbu_Computer_Report.docx
Sbu_Computer_Report.pdf		Sbu_Computer_Report.pdf
SevenSeg_Driver.v		SevenSeg_Driver.v
SevenSegment_Driver.v		SevenSegment_Driver.v
ToBCD_isim_beh.exe		ToBCD_isim_beh.exe
ToBCD_isim_beh1.wdb		ToBCD_isim_beh1.wdb
ToSeg.v		ToSeg.v
TopModule.spl		TopModule.spl
TopModule.sym		TopModule.sym
TopModule.v		TopModule.v
TopModule.xdl		TopModule.xdl
TopModule_isim_beh.exe		TopModule_isim_beh.exe
TopModule_isim_beh.wdb		TopModule_isim_beh.wdb
_impact.cmd		_impact.cmd
_impact.log		_impact.log
auto_project.ipf		auto_project.ipf
auto_project_1.ipf		auto_project_1.ipf
datapath.pdf		datapath.pdf
datapath.png		datapath.png
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
pa.fromNcd.tcl		pa.fromNcd.tcl
planAhead.ngc2edif.log		planAhead.ngc2edif.log
planAhead_pid600.debug		planAhead_pid600.debug
shahid_beheshti_university.jpg		shahid_beheshti_university.jpg
toBCD.v		toBCD.v
toBCD.vhd		toBCD.vhd
xilinxsim.ini		xilinxsim.ini

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SBU Processor

A 32-bit RISC processor based on Harvard architecture.

tahaeghtesad/FPGA

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SBU Processor

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