GitHub - naiding/MIPS: MIPS CPU by verilog and ISE

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
_xmsgs		_xmsgs
ipcore_dir		ipcore_dir
iseconfig		iseconfig
isim		isim
MIPSCPU.gise		MIPSCPU.gise
MIPSCPU.xise		MIPSCPU.xise
U201313768.coe		U201313768.coe
U201313768.txt		U201313768.txt
alu.v		alu.v
aluctr.v		aluctr.v
aluctrsim.v		aluctrsim.v
aluctrsim_isim_beh.exe		aluctrsim_isim_beh.exe
aluctrsim_stx_beh.prj		aluctrsim_stx_beh.prj
alusim.v		alusim.v
alusim_isim_beh.exe		alusim_isim_beh.exe
alusim_stx_beh.prj		alusim_stx_beh.prj
ctr.v		ctr.v
ctrsim.v		ctrsim.v
ctrsim_isim_beh.exe		ctrsim_isim_beh.exe
ctrsim_isim_beh.wdb		ctrsim_isim_beh.wdb
ctrsim_stx_beh.prj		ctrsim_stx_beh.prj
dist_mem_gen_v7_2.mif		dist_mem_gen_v7_2.mif
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
irom.mif		irom.mif
isim.cmd		isim.cmd
isim.log		isim.log
readme.txt		readme.txt
regFile.v		regFile.v
regFile_stx_beh.prj		regFile_stx_beh.prj
regsim.v		regsim.v
regsim_beh.prj		regsim_beh.prj
regsim_isim_beh.exe		regsim_isim_beh.exe
regsim_isim_beh1.wdb		regsim_isim_beh1.wdb
regsim_stx_beh.prj		regsim_stx_beh.prj
signext.v		signext.v
signext_summary.html		signext_summary.html
test.coe		test.coe
top.v		top.v
top_isim_beh.exe		top_isim_beh.exe
top_stx_beh.prj		top_stx_beh.prj
top_summary.html		top_summary.html
topsim.v		topsim.v
topsim_beh.prj		topsim_beh.prj
topsim_isim_beh.exe		topsim_isim_beh.exe
topsim_stx_beh.prj		topsim_stx_beh.prj
xilinxsim.ini		xilinxsim.ini