static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) { struct mct_clock_event_device *mevt; unsigned int cpu = smp_processor_id(); mevt = this_cpu_ptr(&percpu_mct_tick); mevt->evt = evt; mevt->base = EXYNOS4_MCT_L_BASE(cpu); sprintf(mevt->name, "mct_tick%d", cpu); evt->name = mevt->name; evt->cpumask = cpumask_of(cpu); evt->set_next_event = exynos4_tick_set_next_event; evt->set_mode = exynos4_tick_set_mode; evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; evt->rating = 450; clockevents_calc_mult_shift(evt, clk_rate / 2, 5); evt->max_delta_ns = clockevent_delta2ns(0x7fffffff, evt); evt->min_delta_ns = clockevent_delta2ns(0xf, evt); clockevents_register_device(evt); exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET); if (mct_int_type == MCT_INT_SPI) { if (cpu == 0) { mct_tick0_event_irq.dev_id = mevt; evt->irq = IRQ_MCT_L0; setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); } else { mct_tick1_event_irq.dev_id = mevt; evt->irq = IRQ_MCT_L1; setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); } } else { enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0); } return 0; }
static void exynos4_mct_write(unsigned int value, void *addr) { void __iomem *stat_addr; u32 mask; u32 i; __raw_writel(value, addr); if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) { u32 base = (u32) addr & EXYNOS4_MCT_L_MASK; switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) { case (u32) MCT_L_TCON_OFFSET: stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 3; /* L_TCON write status */ break; case (u32) MCT_L_ICNTB_OFFSET: stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 1; /* L_ICNTB write status */ break; case (u32) MCT_L_TCNTB_OFFSET: stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 0; /* L_TCNTB write status */ break; default: return; } } else { switch ((u32) addr) { case (u32) EXYNOS4_MCT_G_TCON: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 16; /* G_TCON write status */ break; case (u32) EXYNOS4_MCT_G_COMP0_L: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 0; /* G_COMP0_L write status */ break; case (u32) EXYNOS4_MCT_G_COMP0_U: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 1; /* G_COMP0_U write status */ break; case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 2; /* G_COMP0_ADD_INCR write status */ break; case (u32) EXYNOS4_MCT_G_CNT_L: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 0; /* G_CNT_L write status */ break; case (u32) EXYNOS4_MCT_G_CNT_U: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 1; /* G_CNT_U write status */ break; default: return; } } /* Wait until written values are applied */ for (i = 0; i < 0x1000; i++) if (__raw_readl(stat_addr) & mask) { __raw_writel(mask, stat_addr); return; } panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr); }