fapi2::ReturnCode p9_chiplet_fabric_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { fapi2::ReturnCode l_rc; char l_procTargetStr[fapi2::MAX_ECMD_STRING_LEN]; char l_chipletTargetStr[fapi2::MAX_ECMD_STRING_LEN]; fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; std::vector<fapi2::Target<fapi2::TARGET_TYPE_XBUS>> l_xbus_chiplets; std::vector<fapi2::Target<fapi2::TARGET_TYPE_OBUS>> l_obus_chiplets; fapi2::ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE_Type l_fbc_optics_cfg_mode = { fapi2::ENUM_ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE_SMP }; FAPI_DBG("Start"); // Get proc target string fapi2::toString(i_target, l_procTargetStr, sizeof(l_procTargetStr)); // apply FBC non-hotplug initfile FAPI_DBG("Invoking p9.fbc.no_hp.scom.initfile on target %s...", l_procTargetStr); FAPI_EXEC_HWP(l_rc, p9_fbc_no_hp_scom, i_target, FAPI_SYSTEM); if (l_rc) { FAPI_ERR("Error from p9_fbc_no_hp_scom"); fapi2::current_err = l_rc; goto fapi_try_exit; } // setup IOE (XBUS FBC IO) TL SCOMs FAPI_DBG("Invoking p9.fbc.ioe_tl.scom.initfile on target %s...", l_procTargetStr); FAPI_EXEC_HWP(l_rc, p9_fbc_ioe_tl_scom, i_target, FAPI_SYSTEM); if (l_rc) { FAPI_ERR("Error from p9_fbc_ioe_tl_scom"); fapi2::current_err = l_rc; goto fapi_try_exit; } l_xbus_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_XBUS>(); if (l_xbus_chiplets.size()) { FAPI_TRY(fapi2::putScom(i_target, PU_PB_IOE_FIR_ACTION0_REG, FBC_IOE_TL_FIR_ACTION0), "Error from putScom (PU_PB_IOE_FIR_ACTION0_REG)"); FAPI_TRY(fapi2::putScom(i_target, PU_PB_IOE_FIR_ACTION1_REG, FBC_IOE_TL_FIR_ACTION1), "Error from putScom (PU_PB_IOE_FIR_ACTION1_REG)"); FAPI_TRY(fapi2::putScom(i_target, PU_PB_IOE_FIR_MASK_REG, FBC_IOE_TL_FIR_MASK), "Error from putScom (PU_PB_IOE_FIR_MASK_REG)"); } // setup IOE (XBUS FBC IO) DL SCOMs for (auto l_iter = l_xbus_chiplets.begin(); l_iter != l_xbus_chiplets.end(); l_iter++) { fapi2::toString(*l_iter, l_chipletTargetStr, sizeof(l_chipletTargetStr)); FAPI_DBG("Invoking p9.fbc.ioe_dl.scom.initfile on target %s...", l_chipletTargetStr); FAPI_EXEC_HWP(l_rc, p9_fbc_ioe_dl_scom, *l_iter, i_target); if (l_rc) { FAPI_ERR("Error from p9_fbc_ioe_dl_scom"); fapi2::current_err = l_rc; goto fapi_try_exit; } // configure action registers & unmask FAPI_TRY(fapi2::putScom(*l_iter, XBUS_LL0_IOEL_FIR_ACTION0_REG, FBC_IOE_DL_FIR_ACTION0), "Error from putScom (XBUS_LL0_IOEL_FIR_ACTION0_REG)"); FAPI_TRY(fapi2::putScom(*l_iter, XBUS_LL0_IOEL_FIR_ACTION1_REG, FBC_IOE_DL_FIR_ACTION1), "Error from putScom (XBUS_LL0_IOEL_FIR_ACTION1_REG)"); FAPI_TRY(fapi2::putScom(*l_iter, XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG, FBC_IOE_DL_FIR_MASK), "Error from putScom (XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG)"); } // set FBC optics config mode attribute l_obus_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS>(); for (auto l_iter = l_obus_chiplets.begin(); l_iter != l_obus_chiplets.end(); l_iter++) { uint8_t l_unit_pos; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, *l_iter, l_unit_pos), "Error from FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS)"); FAPI_INF("Updating index: %d\n", l_unit_pos); FAPI_INF(" before: %d\n", l_fbc_optics_cfg_mode[l_unit_pos]); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OPTICS_CONFIG_MODE, *l_iter, l_fbc_optics_cfg_mode[l_unit_pos]), "Error from FAPI_ATTR_GET(ATTR_OPTICS_CONFIG_MODE)"); FAPI_INF(" after: %d\n", l_fbc_optics_cfg_mode[l_unit_pos]); } FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE, i_target, l_fbc_optics_cfg_mode), "Error from FAPI_ATTR_SET(ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE)"); fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; }
//----------------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------------- /// /// @brief configure Cumulus inband address /// /// @param[in] i_target => Processor chip target /// /// @return FAPI_RC_SUCCESS if the setup completes successfully, else error // fapi2::ReturnCode p9c_set_inband_addr(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { uint64_t l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m, l_base_addr_mmio; FAPI_DBG("Start"); // determine base address of chip MMIO range FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, EFF_FBC_GRP_CHIP_IDS, l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m, l_base_addr_mmio), "Error from p9_fbc_utils_get_chip_base_address"); for (auto l_dmi : i_target.getChildren<fapi2::TARGET_TYPE_DMI>()) { fapi2::ATTR_DMI_INBAND_BAR_ENABLE_Type l_bar_enable; // retrieve inband BAR enable FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DMI_INBAND_BAR_ENABLE, l_dmi, l_bar_enable), "Error from FAPI_ATTR_GET (ATTR_DMI_INBAND_BAR_ENABLE)"); if (l_bar_enable == fapi2::ENUM_ATTR_DMI_INBAND_BAR_ENABLE_ENABLE) { fapi2::ATTR_DMI_INBAND_BAR_BASE_ADDR_OFFSET_Type l_bar_offset; uint64_t l_dmi_inband_addr; fapi2::buffer<uint64_t> l_scom_data; uint8_t l_dmi_pos; // retrieve inband BAR offset FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DMI_INBAND_BAR_BASE_ADDR_OFFSET, l_dmi, l_bar_offset), "Error from FAPI_ATTR_GET (ATTR_DMI_INBAND_BAR_BASE_ADDR_OFFSET)"); // form SCOM register format l_scom_data.flush<0>(); // BAR address 8:38 into bits 4:34 l_dmi_inband_addr = l_base_addr_mmio + l_bar_offset; l_scom_data.insert<4, 31, 8>(l_dmi_inband_addr); // Set valid(bit0 = 1), P9 mode(bit3 = 0) l_scom_data.setBit<0>(); // get MI target to configure MCFGPR fapi2::Target<fapi2::TARGET_TYPE_MI> l_mi = l_dmi.getParent<fapi2::TARGET_TYPE_MI>(); // retrieve DMI pos FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_dmi, l_dmi_pos), "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); // configure inband channel 0 MCFGPR0 if(l_dmi_pos % 2 == 0) { FAPI_TRY(fapi2::putScom(l_mi, MCS_MCRSVDE, l_scom_data), "Error from putScom MCFGPR0 for DMI id: %d", l_dmi_pos); } // configure inband channel 1 MCFGPR1 else { FAPI_TRY(fapi2::putScom(l_mi, MCS_MCRSVDF, l_scom_data), "Error from putScom MCFGPR1 for DMI id: %d", l_dmi_pos); } } } // configure host attention routing for (auto l_mc : i_target.getChildren<fapi2::TARGET_TYPE_MC>()) { fapi2::buffer<uint64_t> l_mcbcfg_data = 0; fapi2::buffer<uint64_t> l_mcbcfg_mask = 0; // Set P9 MCB Configuration Register // MCBCFGQ[62]=0 (disable special attention output) // MCBCFGQ[63]=1 (enable host attention output) l_mcbcfg_mask.setBit<62>(); l_mcbcfg_mask.setBit<63>(); l_mcbcfg_data.setBit<63>(); FAPI_TRY(fapi2::putScomUnderMask(l_mc, DMI_MCBCFG_0x070123E0, l_mcbcfg_data, l_mcbcfg_mask), "Error from putScom DMI_MCBCFG"); } for (auto l_mi : i_target.getChildren<fapi2::TARGET_TYPE_MI>()) { fapi2::buffer<uint64_t> l_mcmode2_data = 0; fapi2::buffer<uint64_t> l_mcmode2_mask = 0; // Set P9 MC Mode2 Register // MCMODE2Q[44]=0 (disable special attention output) // MCMODE2Q[45]=1 (enable host attention output) l_mcmode2_mask.setBit<44>(); l_mcmode2_mask.setBit<45>(); l_mcmode2_data.setBit<45>(); FAPI_TRY(fapi2::putScomUnderMask(l_mi, MI_MCMODE2_0x05010813, l_mcmode2_data, l_mcmode2_mask), "Error from putScom MI_MCMODE2"); } fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; }
fapi2::ReturnCode resetHTM( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint8_t i_pos) { FAPI_DBG("Entering"); fapi2::ReturnCode l_rc; fapi2::buffer<uint64_t> l_scomData(0); fapi2::buffer<uint64_t> l_scomData_2(0); uint32_t l_htmPendingActionCount = 0; // Verify NHTMs are in "Complete" state // NHTM0 FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData), "resetHTM: getScom returns error: Addr " "0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT, (uint64_t)fapi2::current_err); // NHTM1 FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2), "resetHTM: getScom returns error: Addr " "0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT, (uint64_t)fapi2::current_err); FAPI_ASSERT( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>() && l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>(), fapi2::P9_NHTM_CTRL_BAD_STATE() .set_TARGET(i_target) .set_HTM_STATUS_REG_NHTM0(l_scomData) .set_HTM_STATUS_REG_NHTM1(l_scomData_2), "resetHTM: NHTM is not in Complete state, can't reset " "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX", l_scomData, l_scomData_2); // Reset l_scomData = 0; l_scomData.flush<0>().setBit<PU_HTM0_HTM_TRIG_HTMSC_RESET>(); FAPI_INF("resetHTM: HTM_TRIG reg reset NHTM: 0x%016llX", l_scomData); FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[0] + HTM_TRIG, l_scomData), "resetHTM: putScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_TRIG, (uint64_t)fapi2::current_err); FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[1] + HTM_TRIG, l_scomData), "resetHTM: putScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_TRIG, (uint64_t)fapi2::current_err); l_htmPendingActionCount = 0; FAPI_INF("resetHTM: Waiting for NHTM Ready bit on NHTMs...", i_pos); while (l_htmPendingActionCount < P9_HTM_CTRL_TIMEOUT_COUNT) { FAPI_TRY(fapi2::delay(P9_HTM_CTRL_HW_NS_DELAY, P9_HTM_CTRL_SIM_CYCLE_DELAY), "resetHTM: fapi delay returns an error, l_rc 0x%.8X", (uint64_t)fapi2::current_err); // Check ready bit FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData), "resetHTM: getScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT, (uint64_t)fapi2::current_err); FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2), "resetHTM: getScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT, (uint64_t)fapi2::current_err); if ( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() && l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() ) { FAPI_INF("resetHTM: NHTM status = Ready on both NHTMs."); break; } // "Ready" is not asserted yet; increment timeout and check again l_htmPendingActionCount++; } // Error out if Ready bit is not set after reset FAPI_ASSERT( (l_htmPendingActionCount < P9_HTM_CTRL_TIMEOUT_COUNT), fapi2::P9_NHTM_CTRL_TIMEOUT() .set_TARGET(i_target) .set_DELAY_COUNT(l_htmPendingActionCount) .set_HTM_STATUS_REG_NHTM0(l_scomData) .set_HTM_STATUS_REG_NHTM1(l_scomData_2), "resetHTM: Timeout waiting for Ready bit after reset, Count 0x%.8X, " "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX", l_htmPendingActionCount, l_scomData, l_scomData_2); #if 0 // Note: // Save this code in case we want to perform reset via ADU // Build address value l_scomData.flush<0>().setBit<ADU_ADDRESS_HTM_RESET_BIT>(); // Reset global trigger on the NHTM engines FAPI_TRY(aduNHTMControl(i_target, l_scomData), "resetHTM: aduNHTMControl returns error."); #endif fapi_try_exit: FAPI_DBG("Exiting"); return fapi2::current_err; }
/// @brief To do check on Clock controller status for chiplets /// /// @param[in] i_target Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target /// @param[in] i_clock_cmd Issue clock controller command (START/STOP) /// @param[in] i_regions Enable required REGIONS /// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode p9_sbe_common_check_cc_status_function( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, const fapi2::buffer<uint8_t> i_clock_cmd, const fapi2::buffer<uint16_t> i_regions, const fapi2::buffer<uint8_t> i_clock_types) { bool l_reg_sl = false; bool l_reg_nsl = false; bool l_reg_ary = false; fapi2::buffer<uint64_t> l_sl_clock_status; fapi2::buffer<uint64_t> l_nsl_clock_status; fapi2::buffer<uint64_t> l_ary_clock_status; fapi2::buffer<uint16_t> l_sl_clkregion_status; fapi2::buffer<uint16_t> l_nsl_clkregion_status; fapi2::buffer<uint16_t> l_ary_clkregion_status; fapi2::buffer<uint16_t> l_regions; FAPI_INF("p9_sbe_common_check_cc_status_function: Entering ..."); l_reg_sl = i_clock_types.getBit<5>(); l_reg_nsl = i_clock_types.getBit<6>(); l_reg_ary = i_clock_types.getBit<7>(); i_regions.extractToRight<5, 11>(l_regions); if ( l_reg_sl ) { FAPI_DBG("Check for Clocks running SL"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status); if ( i_clock_cmd == 0b01 ) { FAPI_DBG("Checking for clock start command"); l_sl_clkregion_status.flush<1>(); l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); l_sl_clkregion_status.invert(); l_sl_clkregion_status &= l_regions; FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) .set_REGIONS(i_regions) .set_READ_CLK(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } if ( i_clock_cmd == 0b10 ) { FAPI_DBG("Checking for clock stop command"); l_sl_clkregion_status.flush<0>(); l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); l_sl_clkregion_status &= l_regions; FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) .set_REGIONS(i_regions) .set_READ_CLK(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } } if ( l_reg_nsl ) { FAPI_DBG("Check for clocks running NSL"); //Getting CLOCK_STAT_NSL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status); if ( i_clock_cmd == 0b01 ) { FAPI_DBG("Checking for clock start command"); l_nsl_clkregion_status.flush<1>(); l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); l_nsl_clkregion_status.invert(); l_nsl_clkregion_status &= l_regions; FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) .set_REGIONS(i_regions) .set_READ_CLK(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } if ( i_clock_cmd == 0b10 ) { FAPI_DBG("Checking for clock stop command"); l_nsl_clkregion_status.flush<0>(); l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); l_nsl_clkregion_status &= l_regions; FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) .set_REGIONS(i_regions) .set_READ_CLK(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } } if ( l_reg_ary ) { FAPI_DBG("Check for clocks running ARY"); //Getting CLOCK_STAT_ARY register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status); if ( i_clock_cmd == 0b01 ) { FAPI_DBG("Checking for clock start command"); l_ary_clkregion_status.flush<1>(); l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); l_ary_clkregion_status.invert(); l_ary_clkregion_status &= l_regions; FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) .set_REGIONS(i_regions) .set_READ_CLK(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } if ( i_clock_cmd == 0b10 ) { FAPI_DBG("Checking for clock stop command"); l_ary_clkregion_status.flush<0>(); l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); l_ary_clkregion_status &= l_regions; FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) .set_REGIONS(i_regions) .set_READ_CLK(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } } FAPI_INF("p9_sbe_common_check_cc_status_function: Exiting ..."); fapi_try_exit: return fapi2::current_err; }
/// @brief -- Utility function that can be used to start clocks for a specific input regions /// -- i_regions is to input regions /// /// /// @param[in] i_target Reference to TARGET_TYPE_PERV target /// @param[in] i_clock_cmd Issue clock controller command (START/STOP) /// @param[in] i_startslave Bit to configure to start Slave /// @param[in] i_startmaster Bit to configure to start Master /// @param[in] i_regions Enable required REGIONS /// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode p9_sbe_common_clock_start_stop(const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, const fapi2::buffer<uint8_t> i_clock_cmd, const bool i_startslave, const bool i_startmaster, const fapi2::buffer<uint64_t> i_regions, const fapi2::buffer<uint8_t> i_clock_types) { fapi2::buffer<uint64_t> l_sl_clock_status; fapi2::buffer<uint64_t> l_nsl_clock_status; fapi2::buffer<uint64_t> l_ary_clock_status; fapi2::buffer<uint64_t> l_exp_sl_clock_status; fapi2::buffer<uint64_t> l_exp_nsl_clock_status; fapi2::buffer<uint64_t> l_exp_ary_clock_status; fapi2::buffer<uint8_t> l_clk_cmd; fapi2::buffer<uint16_t> l_regions; fapi2::buffer<uint8_t> l_reg_all; bool l_reg_sl = false; bool l_reg_nsl = false; bool l_reg_ary = false; fapi2::buffer<uint64_t> l_data64; int l_timeout = 0; FAPI_INF("p9_sbe_common_clock_start_stop: Entering ..."); i_regions.extractToRight<53, 11>(l_regions); i_clock_types.extractToRight<5, 3>(l_reg_all); l_reg_sl = i_clock_types.getBit<5>(); l_reg_nsl = i_clock_types.getBit<6>(); l_reg_ary = i_clock_types.getBit<7>(); FAPI_DBG("Chiplet exit flush"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); FAPI_TRY(fapi2::putScom(i_target, PERV_CPLT_CTRL0_OR, l_data64)); FAPI_DBG("Clear Scan region type register"); //Setting SCAN_REGION_TYPE register value //SCAN_REGION_TYPE = 0 FAPI_TRY(fapi2::putScom(i_target, PERV_SCAN_REGION_TYPE, 0)); FAPI_DBG("Reading the initial status of clock controller"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL //Getting CLOCK_STAT_NSL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL //Getting CLOCK_STAT_ARY register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY FAPI_DBG("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX", l_sl_clock_status, l_nsl_clock_status, l_ary_clock_status); i_clock_cmd.extractToRight<6, 2>(l_clk_cmd); FAPI_DBG("Setup all Clock Domains and Clock Types"); //Setting CLK_REGION register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLK_REGION, l_data64)); l_data64.insertFromRight<PERV_1_CLK_REGION_CLOCK_CMD, PERV_1_CLK_REGION_CLOCK_CMD_LEN> (l_clk_cmd); //CLK_REGION.CLOCK_CMD = l_clk_cmd //CLK_REGION.SLAVE_MODE = i_startslave l_data64.writeBit<PERV_1_CLK_REGION_SLAVE_MODE>(i_startslave); //CLK_REGION.MASTER_MODE = i_startmaster l_data64.writeBit<PERV_1_CLK_REGION_MASTER_MODE>(i_startmaster); //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions l_data64.insertFromRight<4, 11>(l_regions); //CLK_REGION.SEL_THOLD_ALL = l_reg_all l_data64.insertFromRight<48, 3>(l_reg_all); FAPI_TRY(fapi2::putScom(i_target, PERV_CLK_REGION, l_data64)); // To wait until OPCG Done - CPLT_STAT0.cc_cplt_opcg_done_dc = 1 FAPI_DBG("Poll OPCG done bit to check for completeness"); l_data64.flush<0>(); l_timeout = CPLT_OPCG_DONE_DC_POLL_COUNT; while (l_timeout != 0) { //Getting CPLT_STAT0 register value FAPI_TRY(fapi2::getScom(i_target, PERV_CPLT_STAT0, l_data64)); bool l_poll_data = l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); if (l_poll_data == 1) { break; } fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); --l_timeout; } FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); FAPI_ASSERT(l_timeout > 0, fapi2::CPLT_OPCG_DONE_NOT_SET_ERR() .set_TARGET_CHIPLET(i_target) .set_PERV_CPLT_STAT0(l_data64) .set_LOOP_COUNT(l_timeout) .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); //To do do checking only for chiplets that dont have Master-slave mode enabled if ( !i_startslave && !i_startmaster ) { // Calculating the Expected clock status FAPI_TRY(p9_sbe_common_check_status(i_regions, l_sl_clock_status, l_reg_sl, i_clock_cmd, l_exp_sl_clock_status)); FAPI_TRY(p9_sbe_common_check_status(i_regions, l_nsl_clock_status, l_reg_nsl, i_clock_cmd, l_exp_nsl_clock_status)); FAPI_TRY(p9_sbe_common_check_status(i_regions, l_ary_clock_status, l_reg_ary, i_clock_cmd, l_exp_ary_clock_status)); FAPI_DBG("Check for clocks running SL"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_sl_clock_status, l_sl_clock_status); FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) .set_REGIONS(i_regions) .set_READ_CLK(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); FAPI_DBG("Check for clocks running NSL"); //Getting CLOCK_STAT_NSL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_nsl_clock_status, l_nsl_clock_status); FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) .set_REGIONS(i_regions) .set_READ_CLK(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); FAPI_DBG("Check for clocks running ARY"); //Getting CLOCK_STAT_ARY register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_ary_clock_status, l_ary_clock_status); FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) .set_CLOCK_CMD(i_clock_cmd) .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) .set_REGIONS(i_regions) .set_READ_CLK(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } FAPI_INF("p9_sbe_common_clock_start_stop: Exiting ..."); fapi_try_exit: return fapi2::current_err; }
fapi2::ReturnCode pm_pba_fir_init( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { FAPI_IMP("pm_pba_fir_init Enter"); uint8_t firinit_done_flag; p9pmFIR::PMFir <p9pmFIR::FIRTYPE_PBA_LFIR> l_pbaFir(i_target); FAPI_TRY(l_pbaFir.get(p9pmFIR::REG_ALL), "ERROR: Failed to get the PBA FIR values"); /* Clear the FIR and action buffers */ FAPI_TRY(l_pbaFir.clearAllRegBits(p9pmFIR::REG_FIR), "ERROR: Failed to clear PBA FIR"); FAPI_TRY(l_pbaFir.clearAllRegBits(p9pmFIR::REG_ACTION0), "ERROR: Failed to clear PBA FIR"); FAPI_TRY(l_pbaFir.clearAllRegBits(p9pmFIR::REG_ACTION1), "ERROR: Failed to clear PBA FIR"); FAPI_TRY(l_pbaFir.setAllRegBits(p9pmFIR::REG_FIRMASK), "ERROR: Faled to set the PBA FIR MASK"); /* Set the action and mask for the PBA LFIR bits */ FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_OCI_APAR_ERR), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_PB_RDADRERR_FW), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_PB_RDDATATO_FW), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_PB_SUE_FW), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_UE_FW), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_CE_FW), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_OCI_SLAVE_INIT), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_OCI_WRPAR_ERR), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_SPARE), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_UNEXPCRESP), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_UNEXPDATA), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_PARITY_ERR), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_WRADRERR_FW), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_BADCRESP), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_PB_ACKDEAD_FW_RD), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_PB_CRESPTO), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCUE_SETUP_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCUE_PB_ACK_DEAD), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCUE_PB_ADRERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCUE_OCI_DATERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_SETUP_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_PB_ACK_DEAD), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_PB_ADRERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_RDDATATO_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_SUE_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_UE_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_CE), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_BCDE_OCI_DATERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_INTERNAL_ERR), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_ILLEGAL_CACHE_OP), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.setRecvAttn(PBAFIR_OCI_BAD_REG_ADDR), FIR_REC_ATTN_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXPUSH_WRERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXRCV_DLO_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXRCV_DLO_TO), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXRCV_RSVDATA_TO), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXFLOW_ERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXSND_DHI_RTYTO), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXSND_DLO_RTYTO), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXSND_RSVTO), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_AXSND_RSVERR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_PB_ACKDEAD_FW_WR), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_RESERVED_41), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_RESERVED_42), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_RESERVED_43), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_FIR_PARITY_ERR2), FIR_MASK_ERROR); FAPI_TRY(l_pbaFir.mask(PBAFIR_FIR_PARITY_ERR), FIR_MASK_ERROR); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_FIRINIT_DONE_ONCE_FLAG, i_target, firinit_done_flag), "ERROR: Failed to fetch the entry status of FIRINIT"); FAPI_DBG("firinit_done_flag for PBA = %d", firinit_done_flag); if (firinit_done_flag) { FAPI_TRY(l_pbaFir.restoreSavedMask(), "ERROR: Failed to restore the mask saved"); } FAPI_TRY(l_pbaFir.put(), "ERROR:Failed to write to the PBA FIR MASK"); fapi_try_exit: return fapi2::current_err; }
/// @brief --For all chiplets exit flush /// --For all chiplets enable alignment /// --For all chiplets disable alignemnt /// /// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target /// @return FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode p9_sbe_common_align_chiplets(const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) { fapi2::buffer<uint64_t> l_data64; int l_timeout = 0; FAPI_INF("p9_sbe_common_align_chiplets: Entering ..."); FAPI_DBG("For all chiplets: exit flush"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); FAPI_DBG("For all chiplets: enable alignement"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 1 l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); FAPI_DBG("Clear chiplet is aligned"); //Setting SYNC_CONFIG register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b1 l_data64.setBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); FAPI_DBG("Unset Clear chiplet is aligned"); //Setting SYNC_CONFIG register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0 l_data64.clearBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); l_timeout = CPLT_ALIGN_CHECK_POLL_COUNT; //UNTIL CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC == 1 while (l_timeout != 0) { //Getting CPLT_STAT0 register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); bool l_poll_data = l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC if (l_poll_data == 1) { break; } fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); --l_timeout; } FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, fapi2::CPLT_NOT_ALIGNED_ERR() .set_TARGET_CHIPLET(i_target_chiplets) .set_PERV_CPLT_STAT0(l_data64) .set_LOOP_COUNT(l_timeout) .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET NOT ALIGNED"); FAPI_DBG("For all chiplets: disable alignement"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 0 l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); FAPI_INF("p9_sbe_common_align_chiplets: Exiting ..."); fapi_try_exit: return fapi2::current_err; }
fapi2::ReturnCode startHTM( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint8_t i_pos, const uint8_t i_traceType) { FAPI_DBG("Entering"); fapi2::ReturnCode l_rc; fapi2::buffer<uint64_t> l_scomData(0); fapi2::buffer<uint64_t> l_scomData_2(0); // Engines must be in ready or pause state FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData), "startHTM: getScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT, (uint64_t)fapi2::current_err); FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2), "startHTM: getScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT, (uint64_t)fapi2::current_err); FAPI_ASSERT( (l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() || l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED>()) && (l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() || l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED>()), fapi2::P9_NHTM_CTRL_BAD_STATE() .set_TARGET(i_target) .set_HTM_STATUS_REG_NHTM0(l_scomData) .set_HTM_STATUS_REG_NHTM1(l_scomData_2), "startHTM: NHTM is not in Ready state, can't start " "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX", l_scomData, l_scomData_2); // Set HTM_TRIG's MARK_VALID l_scomData = 0; l_scomData.setBit<PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID>(); FAPI_INF("startHTM: HTM_TRIG reg Start: 0x%016llX", l_scomData); FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[0] + HTM_TRIG, l_scomData), "startHTM: putScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_TRIG, (uint64_t)fapi2::current_err); FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[1] + HTM_TRIG, l_scomData), "startHTM: putScom returns error: " "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_TRIG, (uint64_t)fapi2::current_err); // Note: Use global PMISC ADU start command to better synchornize // the traces of NHTM0 and NHTM1 // Build address value l_scomData.flush<0>().setBit<ADU_ADDRESS_HTM_START_BIT>(); // Start global trigger on the NHTM engines FAPI_TRY(aduNHTMControl(i_target, l_scomData), "startHTM: aduNHTMControl returns error."); fapi_try_exit: FAPI_DBG("Exiting"); return fapi2::current_err; }
/// /// @brief p9_htm_start procedure entry point /// See doxygen in p9_htm_start.H /// fapi2::ReturnCode p9_htm_start( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { FAPI_DBG("Entering"); fapi2::ReturnCode l_rc; uint8_t l_nhtmType; uint8_t l_chtmType[NUM_CHTM_ENGINES]; uint8_t l_corePos = 0; auto l_modeRegList = std::vector<uint64_t>(); auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>(); fapi2::buffer<uint64_t> l_scomData(0); // Display attribute trace setup values FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_TRACE_TYPE, i_target, l_nhtmType), "p9_htm_start: Error getting ATTR_NHTM_TRACE_TYPE, l_rc 0x%.8X", (uint64_t)fapi2::current_err); FAPI_INF("p9_htm_start: NHTM type: 0x%.8X", l_nhtmType); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_TRACE_TYPE, i_target, l_chtmType), "p9_htm_start: Error getting ATTR_CHTM_TRACE_TYPE, l_rc 0x%.8X", (uint64_t)fapi2::current_err); FAPI_INF("p9_htm_start: CHTM type:"); for (uint8_t ii = 0; ii < NUM_CHTM_ENGINES; ii++) { FAPI_INF(" Core[%u] 0x%.8X", ii, l_chtmType[ii]); } // Start NHTM if (l_nhtmType != fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_DISABLE) { // Start trace for both NHTM0 and NHTM1 // Note: We want to synch the trace for both NHTM engines as much // as possible, so do not loop on individual engine // here. The startHTM function will check state and issue // a global ADU command to start both engines. FAPI_TRY( startHTM(i_target, 0, l_nhtmType), "p9_htm_start: startHTM() returns error NHTM" "l_rc 0x%.8X", (uint64_t)fapi2::current_err ); } // Start CHTM for (auto l_core : l_coreChiplets) { // Get the core position FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_core, l_corePos), "Error getting ATTR_CHIP_UNIT_POS"); if (l_chtmType[l_corePos] != fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE) { FAPI_DBG("Start HTM on core %u....", l_corePos); FAPI_TRY(startHTM(l_core, l_corePos, l_chtmType[l_corePos]), "p9_htm_start: startHTM() returns error: CHTM %u, " "l_rc 0x%.8X", l_corePos, (uint64_t)fapi2::current_err ); } } fapi_try_exit: FAPI_DBG("Exiting"); return fapi2::current_err; }
//------------------------------------------------------------------------------ // function: // Stop SBE runtime scan service // // parameters: i_target => chip target // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_stop_sbe_scan_service( const fapi::Target& i_target, const void* i_pSEEPROM) { // return codes fapi::ReturnCode rc; uint32_t rc_ecmd = 0; // track if procedure has cleared I2C master bus fence bool i2cm_bus_fence_cleared = false; // mark function entry FAPI_DBG("Start"); do { // check SBE progress bool sbe_running = true; size_t loop_time = 0; uint8_t halt_code = 0; uint16_t istep_num = 0; uint8_t substep_num = 0; bool scan_service_loop_reached = false; // retrieve status rc = proc_sbe_utils_check_status( i_target, sbe_running, halt_code, istep_num, substep_num); if (!rc.ok()) { FAPI_ERR("Error from proc_check_sbe_state_check_status"); break; } // get HB->SBE request mailbox, check that it is clear ecmdDataBufferBase mbox_data(64); bool sbe_ready = false; rc = fapiGetScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data); if (!rc.ok()) { FAPI_ERR("Scom error reading SBE MBOX0 Register"); break; } sbe_ready = (mbox_data.getDoubleWord(0) == 0); scan_service_loop_reached = sbe_running && sbe_ready && !halt_code && (istep_num == PROC_SBE_SCAN_SERVICE_ISTEP_NUM) && (substep_num == SUBSTEP_SBE_READY); FAPI_INF("SBE is running [%d], loop time [%zd], scan service loop reached [%d]", sbe_running, loop_time, scan_service_loop_reached); if (!sbe_running) { FAPI_INF("SBE is stopped, exiting!"); break; } else if (scan_service_loop_reached) { // format stop request rc_ecmd |= mbox_data.setBit(MBOX0_REQUEST_VALID_BIT); rc_ecmd |= mbox_data.insertFromRight(MBOX0_HALT_PATTERN, MBOX0_HALT_PATTERN_START_BIT, (MBOX0_HALT_PATTERN_END_BIT- MBOX0_HALT_PATTERN_START_BIT)+1); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up SBE MBOX0 data buffer.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } // submit stop request to SBE FAPI_DBG("Submitting stop request to SBE"); rc = fapiPutScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data); if (!rc.ok()) { FAPI_ERR("Error writing SBE MBOX0 Register"); break; } // pause to allow request to be processed uint32_t loop_num = 0; while (sbe_running && (loop_num < SBE_HALT_POLL_MAX_LOOPS)) { loop_num++; rc = fapiDelay(SBE_HALT_POLL_DELAY_HW, SBE_HALT_POLL_DELAY_SIM); if (!rc.ok()) { FAPI_ERR("Error from fapiDelay"); break; } // retrieve status rc = proc_sbe_utils_check_status( i_target, sbe_running, halt_code, istep_num, substep_num); if (!rc.ok()) { FAPI_ERR("Error from proc_check_sbe_state_check_status"); break; } } if (rc) { break; } if (sbe_running) { FAPI_ERR("SBE is STILL running!"); const fapi::Target & TARGET = i_target; FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_SBE_NOT_STOPPED); break; } // before analysis proceeds, make sure that I2C master bus fence is cleared FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target); if (!rc.ok()) { FAPI_ERR("Error from proc_reset_i2cm_bus_fence"); break; } // mark that fence has been cleared i2cm_bus_fence_cleared = true; // ensure correct halt code is captured rc = proc_sbe_utils_check_status( i_target, sbe_running, halt_code, istep_num, substep_num); if (!rc.ok()) { FAPI_ERR("Error from proc_check_sbe_state_check_status"); break; } // confirm that expected halt point was reached if (halt_code != SBE_EXIT_SUCCESS_0xF) { FAPI_ERR("SBE halted with error 0x%X (istep 0x%03X, substep 0x%X)", halt_code, istep_num, substep_num); // extract & return error code from analyzing SBE state FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, NULL, i_pSEEPROM, SBE); break; } if ((istep_num != PROC_SBE_SCAN_SERVICE_ISTEP_NUM) || (substep_num != SUBSTEP_HALT_SUCCESS)) { FAPI_ERR("Expected SBE istep 0x%03llX, substep 0x%X but found istep 0x%03X, substep 0x%X", PROC_SBE_SCAN_SERVICE_ISTEP_NUM, SUBSTEP_HALT_SUCCESS, istep_num, substep_num); const fapi::Target & TARGET = i_target; const uint32_t & ISTEP_NUM = istep_num; const uint32_t & SUBSTEP_NUM = substep_num; FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_SBE_BAD_HALT); break; } // Reset the SBE so it can be used for MPIPL if needed ecmdDataBufferBase sbe_reset_data(64); rc = fapiPutScom(i_target, PORE_SBE_RESET_0x000E0002, sbe_reset_data); if (!rc.ok()) { FAPI_ERR("Scom error resetting SBE\n"); break; } } // error else { FAPI_ERR("SBE did not reach acceptable final state!"); const fapi::Target & TARGET = i_target; const bool & SBE_RUNNING = sbe_running; const uint8_t & HALT_CODE = halt_code; const uint16_t & ISTEP_NUM = istep_num; const uint8_t & SUBSTEP_NUM = substep_num; FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_UNEXPECTED_FINAL_STATE); break; } } while(0); // if an error occurred prior to the I2C master bus fence // being cleared, attempt to clear it prior to exit if (!rc.ok() && !i2cm_bus_fence_cleared) { // discard rc, return that of original fail fapi::ReturnCode rc_unused; FAPI_EXEC_HWP(rc_unused, proc_reset_i2cm_bus_fence, i_target); } // mark function entry FAPI_DBG("End"); return rc; }
fapi2::ReturnCode p9_set_fsi_gp_shadow(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { fapi2::buffer<uint8_t> l_read_attr; fapi2::buffer<uint32_t> l_cfam_data; FAPI_INF("p9_set_fsi_gp_shadow: Entering ..."); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE, i_target_chip, l_read_attr)); if ( l_read_attr ) { FAPI_DBG("Setting flush values for root_ctrl_copy and perv_ctrl_copy registers"); //Setting ROOT_CTRL0_COPY register value //CFAM.ROOT_CTRL0_COPY = p9SetFsiGpShadow::ROOT_CTRL0_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL0_FLUSHVALUE)); //Setting ROOT_CTRL1_COPY register value //CFAM.ROOT_CTRL1_COPY = p9SetFsiGpShadow::ROOT_CTRL1_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL1_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL1_FLUSHVALUE)); //Setting ROOT_CTRL2_COPY register value //CFAM.ROOT_CTRL2_COPY = p9SetFsiGpShadow::ROOT_CTRL2_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL2_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL2_FLUSHVALUE)); //Setting ROOT_CTRL3_COPY register value //CFAM.ROOT_CTRL3_COPY = p9SetFsiGpShadow::ROOT_CTRL3_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL3_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL3_FLUSHVALUE)); //Setting ROOT_CTRL4_COPY register value //CFAM.ROOT_CTRL4_COPY = p9SetFsiGpShadow::ROOT_CTRL4_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL4_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL4_FLUSHVALUE)); //Setting ROOT_CTRL5_COPY register value //CFAM.ROOT_CTRL5_COPY = p9SetFsiGpShadow::ROOT_CTRL5_FLUSHVALUE FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL5_COPY_FSI, l_cfam_data)); l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL5_MASK) | p9SetFsiGpShadow::ROOT_CTRL5_FLUSHVALUE; FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL5_COPY_FSI, l_cfam_data)); //Setting ROOT_CTRL6_COPY register value //CFAM.ROOT_CTRL6_COPY = p9SetFsiGpShadow::ROOT_CTRL6_FLUSHVALUE FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL6_COPY_FSI, l_cfam_data)); l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL6_MASK) | p9SetFsiGpShadow::ROOT_CTRL6_FLUSHVALUE; FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL6_COPY_FSI, l_cfam_data)); //Setting ROOT_CTRL7_COPY register value //CFAM.ROOT_CTRL7_COPY = p9SetFsiGpShadow::ROOT_CTRL7_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL7_COPY_FSI, p9SetFsiGpShadow::ROOT_CTRL7_FLUSHVALUE)); //Setting ROOT_CTRL8_COPY register value //CFAM.ROOT_CTRL8_COPY = p9SetFsiGpShadow::ROOT_CTRL8_FLUSHVALUE FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL8_COPY_FSI, l_cfam_data)); l_cfam_data = (l_cfam_data & p9SetFsiGpShadow::ROOT_CTRL8_MASK) | p9SetFsiGpShadow::ROOT_CTRL8_FLUSHVALUE; FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL8_COPY_FSI, l_cfam_data)); //Setting PERV_CTRL0_COPY register value //CFAM.PERV_CTRL0_COPY = p9SetFsiGpShadow::PERV_CTRL0_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_PERV_CTRL0_COPY_FSI, p9SetFsiGpShadow::PERV_CTRL0_FLUSHVALUE)); //Setting PERV_CTRL1_COPY register value //CFAM.PERV_CTRL1_COPY = p9SetFsiGpShadow::PERV_CTRL1_FLUSHVALUE FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_PERV_CTRL1_COPY_FSI, p9SetFsiGpShadow::PERV_CTRL1_FLUSHVALUE)); } /* Write the value of FUSED_CORE_MODE into PERV_CTRL0(23) regardless of chip EC; the bit is nonfunctional on Nimbus DD1 */ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_read_attr)); FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_PERV_CTRL0_COPY_FSI, l_cfam_data)); if (l_read_attr) { l_cfam_data.setBit<P9N2_PERV_PERV_CTRL0_TP_OTP_SCOM_FUSED_CORE_MODE>(); } else { l_cfam_data.clearBit<P9N2_PERV_PERV_CTRL0_TP_OTP_SCOM_FUSED_CORE_MODE>(); } FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_PERV_CTRL0_COPY_FSI, l_cfam_data)); FAPI_INF("p9_set_fsi_gp_shadow: Exiting ..."); fapi_try_exit: return fapi2::current_err; }
fapi::ReturnCode fapiDelay(uint64_t i_nanoSeconds, uint64_t i_simCycles) { FAPI_DBG( INFO_MRK "delay %lld nanosec", i_nanoSeconds ); nanosleep( 0, i_nanoSeconds ); return fapi::FAPI_RC_SUCCESS; }