/** * @brief Initialize the SSP through the data in structure SSP_InitTypeDef * @param InitStruct: parameters to configure SSP mode * @retval None */ void SSP_Init(SSP_InitTypeDef * InitStruct) { /* Check the parameters */ assert_param(IS_POINTER_NOT_NULL(InitStruct)); SSP_SetFrameFormat(InitStruct->FrameFormat); SSP_SetClkPreScale(InitStruct->PreScale, InitStruct->ClkRate); SSP_SetClkPolarity(InitStruct->ClkPolarity); SSP_SetClkPhase(InitStruct->ClkPhase); SSP_SetDataSize(InitStruct->DataSize); SSP_SetMSMode(InitStruct->Mode); }
void spi_frequency(spi_t *obj, int hz) { TSB_SSP_TypeDef* spi; // Search Freq data int fr_gear = 1; int cur_hz = 1; int32_t best_diff = TMPM46B_SPI_FMAX; int best_cpsdvsr = 254; int best_scr = 255; int cur_cpsdvsr = 48; int cur_scr = 0; int32_t diff; /* Assert Min frequency Hz = Fsys / (CPSDVSR * (SCR + 1)) Domain value of CPSDVSR is an even number between 2 to 254 Domain value of SCR is a number between 0 to 255 Hz Min if CPSDVSR and SCR max (CPSDVSR = 254, SCR = 255) */ MBED_ASSERT((SystemCoreClock / 65024) <= (uint32_t)hz); if (obj->module == SPI_2) { MBED_ASSERT(hz <= TMPM46B_SPI_2_FMAX); } else { MBED_ASSERT(hz <= TMPM46B_SPI_FMAX); // Default value of SPI_0, SPI_1, SPI_2 } spi = obj->spi; fr_gear = SystemCoreClock / hz; if (fr_gear < 48) { cur_cpsdvsr = fr_gear; } while (best_diff != 0 && cur_cpsdvsr <= 254) { cur_scr = fr_gear / cur_cpsdvsr - 1; if (cur_scr < 0) { break; } for (; cur_scr < 256; ++cur_scr) { cur_hz = SystemCoreClock / (cur_cpsdvsr * (1 + cur_scr)); diff = cur_hz - hz; if (diff < 0) { diff = -diff; } if (diff < best_diff) { best_cpsdvsr = cur_cpsdvsr; best_scr = cur_scr; best_diff = diff; } else if (diff >= best_diff) { break; } } cur_cpsdvsr += 2; } SSP_Disable(spi); // Set bit rate of SPI SSP_SetClkPreScale(spi, (uint8_t)best_cpsdvsr, (uint8_t)best_scr); SSP_Enable(spi); }