/**Function************************************************************* Synopsis [Maps virtual latches into real latches.] Description [Creates new latches and assigns them to virtual latches on the edges of a sequential AIG. The nodes of the new network should be created before this procedure is called.] SideEffects [] SeeAlso [] ***********************************************************************/ void Seq_NtkShareLatches( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk ) { Abc_Obj_t * pObj, * pFanin; stmm_table * tLatchMap; int i; assert( Abc_NtkIsSeq( pNtk ) ); tLatchMap = stmm_init_table( stmm_ptrcmp, stmm_ptrhash ); Abc_AigForEachAnd( pNtk, pObj, i ) { pFanin = Abc_ObjFanin0(pObj); Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,0), Seq_NodeCountLats(pObj,0), tLatchMap ); pFanin = Abc_ObjFanin1(pObj); Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,1), Seq_NodeCountLats(pObj,1), tLatchMap ); }
/**Function************************************************************* Synopsis [Insert the last Lat on the edge.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Seq_NodeCompareLats( Abc_Obj_t * pObj1, int Edge1, Abc_Obj_t * pObj2, int Edge2 ) { Seq_Lat_t * pRing1, * pRing2, * pLat1, * pLat2; int i, nLatches1, nLatches2; nLatches1 = Seq_NodeCountLats( pObj1, Edge1 ); nLatches2 = Seq_NodeCountLats( pObj2, Edge2 ); if ( nLatches1 != nLatches2 ) return 0; pRing1 = Seq_NodeGetRing( pObj1, Edge1 ); pRing2 = Seq_NodeGetRing( pObj2, Edge2 ); for ( i = 0, pLat1 = pRing1, pLat2 = pRing2; i < nLatches1; i++, pLat1 = pLat1->pNext, pLat2 = pLat2->pNext ) if ( Seq_LatInit(pLat1) != Seq_LatInit(pLat2) ) return 0; return 1; }
/**Function************************************************************* Synopsis [Insert the last Lat on the edge.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Seq_NodeDupLats( Abc_Obj_t * pObjNew, Abc_Obj_t * pObj, int Edge ) { Seq_Lat_t * pRing, * pLat; int i, nLatches; pRing = Seq_NodeGetRing( pObj, Edge ); if ( pRing == NULL ) return; nLatches = Seq_NodeCountLats( pObj, Edge ); for ( i = 0, pLat = pRing; i < nLatches; i++, pLat = pLat->pNext ) Seq_NodeInsertLast( pObjNew, Edge, Seq_LatInit(pLat) ); }
void Seq_NtkShareLatches( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk ) { Abc_Obj_t * pObj, * pFanin; stmm_table * tLatchMap; int i; assert( Abc_NtkIsSeq( pNtk ) ); tLatchMap = stmm_init_table( stmm_ptrcmp, stmm_ptrhash ); Abc_AigForEachAnd( pNtk, pObj, i ) { pFanin = Abc_ObjFanin0(pObj); Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,0), Seq_NodeCountLats(pObj,0), tLatchMap ); pFanin = Abc_ObjFanin1(pObj); Seq_NtkShareLatches_rec( pNtkNew, pFanin->pCopy, Seq_NodeGetRing(pObj,1), Seq_NodeCountLats(pObj,1), tLatchMap ); } Abc_NtkForEachPo( pNtk, pObj, i ) Seq_NtkShareLatches_rec( pNtkNew, Abc_ObjFanin0(pObj)->pCopy, Seq_NodeGetRing(pObj,0), Seq_NodeCountLats(pObj,0), tLatchMap ); stmm_free_table( tLatchMap ); } /**Function************************************************************* Synopsis [Maps virtual latches into real latches.] Description [Creates new latches and assigns them to virtual latches on the edges of a sequential AIG. The nodes of the new network should be created before this procedure is called.] SideEffects [] SeeAlso []