void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; switch (obj->index) { case 0: irq_n=UART0_RX_TX_IRQn; vector = (uint32_t)&uart0_irq; break; case 1: irq_n=UART1_RX_TX_IRQn; vector = (uint32_t)&uart1_irq; break; case 2: irq_n=UART2_RX_TX_IRQn; vector = (uint32_t)&uart2_irq; break; #if (UART_NUM > 3) case 3: irq_n=UART3_RX_TX_IRQn; vector = (uint32_t)&uart3_irq; break; case 4: irq_n=UART4_RX_TX_IRQn; vector = (uint32_t)&uart4_irq; break; #endif } uint32_t uart_addrs[] = UART_BASE_ADDRS; if (enable) { switch (irq) { case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], true); break; case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], true); break; } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); switch (irq) { case RxIrq: UART_HAL_SetRxDataRegFullIntCmd(uart_addrs[obj->index], false); break; case TxIrq: UART_HAL_SetTxDataRegEmptyIntCmd(uart_addrs[obj->index], false); break; } switch (other_irq) { case RxIrq: all_disabled = UART_HAL_GetRxDataRegFullIntCmd(uart_addrs[obj->index]) == 0; break; case TxIrq: all_disabled = UART_HAL_GetTxDataRegEmptyIntCmd(uart_addrs[obj->index]) == 0; break; } if (all_disabled) NVIC_DisableIRQ(irq_n); } }
void UART_DRV_CompleteSendData(uint32_t instance) { // assert(instance < HW_UART_UART_APP_INDEX_COUNT); mico_uart_t uart = getUartBy(instance); uint32_t baseAddr = g_uartBaseAddr[instance]; uart_state_t * uartState = (uart_state_t *)g_uartStatePtr[instance]; /* Disable the transmitter data register empty interrupt */ UART_HAL_SetTxDataRegEmptyIntCmd(baseAddr, false); /* Signal the synchronous completion object. */ if (uartState->isTxBlocking) { OSA_SemaPost(&uartState->txIrqSync); mico_rtos_set_semaphore(&uart_interfaces[uart].tx_complete); } /* Update the information of the module driver state */ uartState->isTxBusy = false; }