static int FillHWRect(_THIS, GAL_Surface *dst, GAL_Rect *rect, Uint32 color) { char *dst_base; dst_base = (char *)((char *)dst->pixels - mapped_mem); /* Execute the fill command */ WaitIdle (this); /* Set the destination pixel format */ validate_dst (this, dst); neo2200->fgColor = color; neo2200->bltCntl = NEO_BC3_FIFO_EN | NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING | 0x0c0000; neo2200->dstStart = (Uint32) dst_base + (rect->y * dst->pitch) + (rect->x * dst->format->BytesPerPixel); neo2200->xyExt = (rect->h << 16) | (rect->w & 0xffff); WaitIdle (this); return(0); }
static void HWAccelBlit_helper (GAL_Surface *src, GAL_Rect *srcrect, GAL_Surface *dst, GAL_Rect *dstrect) { GAL_VideoDevice *this = current_video; Uint32 src_base; Uint32 dst_base; /* Set the source and destination pixel format */ src_base = (Uint32)((char *)src->pixels - mapped_mem); dst_base = (Uint32)((char *)dst->pixels - mapped_mem); /* Perform the blit! */ neo2200->pitch = (dst->pitch << 16) | (src->pitch & 0xFFFF); neo2200->bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0c0000; if ( (src->flags & GAL_SRCCOLORKEY) == GAL_SRCCOLORKEY ) { neo2200->bltCntl |= NEO_BC0_SRC_TRANS; neo2200->xpColor = src->format->colorkey; } neo2200->srcStart = (Uint32) src_base + srcrect->y * src->pitch + srcrect->x * src->format->BytesPerPixel; neo2200->dstStart = (Uint32) dst_base + (dstrect->y * dst->pitch) + (dstrect->x * dst->format->BytesPerPixel); neo2200->xyExt = (srcrect->h << 16) | (srcrect->w & 0xffff); WaitIdle (this); }
static Bool SMI_CrtcLock (xf86CrtcPtr crtc) { ScrnInfoPtr pScrn = crtc->scrn; SMIPtr pSmi = SMIPTR(pScrn); ENTER(); WaitIdle(); LEAVE(FALSE); }
void GpuTimer::Reset( bool bResetSum ) { FinishCollection(); m_FrameID = (m_FrameID+1) & 0x3FFFFFFF; if( bResetSum ) { WaitIdle(); m_CurTimeFrame.invalid = 1; m_CurTime = 0.0; m_LastTime = 0.0; m_SumTime = 0.0; m_NumFrames = 0; } }
/*------------------------------------------------------------------------------ * * Misc. helper functions * *----------------------------------------------------------------------------*/ void _g3dkmd_Reset(G3DKMD_RESET_MODE mode) { if (mode == G3DKMD_RESET_MODE_COMMAND_QUEUE) { _g3dkmd_ResetCommandQueue(); } else if (mode == G3DKMD_RESET_MODE_ALL) { _g3dkmd_ResetCommandQueue(); #if 0 WaitIdle(); /* set multi-buffering */ if (g_G3dGlobals.Config.MultiBufferingEnabled == true) { REG_MASK_WRITE(REG_MULTI_BUF, MSK_MULTI_BUF_EN, MSK_MULTI_BUF_EN); /* double buffers */ REG_MASK_WRITE(REG_MULTI_BUF, (1 << SHF_MULTI_BUF_NUM), MSK_MULTI_BUF_NUM); REG_MASK_WRITE(REG_MULTI_BUF, 0, MSK_MULTI_BUF_MD); } else { REG_MASK_WRITE(REG_MULTI_BUF, 0, MSK_MULTI_BUF_EN); REG_MASK_WRITE(REG_MULTI_BUF, 0, MSK_MULTI_BUF_NUM); REG_MASK_WRITE(REG_MULTI_BUF, 0, MSK_MULTI_BUF_MD); } /* initialize fixed HW register settings */ WaitCommandQueue(sizeof(U32) * 4); WriteCommand(SINGLE_COMMAND | REG_PAGE_END); WriteCommand(0); WriteCommand(SINGLE_COMMAND | REG_VP_TRANSFORM); WriteCommand(MSK_CL_VP_TRANSFORM); #endif } }/* _g3dkmd_Reset */
void s3CleanUp(void) { int i; unsigned char tmp; outb(vgaCRIndex, 0x39); outb(vgaCRReg, 0xa5); if (s3MmioMem != NULL ) { WaitIdle(); VerticalRetraceWait(); ((mmtr)s3MmioMem)->memport_regs.regs.fifo_control = oldS3->fifo[0]; WaitIdle(); /* Don't ask... */ ((mmtr)s3MmioMem)->memport_regs.regs.streams_timeout = oldS3->fifo[1]; } #if 1 /* This seems to help, but maybe a wait for */ /* VSYNC would be better than WaitIdleEmpty(). */ /* STREAMS disable code, for 24 & 32 Bpp */ if ( ( s3InfoRec.bitsPerPixel == 32 || s3InfoRec.bitsPerPixel == 24 ) && s3MmioMem != NULL ) { /* temp - KJB */ ((mmtr)s3MmioMem)->streams_regs.regs.prim_fbaddr0 = 0; /* ((y * s3DisplayWidth + (x & ~3)) * s3Bpp) */ /* & ~3 */; /* end temp */ outb(vgaCRIndex, 0x67); tmp = inb(vgaCRReg); /* WaitIdleEmpty(); */ /* Disable STREAMS processor */ outb( vgaCRReg, tmp & ~0x0C ); } #endif vgaProtect(TRUE); if (s3NewMmio) { outb (vgaCRIndex, 0x58); outb (vgaCRReg, s3SAM256); /* disable linear mode */ } /* end BL */ WaitQueue(8); outb(vgaCRIndex, 0x35); tmp = inb(vgaCRReg); outb(vgaCRReg, (tmp & 0xf0)); cebank(); if (s3NewMmio) { outb(vgaCRIndex, 0x53); outb(vgaCRReg, 0x00); } /* Restore S3 Trio32/64 ext. sequenzer (PLL) registers */ if (DAC_IS_TRIO) { outb(0x3c2, oldS3->Trio[0]); outb(0x3c4, 0x08); outb(0x3c5, 0x06); outb(0x3c4, 0x09); outb(0x3c5, oldS3->Trio[2]); outb(0x3c4, 0x0a); outb(0x3c5, oldS3->Trio[3]); outb(0x3c4, 0x0b); outb(0x3c5, oldS3->Trio[4]); outb(0x3c4, 0x0d); outb(0x3c5, oldS3->Trio[5]); outb(0x3c4, 0x10); outb(0x3c5, oldS3->Trio[8]); outb(0x3c4, 0x11); outb(0x3c5, oldS3->Trio[9]); outb(0x3c4, 0x12); outb(0x3c5, oldS3->Trio[10]); outb(0x3c4, 0x13); outb(0x3c5, oldS3->Trio[11]); outb(0x3c4, 0x1a); outb(0x3c5, oldS3->Trio[12]); outb(0x3c4, 0x1b); outb(0x3c5, oldS3->Trio[13]); outb(0x3c4, 0x15); tmp = inb(0x3c5) & ~0x21; outb(0x3c5, tmp | 0x03); outb(0x3c5, tmp | 0x23); outb(0x3c5, tmp | 0x03); outb(0x3c4, 0x15); outb(0x3c5, oldS3->Trio[6]); outb(0x3c4, 0x18); outb(0x3c5, oldS3->Trio[7]); outb(0x3c4, 0x08); outb(0x3c5, oldS3->Trio[1]); } /* restore s3 special bits */ /* restore 801 specific registers */ for (i = 32; i < 46; i++) { outb(vgaCRIndex, 0x40 + i); outb(vgaCRReg, oldS3->s3sysreg[i]); } for (i = 0; i < 16; i++) { if (!((1 << i) & reg50_mask)) continue; outb(vgaCRIndex, 0x50 + i); outb(vgaCRReg, oldS3->s3sysreg[i + 16]); } for (i = 0; i < 5; i++) { outb(vgaCRIndex, 0x30 + i); outb(vgaCRReg, oldS3->s3reg[i]); outb(vgaCRIndex, 0x38 + i); outb(vgaCRReg, oldS3->s3reg[5 + i]); } outb(vgaCRIndex, 0x36); outb(vgaCRReg, oldS3->s3reg[10]); for (i = 0; i < 16; i++) { outb(vgaCRIndex, 0x40 + i); outb(vgaCRReg, oldS3->s3sysreg[i]); } outb(vgaCRIndex, 0x45); inb(vgaCRReg); /* reset color stack pointer */ outb(vgaCRIndex, 0x4A); for (i = 0; i < 4; i++) outb(vgaCRReg, oldS3->ColorStack[i]); outb(vgaCRIndex, 0x45); inb(vgaCRReg); /* reset color stack pointer */ outb(vgaCRIndex, 0x4B); for (i = 4; i < 8; i++) outb(vgaCRReg, oldS3->ColorStack[i]); if (OFLG_ISSET(CLOCK_OPTION_ICS2595, &s3InfoRec.clockOptions)){ outb(vgaCRIndex, 0x42); outb(vgaCRReg, (oldS3->s3sysreg[2] & 0xf0) | 0x01); outb(vgaCRIndex, 0x5c); /* switch back to 28MHz clock */ outb(vgaCRReg, 0x20); outb(vgaCRReg, 0x00); } vgaHWRestore((vgaHWPtr)oldS3); outb(0x3c2, old_clock); i = inb(0x3CC); if (savedVgaIOBase == 0x3B0) i &= 0xFE; else i |= 0x01; outb(0x3C2, i); vgaIOBase = savedVgaIOBase; vgaCRIndex = vgaIOBase + 4; vgaCRReg = vgaIOBase + 5; vgaProtect(FALSE); #ifdef PC98 crtswitch(0); #endif xf86DisableIOPorts(s3InfoRec.scrnIndex); }
void GpuCpuTimer::Stop() { WaitIdle(); CpuTimer::Stop(); }
void GpuCpuTimer::Start() { WaitIdle(); CpuTimer::Start(); }