/***************************************************************************//** * @brief gpio_data *******************************************************************************/ void gpio_data(uint8_t pin, uint8_t data) { #ifdef _XPARAMETERS_PS_H_ XGpioPs_WritePin(&gpio_instance, pin, data); #else uint32_t config = 0; uint32_t data_reg_addr; if (pin >= 32) { data_reg_addr = XGPIO_DATA2_OFFSET; pin -= 32; } else data_reg_addr = XGPIO_DATA_OFFSET; config = Xil_In32((gpio_config->BaseAddress + data_reg_addr)); if(data) { config |= (1 << pin); } else { config &= ~(1 << pin); } Xil_Out32((gpio_config->BaseAddress + data_reg_addr), config); #endif }
/***************************************************************************//** * @brief gpio_direction *******************************************************************************/ void gpio_direction(uint8_t pin, uint8_t direction) { #ifdef _XPARAMETERS_PS_H_ XGpioPs_SetDirectionPin(&gpio_instance, pin, direction); XGpioPs_SetOutputEnablePin(&gpio_instance, pin, 1); #else uint32_t config = 0; uint32_t tri_reg_addr; if (pin >= 32) { tri_reg_addr = XGPIO_TRI2_OFFSET; pin -= 32; } else tri_reg_addr = XGPIO_TRI_OFFSET; config = Xil_In32((gpio_config->BaseAddress + tri_reg_addr)); if(direction) { config &= ~(1 << pin); } else { config |= (1 << pin); } Xil_Out32((gpio_config->BaseAddress + tri_reg_addr), config); #endif }
void test(XHwIcap *HwIcap_p) { u8 i, flag, allFlag = 0; u16 j; u32 result, expectedResult; #define NUM_TEST 24 u8 mem[NUM_TEST][NUMBER_OF_PARAMETERS] = { {1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1}, {0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 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xil_printf("Writing %x to input register...\n\r",j); Xil_Out32(XPAR_AXI_ROM_0_BASEADDR, j); result = Xil_In32(XPAR_AXI_ROM_0_BASEADDR+4); expectedResult = parameter[j]; /*xil_printf("Reading output register: x%x (x%x expected)\n\r", result, expectedResult);*/ if(result != expectedResult) xil_printf("Test %d.%d failed\n\r",i,j); flag |= (result != expectedResult); } if(!flag) xil_printf("Test %d succeeded\n\r",i); allFlag |= flag; } if(!allFlag) xil_printf("All tests succeeded\n\r",i); else xil_printf("Some test failed\n\r",i); }
void inline timer0_systick_enable_interrupts(void) { u32 Reg32Value; Reg32Value = Xil_In32(XSCUTIMER_0_CONTROL_REG); Reg32Value |= ENIT0; Xil_Out32(XSCUTIMER_0_CONTROL_REG, Reg32Value); }
/***************************************************************************//** * @brief axi_adc_read *******************************************************************************/ int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data) { *reg_data = Xil_In32((adc->base + reg_addr)); return SUCCESS; }
/***************************************************************************//** * @brief dac_read *******************************************************************************/ int32_t dac_read(dac_core *core, uint32_t reg_addr, uint32_t *reg_data) { *reg_data = Xil_In32((core->base_address + 0x4000 + reg_addr)); return 0; }
/***************************************************************************//** * @brief spi_eng_dma_read *******************************************************************************/ int32_t spi_eng_dma_read(spi_dev *dev, uint32_t reg_addr, uint32_t *reg_data) { *reg_data = Xil_In32((dev->spi_offload_rx_dma_baseaddr + reg_addr)); return 0; }
inline void wlan_tx_buffer_sel(u8 n) { //The register-selected Tx pkt buffer is only used for transmissions that // are initiated via wlan_tx_start(); normal MAC transmissions will use // the mac_hw Tx functions, which override this pkt buf selection Xil_Out32(WLAN_TX_REG_PKT_BUF_SEL, ((Xil_In32(WLAN_TX_REG_PKT_BUF_SEL) & ~0xF) | (n&0xF)) ); return; }
/****************************************************************************** * @brief Uart Interrupt Handler * * @param None. * * @return None. ******************************************************************************/ void Ps7UartIntrHandler(void) { // Read data from RX Fifo rxData = Xil_In32(UART_BASEADDR + 0x30); // Clear interrupt Xil_Out32(UART_BASEADDR + 0x14, 0x01); }
/***************************************************************************//** * @brief adc_read *******************************************************************************/ int32_t adc_read(adc_core core, uint32_t reg_addr, uint32_t *reg_data) { *reg_data = Xil_In32((core.adc_baseaddr + reg_addr)); return 0; }
/****************************************************************************** * This function reads the I2C controller's 8 bit GPIO bits. * * @param pGpioData . * * @return If successfull, returns 1. Otherwise, returns 0. * * @note None. * ******************************************************************************/ int fmc_iic_axi_GpoRead( fmc_iic_t *pIIC, Xuint32 *pGpioData ) { fmc_iic_axi_t *pContext = (fmc_iic_axi_t *)(pIIC->pContext); *pGpioData = Xil_In32((pContext->CoreAddress + 0x124)); return 1; }
//------------------------------------------------------------------------------ tHostifReturn hostif_sysIrqEnable(BOOL fEnable_p) { if (fEnable_p) { XIntc_EnableIntr(HOSTIF_IRQ_IC_ID, (Xil_In32(HOSTIF_IRQ_IC_ID + XIN_IER_OFFSET) | (1 << HOSTIF_IRQ))); } else { XIntc_DisableIntr(HOSTIF_IRQ_IC_ID, (Xil_In32(HOSTIF_IRQ_IC_ID + XIN_IER_OFFSET) & ~(1 << HOSTIF_IRQ))); } return kHostifSuccessful; }
const NWADP * DEMRF24::deIPGetAdaptor(void) { // get our pins set up Xil_Out32(WF_GPIO_BASEADDRESS+4, 0b0001); Xil_Out32(WF_GPIO_BASEADDRESS, Xil_In32(WF_GPIO_BASEADDRESS)&0b0001); return(GetMRF24GAdaptor(NULL, hRRAdpHeap, NULL)); }
void XPfw_UtilRMW(u32 RegAddress, u32 Mask, u32 Value) { u32 l_Val; l_Val = Xil_In32(RegAddress); l_Val = (l_Val & (~Mask)) | (Mask & Value); Xil_Out32(RegAddress, l_Val); }
//called by other functions to read the timer registers u32 readTimerRegister(uint32_t timerNumber, uint32_t registerOffset)//passes in timer to be read and register offset { if(timerNumber == 0)//timer 0 { uint32_t address = INTERVALTIMER_TIMER_0_BASEADDR + registerOffset;// assign address to equal the base address plus the offset return Xil_In32(address); //return the address } if(timerNumber == 1)//timer 1 { uint32_t address = INTERVALTIMER_TIMER_1_BASEADDR + registerOffset;//// assign address to equal the base address plus the offset return Xil_In32(address); //return the address } if(timerNumber == 2) //timer 2 { uint32_t address = INTERVALTIMER_TIMER_2_BASEADDR + registerOffset;// assign address to equal the base address plus the offset return Xil_In32(address); //return the address } }
void SysAlloc_init(void){ Xil_Out32(MMU_BASE + MMU_INIT_RANGE, 2396745 - 32768); Xil_Out32(MMU_BASE + MMU_INIT, 1); int init_done = 0; while(init_done == 0){ init_done = Xil_In32(MMU_BASE + MMU_INIT); } print("(SysAlloc Init Done) "); }
void ProcessCommand (void) { char *command; uint32_t address; uint32_t data; ResetGetArgument (); /* while ((command = GetArgument ()) != NULL) { xil_printf ("[%s]\n\r", command); } */ if ((command = GetArgument ()) != NULL) { if (!strcmp (command, "r")) { // read register if ((command = GetArgument ()) != NULL) { address = hexatoi (command); data = Xil_In32 (address); xil_printf ("%08x: %08x\n\r", address, data); } } else if (!strcmp (command, "w")) { // write register if ((command = GetArgument ()) != NULL) { address = hexatoi (command); if ((command = GetArgument ()) != NULL) { data = hexatoi (command); Xil_Out32 (address, data); xil_printf ("%08x: %08x\n\r", address, data); } } } else if (!strcmp (command, "mt")) { MoveToCommand (); } else if (!strcmp (command, "?")) { InfoCommand (); } else if (!strcmp (command, "seq0")) { do { if (MoveTo ( 0, 0, 0, 0, 0, 0) < 0) { break; } if (MoveTo ( 0, -946, 7765, 0, 1080, 0) < 0) { break; } if (MoveTo ( 0, 6870, -5812, 0, -2000, 0) < 0) { break; } if (MoveTo ( 1792, 5385, 6222, 0, 1100, 0) < 0) { break; } if (MoveTo ( 0, 2521, 11313, 0, 720, 0) < 0) { break; } if (MoveTo ( 0, -946, 7765, 0, 1080, 0) < 0) { break; } if (MoveTo (-1792, 5385, 6222, 0, 1100, 0) < 0) { break; } if (MoveTo ( 0, 6870, -5812, 0, 2720, 0) < 0) { break; } if (MoveTo (-1792, 5385, 6222, 0, 1100, 0) < 0) { break; } if (MoveTo ( 0, 2521, 11313, 0, 720, 0) < 0) { break; } if (MoveTo ( 1792, 5385, 6222, 0, 1100, 0) < 0) { break; } if (MoveTo ( 0, -5520, 12750, 0, 3960, 0) < 0) { break; } } while (0); } } // reset command buffer commandState = 0; }
//////////////////////////// Interrupt Handler//////////////////////////////// void InterruptHandler (void ) { u32 tmpValue; tmpValue = Xil_In32(XPAR_AXI_DMA_0_BASEADDR + 0x34); tmpValue = tmpValue | 0x1000; Xil_Out32 (XPAR_AXI_DMA_0_BASEADDR + 0x34, tmpValue); global_frame_counter++; }
void sobelfilterIP_RegWrite(unsigned int addr, unsigned int mask, unsigned int value) { // only write to reg if mask != 0x0 if ((mask | 0x0) != 0x0) { #if PLATFORM == XILINX_FPGA Xil_Out32(addr, (Xil_In32(addr) & ~mask) | value); // #elsif for other platforms #endif } }
static void RtcEventHandler(const XPfw_Module_t *ModPtr, u32 EventId) { fw_printf("MOD%d:EVENTID: %d\r\n", ModPtr->ModId, EventId); //XPfw_CorePrintStats(); if (XPFW_EV_RTC_SECONDS == EventId) { /* Ack the Int in RTC Module */ Xil_Out32(RTC_RTC_INT_STATUS, 1U); fw_printf("RTC: %d \r\n", Xil_In32(RTC_CURRENT_TIME)); } }
/**************************************************************************//** * @brief Writes data to an I2C slave. * * @param i2cAddr - The address of the I2C slave. * @param regAddr - Address of the I2C register to be read. * Must be set to -1 if it is not used. * @param txSize - Number of bytes to write to the slave. * @param txBuf - Buffer to store the data to be transmitted. * * @return Returns the number of bytes written. ******************************************************************************/ uint32_t I2C_Write_ps7(uint32_t i2cAddr, uint32_t regAddr, uint32_t txSize, uint8_t* txBuf) { uint32_t timeout = I2C_TIMEOUT; uint32_t cfgValue = 0x00; uint32_t txBufIndex = 0x00; /* Write to the Control Register to set up SCL Speed and addressing mode Set the MS, ACKEN, CLR_FIFO bits and clear the RW bit */ cfgValue = (0 << DIV_A) | (0x3f << DIV_B) | (1 << CLR_FIFO) | (0 << SLVMON) | (0 << HOLD) | (1 << ACK_EN) | (1 << NEA) | (1 << MS) | (0 << RW); Xil_Out32(axi_iic_baseaddr + HW_I2C_CONTROL_REG, cfgValue); // Clear all Interrupts Xil_Out32(axi_iic_baseaddr + HW_I2C_INTR_STATUS_REG, 0xFF); // Set the transfer size if(regAddr != -1) { Xil_Out32(axi_iic_baseaddr + HW_I2C_TX_SIZE_REG, txSize + 1); } else { Xil_Out32(axi_iic_baseaddr + HW_I2C_TX_SIZE_REG, txSize); } // Write the first byte of data to the I2C Data Register if(regAddr != -1) { Xil_Out32(axi_iic_baseaddr + HW_I2C_DATA_REG, regAddr); } else { Xil_Out32(axi_iic_baseaddr + HW_I2C_DATA_REG, txBuf[txBufIndex]); txBufIndex += 1; } // Write the rest of the data into the FIFO while(txBufIndex < txSize) { Xil_Out32(axi_iic_baseaddr + HW_I2C_DATA_REG, txBuf[txBufIndex]); txBufIndex += 1; } // Write the slave address into the I2C address register. This initiates the I2C Transfer. Xil_Out32(axi_iic_baseaddr + HW_I2C_ADDRESS_REG, i2cAddr); // Wait for data transmission to be complete while(((Xil_In32(axi_iic_baseaddr + HW_I2C_INTR_STATUS_REG) & 0x01) == 0x00) && (--timeout)); delay_us(I2C_DELAY); return(timeout ? txBufIndex : 0); }
/***************************************************************************//** * @brief adc_set_pnsel *******************************************************************************/ int32_t adc_set_pnsel(uint32_t ch, enum adc_pnsel sel) { uint32_t reg_data; reg_data = Xil_In32(CF_BASEADDR + ADC_REG_CHAN_CNTRL_3(ch)); reg_data &= ~ADC_ADC_PN_SEL(~0); reg_data |= ADC_ADC_PN_SEL(sel); Xil_Out32(CF_BASEADDR + ADC_REG_CHAN_CNTRL_3(ch), reg_data); return 0; }
// Starts the timer at given base address uint32_t intervalTimer_start_timer(uint32_t baseAddress) { // This stores the current configuration of bits at given address uint32_t tempBit = Xil_In32( baseAddress + INTERVALTIMER_TCSR0_ADDRESS); // This modifies the ENT0 bit without modifying the rest tempBit = tempBit | INTERVALTIMER_ENT0_BIT; Xil_Out32(baseAddress + INTERVALTIMER_TCSR0_ADDRESS , tempBit); return 0; }
/****************************************************************************** * @brief Timer Interrupt Handler * * @param None. * * @return None. ******************************************************************************/ void Ps7TimerIntrHandler(void) { char interrupt; interrupt = Xil_In32(TIMER_BASEADDR + 0x54); if((interrupt & 0x01) == 0x01) { TimerIntrFunction(); } }
int main() { int switch_state; int led = 0x00; init_platform(); print("Hello World\n\r"); while(1) { if(Xil_In32(XPAR_BTNS_5BITS_BASEADDR)) led |= 1; Xil_Out32(XPAR_LEDS_8BITS_BASEADDR,led); if(((led=led<<1)&0x100))led|=0x01; switch_state = Xil_In32(XPAR_SWS_8BITS_BASEADDR); printf("0x%X\n",switch_state); usleep(switch_state*100000); } return 0; }
/** * This function contains the implementation for disabling the level shifters * * @param N/A. * * @return N/A. * * @note None. * ******************************************************************************/ void XSlcr_DisableLevelShifters(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Disable the level shifters */ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); }
/** * This function contains the implementation for remapping the ocm memory region * * @param N/A. * * @return N/A. * * @note None. * ******************************************************************************/ void XOcm_Remap(void) { u32 RegVal; /* Unlock the slcr register access lock */ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); /* Map the ocm region to postbootrom state */ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); }
/***************************************************************************//** * @brief ADC delay. * * @return 0. *******************************************************************************/ u32 adc_delay(void) { u32 delay; u32 error; u32 lasterr; u32 startdelay; u32 stopdelay; lasterr = 1; startdelay = 32; stopdelay = 31; for (delay = 0; delay < 32; delay++) { adc_delay_1(delay); delay_ms(10); Xil_Out32((CF_BASEADDR + CF_REG_DATA_MONITOR), CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG); // writer ones to clear bits delay_ms(100); error = Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR) & (CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG); // read the status of ADC data monitoring if (error == 0) { if (lasterr == 1) { startdelay = delay; } lasterr = 0; } else { if (lasterr == 0) { stopdelay = delay; break; } lasterr = 1; } } if (startdelay > 31) { adc_delay_1(0); return(1); } delay = startdelay + ((stopdelay - startdelay)/2); xil_printf("adc_setup: setting zero error delay (%d)\n\r", delay); adc_delay_1(delay); return(0); }
void _shutdown_cpu(int cpu_id) { unsigned int reg; unlock_slcr(); reg = Xil_In32(ESAL_DP_SLCR_BASE + A9_CPU_SLCR_RESET_CTRL); /* Assert reset signal and stop clock to halt the core */ reg |= (A9_CPU_SLCR_CLK_STOP | A9_CPU_SLCR_RST) << cpu_id; Xil_Out32(ESAL_DP_SLCR_BASE + A9_CPU_SLCR_RESET_CTRL, reg); lock_slcr(); }
void vga_interrupt_handler(void *BaseAddress) { int i; //input = VGA_PERIPH_MEM_mReadMemory(XPAR_MY_PERIPHERAL_0_BASEADDR); input = Xil_In32(XPAR_RC5CONTROLLER_0_BASEADDR); input = rc5toInput(input); /* spaceship and projectiles signals */ if(spaceship_speed_cnt >= (spaceship_speed)) { spaceship_flag = 1; spaceship_speed_cnt = 0; } else spaceship_speed_cnt++; if(projectil_speed == PROJECTILE_SPEED) { projectil_flag = 1; projectil_speed = 0; } else projectil_speed++; /*************************************/ /* signals for movement of rows of invaders */ for(i = INIT_ROWS - 1 + level - 1; i >= 0; i--) { if(invader_speed == (INVADER_SPEED*(INIT_ROWS + level - 1 - i)) - (print_level-1)*3) { flag_row[i] = 1; if(i == 0) invader_speed = 0; } } invader_speed++; /*************************************/ if(shoot_flag != 0) { shoot_flag--; } if(counter == (30 - (level+8)*2)) { counter = 0; invader_shoot_flag = 1; } counter++; }