/* Read/write a pllcontrol reg */ u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val) { ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0, reg); return ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_data), mask, val); }
uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) { if (CHIPTYPE(sih->socitype) == SOCI_SB) return sb_corereg(sih, coreidx, regoff, mask, val); else if (CHIPTYPE(sih->socitype) == SOCI_AI) return ai_corereg(sih, coreidx, regoff, mask, val); else { ASSERT(0); return 0; } }
/* PMU PLL update */ void si_pmu_pllupd(struct si_pub *sih) { ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol), PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD); }