int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); if (bgate) { cgs_set_powergating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); cgs_set_clockgating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE); cz_enable_disable_vce_dpm(hwmgr, false); cz_dpm_powerdown_vce(hwmgr); cz_hwmgr->vce_power_gated = true; } else { cz_dpm_powerup_vce(hwmgr); cz_hwmgr->vce_power_gated = false; cgs_set_clockgating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE); cgs_set_powergating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); cz_dpm_update_vce_dpm(hwmgr); cz_enable_disable_vce_dpm(hwmgr, true); return 0; } return 0; }
int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating)) { if (cz_hwmgr->vce_power_gated != bgate) { if (bgate) { cgs_set_clockgating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); cgs_set_powergating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); cz_enable_disable_vce_dpm(hwmgr, false); cz_dpm_powerdown_vce(hwmgr); cz_hwmgr->vce_power_gated = true; } else { cz_dpm_powerup_vce(hwmgr); cz_hwmgr->vce_power_gated = false; cgs_set_powergating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); cgs_set_clockgating_state( hwmgr->device, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); cz_dpm_update_vce_dpm(hwmgr); cz_enable_disable_vce_dpm(hwmgr, true); return 0; } } } else { cz_hwmgr->vce_power_gated = bgate; cz_dpm_update_vce_dpm(hwmgr); cz_enable_disable_vce_dpm(hwmgr, !bgate); return 0; } if (!cz_hwmgr->vce_power_gated) cz_dpm_update_vce_dpm(hwmgr); return 0; }