/** * dwc2_set_default_params() - Set all core parameters to their * auto-detected default values. */ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) { struct dwc2_hw_params *hw = &hsotg->hw_params; struct dwc2_core_params *p = &hsotg->params; bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); dwc2_set_param_otg_cap(hsotg); dwc2_set_param_phy_type(hsotg); dwc2_set_param_speed(hsotg); dwc2_set_param_phy_utmi_width(hsotg); p->phy_ulpi_ddr = false; p->phy_ulpi_ext_vbus = false; p->enable_dynamic_fifo = hw->enable_dynamic_fifo; p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; p->i2c_enable = hw->i2c_enable; p->ulpi_fs_ls = false; p->ts_dline = false; p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); p->uframe_sched = true; p->external_id_pin_ctl = false; p->hibernation = false; p->max_packet_count = hw->max_packet_count; p->max_transfer_size = hw->max_transfer_size; p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; if ((hsotg->dr_mode == USB_DR_MODE_HOST) || (hsotg->dr_mode == USB_DR_MODE_OTG)) { p->host_dma = dma_capable; p->dma_desc_enable = false; p->dma_desc_fs_enable = false; p->host_support_fs_ls_low_power = false; p->host_ls_low_power_phy_clk = false; p->host_channels = hw->host_channels; p->host_rx_fifo_size = hw->rx_fifo_size; p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; } if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || (hsotg->dr_mode == USB_DR_MODE_OTG)) { p->g_dma = dma_capable; p->g_dma_desc = hw->dma_desc_enable; /* * The values for g_rx_fifo_size (2048) and * g_np_tx_fifo_size (1024) come from the legacy s3c * gadget driver. These defaults have been hard-coded * for some time so many platforms depend on these * values. Leave them as defaults for now and only * auto-detect if the hardware does not support the * default. */ p->g_rx_fifo_size = 2048; p->g_np_tx_fifo_size = 1024; dwc2_set_param_tx_fifo_sizes(hsotg); } }
static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) { int valid = 1; int phy_type = hsotg->params.phy_type; int speed = hsotg->params.speed; switch (speed) { case DWC2_SPEED_PARAM_HIGH: if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && (phy_type == DWC2_PHY_TYPE_PARAM_FS)) valid = 0; break; case DWC2_SPEED_PARAM_FULL: case DWC2_SPEED_PARAM_LOW: break; default: valid = 0; break; } if (!valid) dwc2_set_param_speed(hsotg); }
/** * dwc2_set_parameters() - Set all core parameters. * * @hsotg: Programming view of the DWC_otg controller * @params: The parameters to set */ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, const struct dwc2_core_params *params) { struct dwc2_hw_params *hw = &hsotg->hw_params; struct dwc2_core_params *p = &hsotg->params; bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); dwc2_set_param_otg_cap(hsotg, params->otg_cap); if ((hsotg->dr_mode == USB_DR_MODE_HOST) || (hsotg->dr_mode == USB_DR_MODE_OTG)) { dev_dbg(hsotg->dev, "Setting HOST parameters\n"); dwc2_set_param_bool(hsotg, &p->host_dma, false, "host-dma", true, false, dma_capable); } dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); dwc2_set_param_host_support_fs_ls_low_power(hsotg, params->host_support_fs_ls_low_power); dwc2_set_param_enable_dynamic_fifo(hsotg, params->enable_dynamic_fifo); dwc2_set_param_host_rx_fifo_size(hsotg, params->host_rx_fifo_size); dwc2_set_param_host_nperio_tx_fifo_size(hsotg, params->host_nperio_tx_fifo_size); dwc2_set_param_host_perio_tx_fifo_size(hsotg, params->host_perio_tx_fifo_size); dwc2_set_param_max_transfer_size(hsotg, params->max_transfer_size); dwc2_set_param_max_packet_count(hsotg, params->max_packet_count); dwc2_set_param_host_channels(hsotg, params->host_channels); dwc2_set_param_phy_type(hsotg, params->phy_type); dwc2_set_param_speed(hsotg, params->speed); dwc2_set_param_host_ls_low_power_phy_clk(hsotg, params->host_ls_low_power_phy_clk); dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); dwc2_set_param_phy_ulpi_ext_vbus(hsotg, params->phy_ulpi_ext_vbus); dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); dwc2_set_param_ts_dline(hsotg, params->ts_dline); dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); dwc2_set_param_en_multiple_tx_fifo(hsotg, params->en_multiple_tx_fifo); dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); dwc2_set_param_otg_ver(hsotg, params->otg_ver); dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); dwc2_set_param_hibernation(hsotg, params->hibernation); /* * Set devicetree-only parameters. These parameters do not * take any values from @params. */ if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || (hsotg->dr_mode == USB_DR_MODE_OTG)) { dev_dbg(hsotg->dev, "Setting peripheral device properties\n"); dwc2_set_gadget_dma(hsotg); /* * The values for g_rx_fifo_size (2048) and * g_np_tx_fifo_size (1024) come from the legacy s3c * gadget driver. These defaults have been hard-coded * for some time so many platforms depend on these * values. Leave them as defaults for now and only * auto-detect if the hardware does not support the * default. */ dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size, true, "g-rx-fifo-size", 2048, hw->rx_fifo_size, 16, hw->rx_fifo_size); dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size, true, "g-np-tx-fifo-size", 1024, hw->dev_nperio_tx_fifo_size, 16, hw->dev_nperio_tx_fifo_size); dwc2_set_param_tx_fifo_sizes(hsotg); } }