/** * __fimc_pipeline_close - disable the sensor clock and pipeline power * @fimc: fimc device terminating the pipeline * * Disable power of all subdevs in the pipeline and turn off the external * sensor clock. * Called with the graph mutex held. */ static int __fimc_pipeline_close(struct fimc_pipeline *p) { int ret = 0; if (p->subdevs[IDX_SENSOR]) { ret = fimc_pipeline_s_power(p, 0); fimc_md_set_camclk(p->subdevs[IDX_SENSOR], false); } return ret == -ENXIO ? 0 : ret; }
/** * __fimc_pipeline_shutdown - disable the sensor clock and pipeline power * @fimc: fimc device terminating the pipeline * * Disable power of all subdevs in the pipeline and turn off the external * sensor clock. * Called with the graph mutex held. */ int __fimc_pipeline_shutdown(struct fimc_dev *fimc) { int ret = 0; if (fimc->pipeline.sensor) { ret = fimc_pipeline_s_power(fimc, 0); fimc_md_set_camclk(fimc->pipeline.sensor, false); } return ret == -ENXIO ? 0 : ret; }
/** * __fimc_pipeline_open - update the pipeline information, enable power * of all pipeline subdevs and the sensor clock * @me: media entity to start graph walk with * @prepare: true to walk the current pipeline and acquire all subdevs * * Called with the graph mutex held. */ static int __fimc_pipeline_open(struct exynos_media_pipeline *ep, struct media_entity *me, bool prepare) { struct fimc_md *fmd = entity_to_fimc_mdev(me); struct fimc_pipeline *p = to_fimc_pipeline(ep); struct v4l2_subdev *sd; int ret; if (WARN_ON(p == NULL || me == NULL)) return -EINVAL; if (prepare) fimc_pipeline_prepare(p, me); sd = p->subdevs[IDX_SENSOR]; if (sd == NULL) return -EINVAL; /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) { ret = clk_prepare_enable(fmd->wbclk[CLK_IDX_WB_B]); if (ret < 0) return ret; } ret = fimc_md_set_camclk(sd, true); if (ret < 0) goto err_wbclk; ret = fimc_pipeline_s_power(p, 1); if (!ret) return 0; fimc_md_set_camclk(sd, false); err_wbclk: if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret; }
/** * __fimc_pipeline_initialize - update the pipeline information, enable power * of all pipeline subdevs and the sensor clock * @me: media entity to start graph walk with * @prep: true to acquire sensor (and csis) subdevs * * This function must be called with the graph mutex held. */ static int __fimc_pipeline_initialize(struct fimc_dev *fimc, struct media_entity *me, bool prep) { int ret; if (prep) fimc_pipeline_prepare(fimc, me); if (fimc->pipeline.sensor == NULL) return -EINVAL; ret = fimc_md_set_camclk(fimc->pipeline.sensor, true); if (ret) return ret; return fimc_pipeline_s_power(fimc, 1); }
/** * __fimc_pipeline_open - update the pipeline information, enable power * of all pipeline subdevs and the sensor clock * @me: media entity to start graph walk with * @prep: true to acquire sensor (and csis) subdevs * * This function must be called with the graph mutex held. */ static int __fimc_pipeline_open(struct fimc_pipeline *p, struct media_entity *me, bool prep) { int ret; if (prep) fimc_pipeline_prepare(p, me); if (p->subdevs[IDX_SENSOR] == NULL) return -EINVAL; ret = fimc_md_set_camclk(p->subdevs[IDX_SENSOR], true); if (ret) return ret; return fimc_pipeline_s_power(p, 1); }
/** * __fimc_pipeline_close - disable the sensor clock and pipeline power * @fimc: fimc device terminating the pipeline * * Disable power of all subdevs and turn the external sensor clock off. */ static int __fimc_pipeline_close(struct fimc_pipeline *p) { struct v4l2_subdev *sd = p ? p->subdevs[IDX_SENSOR] : NULL; struct fimc_md *fmd; int ret = 0; if (WARN_ON(sd == NULL)) return -EINVAL; if (p->subdevs[IDX_SENSOR]) { ret = fimc_pipeline_s_power(p, 0); fimc_md_set_camclk(sd, false); } fmd = entity_to_fimc_mdev(&sd->entity); /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; }
/** * __fimc_pipeline_close - disable the sensor clock and pipeline power * @fimc: fimc device terminating the pipeline * * Disable power of all subdevs and turn the external sensor clock off. */ static int __fimc_pipeline_close(struct exynos_media_pipeline *ep) { struct fimc_pipeline *p = to_fimc_pipeline(ep); struct v4l2_subdev *sd = p ? p->subdevs[IDX_SENSOR] : NULL; struct fimc_md *fmd; int ret; if (sd == NULL) { pr_warn("%s(): No sensor subdev\n", __func__); return 0; } ret = fimc_pipeline_s_power(p, 0); fimc_md_set_camclk(sd, false); fmd = entity_to_fimc_mdev(&sd->entity); /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */ if (!IS_ERR(fmd->wbclk[CLK_IDX_WB_B]) && p->subdevs[IDX_IS_ISP]) clk_disable_unprepare(fmd->wbclk[CLK_IDX_WB_B]); return ret == -ENXIO ? 0 : ret; }