static int gpu_set_clk_vol(struct kbase_device *kbdev, int clock, int voltage) { static int prev_clock = -1; struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; if (!platform) return -ENODEV; if ((clock > platform->table[platform->table_size-1].clock) || (clock < platform->table[0].clock)) { GPU_LOG(DVFS_ERROR, "Mismatch clock error (%d)\n", clock); return -1; } if (clock > prev_clock) { gpu_set_voltage(platform, voltage + platform->voltage_margin); #if SOC_NAME == 5260 set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif /* SOC_NAME */ gpu_set_clock(platform, clock); } else { gpu_set_clock(platform, clock); #if SOC_NAME == 5260 set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif /* SOC_NAME */ gpu_set_voltage(platform, voltage + platform->voltage_margin); } GPU_LOG(DVFS_INFO, "[G3D] clock changed [%d -> %d]\n", prev_clock, clock); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, prev_clock); prev_clock = clock; return 0; }
int gpu_regulator_init(struct exynos_context *platform) { int gpu_voltage = 0; g3d_regulator = regulator_get(NULL, "vdd_g3d"); if (IS_ERR(g3d_regulator)) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get vdd_g3d regulator, 0x%p\n", __func__, g3d_regulator); g3d_regulator = NULL; return -1; } gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000); if (gpu_voltage == 0) gpu_voltage = platform->gpu_default_vol; if (gpu_set_voltage(platform, gpu_voltage) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage); return -1; } if (platform->dvs_status) GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "dvs GPIO PMU status enable\n"); GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n"); return 0; }
static int gpu_set_clk_vol(struct kbase_device *kbdev, int clock, int voltage) { static int prev_clock = -1; struct exynos_context *platform = (struct exynos_context *)kbdev->platform_context; if (!platform) return -ENODEV; if ((clock > platform->table[platform->table_size-1].clock) || (clock < platform->table[0].clock)) { GPU_LOG(DVFS_ERROR, "Mismatch clock error (%d)\n", clock); return -1; } if (platform->voltage_margin) voltage = MAX(voltage + platform->voltage_margin, COLD_MINIMUM_VOL); if (clock > prev_clock) { gpu_set_voltage(platform, voltage); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_clock(platform, clock); #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ } else { #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ gpu_set_clock(platform, clock); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_voltage(platform, voltage); } GPU_LOG(DVFS_INFO, "[G3D]clk[%d -> %d], vol[%d + %d]\n", prev_clock, clock, voltage, platform->voltage_margin); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, prev_clock); prev_clock = clock; return 0; }
int gpu_regulator_init(struct exynos_context *platform) { int gpu_voltage = 0; g3d_regulator = regulator_get(NULL, "vdd_g3d"); if (IS_ERR(g3d_regulator)) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get vdd_g3d regulator, 0x%p\n", __func__, g3d_regulator); g3d_regulator = NULL; return -1; } if (platform->dvs_status) { dvs_en_regulator = regulator_get(NULL, "DVS_EN"); if (IS_ERR(dvs_en_regulator)) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get DVS_EN regulator, 0x%p\n", __func__, dvs_en_regulator); dvs_en_regulator = NULL; return -1; } if (gpu_enable_dvs_en_regulator(platform) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable dvs_en regulator\n", __func__); dvs_en_regulator = NULL; return -1; } if (gpu_disable_dvs_en_regulator(platform) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to disable dvs_en regulator\n", __func__); dvs_en_regulator = NULL; return -1; } platform->dvs_is_enabled = false; } gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000); if (gpu_voltage == 0) gpu_voltage = platform->gpu_default_vol; if (gpu_set_voltage(platform, gpu_voltage) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage); return -1; } GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n"); return 0; }
int gpu_regulator_init(struct exynos_context *platform) { int gpu_voltage = 0; #if 0 platform->g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(platform->g3d_regulator)) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get regulator, 0x%p\n", __func__, platform->g3d_regulator); platform->g3d_regulator = NULL; return -1; } if (gpu_regulator_enable(platform) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable regulator\n", __func__); platform->g3d_regulator = NULL; return -1; } #if 0 gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000); #else gpu_voltage = 0; #endif if (gpu_voltage == 0) gpu_voltage = platform->gpu_default_vol; if (gpu_set_voltage(platform, gpu_voltage) != 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage); return -1; } GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n"); return 0; }
int gpu_control_state_set(struct kbase_device *kbdev, gpu_control_state state, int param) { int ret = 0, voltage; #ifdef CONFIG_MALI_MIDGARD_DVFS unsigned long flags; #endif /* CONFIG_MALI_MIDGARD_DVFS */ struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; if (!platform) return -ENODEV; mutex_lock(&platform->gpu_clock_lock); switch (state) { case GPU_CONTROL_CLOCK_ON: ret = gpu_clock_on(platform); #ifdef GPU_EARLY_CLK_GATING break; case GPU_CONTROL_CLOCK_ON_POST: #endif /* GPU_EARLY_CLK_GATING*/ #ifdef CONFIG_MALI_MIDGARD_DVFS if (!kbdev->pm.metrics.timer_active) { spin_lock_irqsave(&kbdev->pm.metrics.lock, flags); kbdev->pm.metrics.timer_active = true; spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags); #if !defined(SLSI_SUBSTITUTE) hrtimer_start(&kbdev->pm.metrics.timer, HR_TIMER_DELAY_MSEC(platform->polling_speed), HRTIMER_MODE_REL); #else kbdev->pm.metrics.tlist.expires = jiffies + msecs_to_jiffies(platform->polling_speed); add_timer_on(&kbdev->pm.metrics.tlist, 0); #endif } gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, 0); #endif /* CONFIG_MALI_MIDGARD_DVFS */ break; #ifdef GPU_EARLY_CLK_GATING case GPU_CONTROL_CLOCK_OFF_POST: #else case GPU_CONTROL_CLOCK_OFF: #endif /* GPU_EARLY_CLK_GATING*/ #ifdef CONFIG_MALI_MIDGARD_DVFS if (platform->dvfs_status && kbdev->pm.metrics.timer_active) { spin_lock_irqsave(&kbdev->pm.metrics.lock, flags); kbdev->pm.metrics.timer_active = false; spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags); #if !defined(SLSI_SUBSTITUTE) hrtimer_cancel(&kbdev->pm.metrics.timer); #else del_timer(&kbdev->pm.metrics.tlist); #endif } gpu_pm_qos_command(platform, GPU_CONTROL_PM_QOS_RESET); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, platform->cur_clock); #endif /* CONFIG_MALI_MIDGARD_DVFS */ #ifdef GPU_EARLY_CLK_GATING break; case GPU_CONTROL_CLOCK_OFF: #endif /* GPU_EARLY_CLK_GATING*/ ret = gpu_clock_off(platform); break; case GPU_CONTROL_CHANGE_CLK_VOL: ret = gpu_set_clk_vol(kbdev, param, gpu_dvfs_handler_control(kbdev, GPU_HANDLER_DVFS_GET_VOLTAGE, param)); #ifdef CONFIG_MALI_MIDGARD_DVFS if (ret == 0) { ret = gpu_dvfs_handler_control(kbdev, GPU_HANDLER_DVFS_GET_LEVEL, platform->cur_clock); if (ret >= 0) { spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); platform->step = ret; spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); } else { GPU_LOG(DVFS_ERROR, "Invalid dvfs level returned [%d]\n", GPU_CONTROL_CHANGE_CLK_VOL); } } if (gpu_pm_qos_command(platform, GPU_CONTROL_PM_QOS_SET) < -1) GPU_LOG(DVFS_ERROR, "failed to set the PM_QOS\n"); #endif /* CONFIG_MALI_MIDGARD_DVFS */ break; case GPU_CONTROL_PREPARE_ON: #ifdef CONFIG_MALI_MIDGARD_DVFS spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); if (platform->dvfs_status && platform->wakeup_lock) platform->cur_clock = MALI_DVFS_START_FREQ; if (platform->min_lock > 0) platform->cur_clock = MAX(platform->min_lock, platform->cur_clock); if (platform->max_lock > 0) platform->cur_clock = MIN(platform->max_lock, platform->cur_clock); platform->down_requirement = platform->table[platform->step].stay_count; spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); #endif /* CONFIG_MALI_MIDGARD_DVFS */ break; case GPU_CONTROL_IS_POWER_ON: ret = gpu_is_power_on(); break; case GPU_CONTROL_SET_MARGIN: voltage = MAX(platform->table[platform->step].voltage + platform->voltage_margin, COLD_MINIMUM_VOL); gpu_set_voltage(platform, voltage); GPU_LOG(DVFS_DEBUG, "we set the voltage: %d\n", voltage); break; default: mutex_unlock(&platform->gpu_clock_lock); return -1; } mutex_unlock(&platform->gpu_clock_lock); return ret; }