/* this is a weak define that we are overriding */
void pin_mux_usb(void)
{
uchar val;
int ret;
/*
* This is a hack. This should be represented in DT using the
* vbus-gpio property. However, U-Boot's DT support doesn't
* support any GPIO controller other than the Tegra's yet.
*/
/* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
ret = i2c_set_bus_num(0);
if (ret)
printf("i2c_set_bus_num failed: %d\n", ret);
val = 0x03;
ret = i2c_write(0x20, 2, 1, &val, 1);
if (ret)
printf("i2c_write 0 0x20 2 failed: %d\n", ret);
val = 0xfc;
ret = i2c_write(0x20, 6, 1, &val, 1);
if (ret)
printf("i2c_write 0 0x20 6 failed: %d\n", ret);
}
int misc_init_r(void)
{
struct novena_eeprom_data data;
uchar *datap = (uchar *)&data;
const char *signature = "Novena";
int ret;
/* If 'ethaddr' is already set, do nothing. */
if (getenv("ethaddr"))
return 0;
/* EEPROM is at bus 2. */
ret = i2c_set_bus_num(2);
if (ret) {
puts("Cannot select EEPROM I2C bus.\n");
return 0;
}
/* EEPROM is at address 0x56. */
ret = eeprom_read(0x56, 0, datap, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
return 0;
}
/* Check EEPROM signature. */
if (memcmp(data.signature, signature, 6)) {
puts("Invalid I2C EEPROM signature.\n");
return 0;
}
/* Set ethernet address from EEPROM. */
eth_setenv_enetaddr("ethaddr", data.mac);
return ret;
}
/*
* Routine: get_board_revision
* Description: Returns the board revision
*/
int get_board_revision(void)
{
int revision;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
unsigned char data;
/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
/* these boards should return a revision number of 0 */
/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
i2c_set_bus_num(TWL4030_I2C_BUS);
data = 0x01;
i2c_write(0x4B, 0x29, 1, &data, 1);
data = 0x0c;
i2c_write(0x4B, 0x2b, 1, &data, 1);
i2c_read(0x4B, 0x2a, 1, &data, 1);
#endif
if (!gpio_request(112, "") &&
!gpio_request(113, "") &&
!gpio_request(115, "")) {
gpio_direction_input(112);
gpio_direction_input(113);
gpio_direction_input(115);
revision = gpio_get_value(115) << 2 |
gpio_get_value(113) << 1 |
gpio_get_value(112);
} else {
puts("Error: unable to acquire board revision GPIOs\n");
revision = -1;
}
return revision;
}
int last_stage_init(void)
{
int slaves;
unsigned int k;
unsigned int mux_ch;
unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
bool hw_type_cat = pca9698_get_value(0x20, 18);
bool ch0_sgmii2_present = false;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 9, 1);
ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
}
}
pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
udelay(10);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
MCFPGA_RESET_N);
}
if (hw_type_cat) {
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
bb_miiphy_write);
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_sgmii2_present)
continue;
setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
}
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
ioep_fpga_print_info(0);
if (!adv7611_probe(0))
printf(" Advantiv ADV7611 HDMI Receiver\n");
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(0))
osd_probe(0);
#endif
#ifdef CONFIG_STRIDER_CPU
ch7301_probe(0, false);
#endif
if (slaves <= 0)
return 0;
mclink_fpgacount = slaves;
for (k = 1; k <= slaves; ++k) {
ioep_fpga_print_info(k);
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(k))
osd_probe(k);
#endif
#ifdef CONFIG_STRIDER_CPU
FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
if (!adv7611_probe(k))
printf(" Advantiv ADV7611 HDMI Receiver\n");
ch7301_probe(k, false);
#endif
if (hw_type_cat) {
miiphy_register(bb_miiphy_buses[k].name,
bb_miiphy_read, bb_miiphy_write);
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
i2c_set_bus_num(strider_fans[k].bus);
init_fan_controller(strider_fans[k].addr);
}
return 0;
}
static int detect_i2c(struct display_info_t const *dev)
{
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
int s5m8767_enable_32khz_cp(void)
{
i2c_set_bus_num(0);
return s5m8767_enablereg(S5M8767_EN32KHZ_CP, S5M8767_REG_ENABLE);
}
static int setup_pmic_voltages(void)
{
unsigned char value, rev_id = 0;
i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_DEVICEID, 1, &value, 1)) {
printf("Read device ID error!\n");
return -1;
}
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_REVID, 1, &rev_id, 1)) {
printf("Read Rev ID error!\n");
return -1;
}
printf("Found PFUZE100! deviceid 0x%x, revid 0x%x\n", value, rev_id);
if (setup_pmic_mode(value & 0xf)) {
printf("setup pmic mode error!\n");
return -1;
}
/* set SW1AB standby volatage 0.975V */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
printf("Read SW1ABSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(9750);
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABSTBY, 1, &value, 1)) {
printf("Set SW1ABSTBY error!\n");
return -1;
}
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
printf("Read SW1ABCONFIG error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1ABCONF, 1, &value, 1)) {
printf("Set SW1ABCONFIG error!\n");
return -1;
}
/* set SW1C standby volatage 0.975V */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
printf("Read SW1CSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(9750);
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CSTBY, 1, &value, 1)) {
printf("Set SW1CSTBY error!\n");
return -1;
}
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
printf("Read SW1CCONFIG error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_SW1CCONF, 1, &value, 1)) {
printf("Set SW1CCONFIG error!\n");
return -1;
}
/* Enable power of VGEN5 3V3, needed for SD3 */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
printf("Read VGEN5CTL error!\n");
return -1;
}
value &= ~0x1F;
value |= 0x1F;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE100_VGEN5CTL, 1, &value, 1)) {
printf("Set VGEN5CTL error!\n");
return -1;
}
}
return 0;
}
static int setup_pmic_voltages(void)
{
unsigned char value, rev_id = 0;
i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_DEVICEID, 1, &value, 1)) {
printf("Read device ID error!\n");
return -1;
}
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_REVID, 1, &rev_id, 1)) {
printf("Read Rev ID error!\n");
return -1;
}
printf("Found PFUZE300! deviceid 0x%x, revid 0x%x\n", value, rev_id);
/* disable Low Power Mode during standby mode */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
printf("Read LDOCTL error!\n");
return -1;
}
value |= 0x1;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
printf("Set LDOCTL error!\n");
return -1;
}
/* SW1A/1B mode set to APS/APS */
value = 0x8;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1AMODE, 1, &value, 1)) {
printf("Set PFUZE300_SW1AMODE error!\n");
return -1;
}
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1BMODE, 1, &value, 1)) {
printf("Set PFUZE300_SW1BMODE error!\n");
return -1;
}
/* SW1A/1B standby voltage set to 1.025V */
value = 0xd;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1ASTBY, 1, &value, 1)) {
printf("Set PFUZE300_SW1ASTBY error!\n");
return -1;
}
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1BSTBY, 1, &value, 1)) {
printf("Set PFUZE300_SW1BSTBY error!\n");
return -1;
}
/* decrease SW1B normal voltage to 0.975V */
if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1BVOLT, 1, &value, 1)) {
printf("Read SW1BVOLT error!\n");
return -1;
}
value &= ~0x1f;
value |= 0x0b;
if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE300_SW1BVOLT, 1, &value, 1)) {
printf("Set SW1BVOLT error!\n");
return -1;
}
}
return 0;
}
static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct rtc_time tm;
int rcode = 0;
int old_bus __maybe_unused;
/* switch to correct I2C bus */
#ifdef CONFIG_DM_RTC
struct udevice *dev;
rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
if (rcode) {
printf("Cannot find RTC: err=%d\n", rcode);
return CMD_RET_FAILURE;
}
#elif defined(CONFIG_SYS_I2C)
old_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
#else
old_bus = I2C_GET_BUS();
I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
#endif
switch (argc) {
case 2: /* set date & time */
if (strcmp(argv[1],"reset") == 0) {
puts ("Reset RTC...\n");
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_reset(dev);
if (!rcode)
rcode = dm_rtc_set(dev, &default_tm);
#else
rtc_reset();
rcode = rtc_set(&default_tm);
#endif
if (rcode)
puts("## Failed to set date after RTC reset\n");
} else {
/* initialize tm with current time */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
#endif
if (!rcode) {
/* insert new date & time */
if (mk_date(argv[1], &tm) != 0) {
puts ("## Bad date format\n");
break;
}
/* and write to RTC */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_set(dev, &tm);
#else
rcode = rtc_set(&tm);
#endif
if (rcode) {
printf("## Set date failed: err=%d\n",
rcode);
}
} else {
puts("## Get date failed\n");
}
}
/* FALL TROUGH */
case 1: /* get date & time */
#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
#else
rcode = rtc_get(&tm);
#endif
if (rcode) {
puts("## Get date failed\n");
break;
}
printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
(tm.tm_wday<0 || tm.tm_wday>6) ?
"unknown " : RELOC(weekdays[tm.tm_wday]),
tm.tm_hour, tm.tm_min, tm.tm_sec);
break;
default:
rcode = CMD_RET_USAGE;
}
/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
i2c_set_bus_num(old_bus);
#elif !defined(CONFIG_DM_RTC)
I2C_SET_BUS(old_bus);
#endif
return rcode ? CMD_RET_FAILURE : 0;
}
/*
* i2c_init_all():
*
* not longer needed, will deleted. Actual init the SPD_BUS
* for compatibility.
* i2c_adap[] must be initialized beforehead with function pointers and
* data, including speed and slaveaddr.
*/
void i2c_init_all(void)
{
i2c_init_board();
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
return;
}
/* setup board specific PMIC */
void setup_pmic(void)
{
struct pmic *p;
u32 reg;
i2c_set_bus_num(CONFIG_I2C_PMIC);
/* configure PFUZE100 PMIC */
if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
power_pfuze100_init(CONFIG_I2C_PMIC);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set VGEN1 to 1.5V and enable */
pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
reg &= ~(LDO_VOL_MASK);
reg |= (LDOA_1_50V | LDO_EN);
pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
/* Set SWBST to 5.0V and enable */
pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
}
}
/* configure LTC3676 PMIC */
else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
power_ltc3676_init(CONFIG_I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
/*
* set board-specific scalar for max CPU frequency
* per CPU based on the LDO enabled Operating Ranges
* defined in the respective IMX6DQ and IMX6SDL
* datasheets. The voltage resulting from the R1/R2
* feedback inputs on Ventana is 1308mV. Note that this
* is a bit shy of the Vmin of 1350mV in the datasheet
* for LDO enabled mode but is as high as we can go.
*
* We will rely on an OS kernel driver to properly
* regulate these per CPU operating point and use LDO
* bypass mode when using the higher frequency
* operating points to compensate as LDO bypass mode
* allows the rails be 125mV lower.
*/
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW1 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
}
}
}
int last_stage_init(void)
{
int slaves;
uint k;
uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
u16 fpga_features;
bool hw_type_cat = pca9698_get_value(0x20, 20);
bool ch0_rgmii2_present;
FPGA_GET_REG(0, fpga_features, &fpga_features);
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 10, 1);
pca9698_direction_output(0x20, 11, 1);
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
uint ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %u\n", k);
break;
}
}
pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
udelay(10);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
MCFPGA_RESET_N);
}
if (hw_type_cat) {
uint mux_ch;
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_rgmii2_present)
continue;
setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
}
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
ioep_fpga_print_info(0);
osd_probe(0);
#ifdef CONFIG_SYS_OSD_DH
osd_probe(4);
#endif
if (slaves <= 0)
return 0;
mclink_fpgacount = slaves;
for (k = 1; k <= slaves; ++k) {
FPGA_GET_REG(k, fpga_features, &fpga_features);
ioep_fpga_print_info(k);
osd_probe(k);
#ifdef CONFIG_SYS_OSD_DH
osd_probe(k + 4);
#endif
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
i2c_set_bus_num(hrcon_fans[k].bus);
init_fan_controller(hrcon_fans[k].addr);
}
return 0;
}
static void tuna_set_led(int color) {
tuna_clear_i2c4();
i2c_set_bus_num(3);
an30259_set_led(TUNA_AN30259_ADDR, color);
i2c_set_bus_num(0);
}
int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const uint8_t *dout, int dout_len,
uint8_t **dinp, int din_len)
{
int old_bus = 0;
/* version8, cmd8, arglen8, out8[dout_len], csum8 */
int out_bytes = dout_len + 4;
/* response8, arglen8, in8[din_len], checksum8 */
int in_bytes = din_len + 3;
uint8_t *ptr;
/* Receive input data, so that args will be dword aligned */
uint8_t *in_ptr;
int ret;
old_bus = i2c_get_bus_num();
/*
* Sanity-check I/O sizes given transaction overhead in internal
* buffers.
*/
if (out_bytes > sizeof(dev->dout)) {
debug("%s: Cannot send %d bytes\n", __func__, dout_len);
return -1;
}
if (in_bytes > sizeof(dev->din)) {
debug("%s: Cannot receive %d bytes\n", __func__, din_len);
return -1;
}
assert(dout_len >= 0);
assert(dinp);
/*
* Copy command and data into output buffer so we can do a single I2C
* burst transaction.
*/
ptr = dev->dout;
/*
* in_ptr starts of pointing to a dword-aligned input data buffer.
* We decrement it back by the number of header bytes we expect to
* receive, so that the first parameter of the resulting input data
* will be dword aligned.
*/
in_ptr = dev->din + sizeof(int64_t);
if (!dev->cmd_version_is_supported) {
/* Send an old-style command */
*ptr++ = cmd;
out_bytes = dout_len + 1;
in_bytes = din_len + 2;
in_ptr--; /* Expect just a status byte */
} else {
*ptr++ = EC_CMD_VERSION0 + cmd_version;
*ptr++ = cmd;
*ptr++ = dout_len;
in_ptr -= 2; /* Expect status, length bytes */
}
memcpy(ptr, dout, dout_len);
ptr += dout_len;
if (dev->cmd_version_is_supported)
*ptr++ = (uint8_t)
cros_ec_calc_checksum(dev->dout, dout_len + 3);
/* Set to the proper i2c bus */
if (i2c_set_bus_num(dev->bus_num)) {
debug("%s: Cannot change to I2C bus %d\n", __func__,
dev->bus_num);
return -1;
}
/* Send output data */
cros_ec_dump_data("out", -1, dev->dout, out_bytes);
ret = i2c_write(dev->addr, 0, 0, dev->dout, out_bytes);
if (ret) {
debug("%s: Cannot complete I2C write to 0x%x\n",
__func__, dev->addr);
ret = -1;
}
if (!ret) {
ret = i2c_read(dev->addr, 0, 0, in_ptr, in_bytes);
if (ret) {
debug("%s: Cannot complete I2C read from 0x%x\n",
__func__, dev->addr);
ret = -1;
}
}
/* Return to original bus number */
i2c_set_bus_num(old_bus);
if (ret)
return ret;
if (*in_ptr != EC_RES_SUCCESS) {
debug("%s: Received bad result code %d\n", __func__, *in_ptr);
return -(int)*in_ptr;
}
if (dev->cmd_version_is_supported) {
int len, csum;
len = in_ptr[1];
if (len + 3 > sizeof(dev->din)) {
debug("%s: Received length %#02x too large\n",
__func__, len);
return -1;
}
csum = cros_ec_calc_checksum(in_ptr, 2 + len);
if (csum != in_ptr[2 + len]) {
debug("%s: Invalid checksum rx %#02x, calced %#02x\n",
__func__, in_ptr[2 + din_len], csum);
return -1;
}
din_len = min(din_len, len);
cros_ec_dump_data("in", -1, in_ptr, din_len + 3);
} else {
cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes);
}
/* Return pointer to dword-aligned input data, if any */
*dinp = dev->din + sizeof(int64_t);
return din_len;
}
int misc_init_r(void)
{
u32 keys;
char *s;
int want_recovery;
/* we use bus I2C-0 for the on-board eeprom */
i2c_set_bus_num(0);
/* setup GPIO directions and initial values */
gpio_configure();
/*
* check the GPIO keyboard,
* enforced start of the recovery when
* - the appropriate keys were pressed
* - a previous installation was aborted or has failed
* - "some" external software told us to
*/
want_recovery = 0;
keys = gpio_querykbd();
printf("GPIO keyboard status [0x%08X]\n", keys);
/* XXX insist in the _exact_ combination? */
if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
printf("GPIO keyboard requested RECOVERY\n");
/* XXX TODO
* refine the logic to detect the first keypress, and
* wait to recheck IF it was the recovery combination?
*/
want_recovery = 1;
}
s = getenv("install_in_progress");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation aborted, running RECOVERY\n");
want_recovery = 1;
}
s = getenv("install_failed");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation FAILED, running RECOVERY\n");
want_recovery = 1;
}
s = getenv("want_recovery");
if ((s != NULL) && (*s != '\0')) {
printf("running RECOVERY according to the request\n");
want_recovery = 1;
}
if (want_recovery)
setenv("bootcmd", "run recovery");
/*
* boot the recovery system without waiting; boot the
* production system without waiting by default, only
* insert a pause (to provide a chance to get a prompt)
* when GPIO keys were pressed during power on
*/
if (want_recovery)
setenv("bootdelay", "0");
else if (!keys)
setenv("bootdelay", "0");
else
setenv("bootdelay", "2");
/* get the ethernet MAC from I2C EEPROM */
mac_read_from_eeprom();
return 0;
}
static inline void I2C_SET_BUS(unsigned int bus)
{
if (I2C_MULTI_BUS)
i2c_set_bus_num(bus);
}
int last_stage_init(void)
{
int slaves;
unsigned int k;
unsigned int mux_ch;
unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
#ifdef CONFIG_STRIDER_CPU
unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
#ifdef CONFIG_STRIDER_CON_DP
bool is_dh = pca9698_get_value(0x20, 25);
#endif
bool ch0_sgmii2_present = false;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 10, 1);
pca9698_direction_output(0x20, 11, 1);
ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
unsigned int ctr = 0;
unsigned char *mclink_controllers = mclink_controllers_dvi;
#ifdef CONFIG_STRIDER_CPU
if (i2c_probe(mclink_controllers[k])) {
mclink_controllers = mclink_controllers_dp;
if (i2c_probe(mclink_controllers[k]))
continue;
}
#else
if (i2c_probe(mclink_controllers[k]))
continue;
#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
}
}
pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
udelay(10);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
MCFPGA_RESET_N);
}
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_sgmii2_present)
continue;
setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
}
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
ioep_fpga_print_info(0);
if (!adv7611_probe(0))
printf(" Advantiv ADV7611 HDMI Receiver\n");
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(0))
osd_probe(0);
#endif
#ifdef CONFIG_STRIDER_CON_DP
if (ioep_fpga_has_osd(0)) {
osd_probe(0);
if (is_dh)
osd_probe(4);
}
#endif
#ifdef CONFIG_STRIDER_CPU
ch7301_probe(0, false);
dp501_probe(0, false);
#endif
if (slaves <= 0)
return 0;
mclink_fpgacount = slaves;
#ifdef CONFIG_STRIDER_CPU
/* get ADV7611 out of reset, power up DP501, give some time to wakeup */
for (k = 1; k <= slaves; ++k)
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
udelay(500000);
#endif
for (k = 1; k <= slaves; ++k) {
ioep_fpga_print_info(k);
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(k))
osd_probe(k);
#endif
#ifdef CONFIG_STRIDER_CON_DP
if (ioep_fpga_has_osd(k)) {
osd_probe(k);
if (is_dh)
osd_probe(k + 4);
}
#endif
#ifdef CONFIG_STRIDER_CPU
if (!adv7611_probe(k))
printf(" Advantiv ADV7611 HDMI Receiver\n");
ch7301_probe(k, false);
dp501_probe(k, false);
#endif
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
i2c_set_bus_num(strider_fans[k].bus);
init_fan_controller(strider_fans[k].addr);
}
return 0;
}
void pmu_write(uchar reg, uchar data)
{
i2c_set_bus_num(4); /* PMU is on bus 4 */
i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
}
static void sunxi_mode_set(const struct ctfb_res_modes *mode,
unsigned int address)
{
int __maybe_unused clk_div, clk_double;
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_tve_reg * __maybe_unused const tve =
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
switch (sunxi_display.monitor) {
case sunxi_monitor_none:
break;
case sunxi_monitor_dvi:
case sunxi_monitor_hdmi:
#ifdef CONFIG_VIDEO_HDMI
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
sunxi_hdmi_mode_set(mode, clk_div, clk_double);
sunxi_composer_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_hdmi_enable();
#endif
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
/*
* The anx9804 needs 1.8V from eldo3, we do this here
* and not via CONFIG_AXP_ELDO3_VOLT from board_init()
* to avoid turning this on when using hdmi output.
*/
axp_set_eldo(3, 1800);
anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
ANX9804_DATA_RATE_1620M,
sunxi_display.depth);
}
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
unsigned int orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
i2c_set_bus_num(orig_i2c_bus);
}
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon0_mode_set(mode, false);
sunxi_composer_enable();
lcdc_enable(lcdc, sunxi_display.depth);
#ifdef CONFIG_VIDEO_LCD_SSD2828
sunxi_ssd2828_init(mode);
#endif
sunxi_lcdc_backlight_enable();
break;
case sunxi_monitor_vga:
#ifdef CONFIG_VIDEO_VGA
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
sunxi_tvencoder_mode_set();
sunxi_composer_enable();
lcdc_enable(lcdc, sunxi_display.depth);
tvencoder_enable(tve);
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon0_mode_set(mode, true);
sunxi_composer_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_vga_external_dac_enable();
#endif
break;
case sunxi_monitor_composite_pal:
case sunxi_monitor_composite_ntsc:
case sunxi_monitor_composite_pal_m:
case sunxi_monitor_composite_pal_nc:
#ifdef CONFIG_VIDEO_COMPOSITE
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
sunxi_tvencoder_mode_set();
sunxi_composer_enable();
lcdc_enable(lcdc, sunxi_display.depth);
tvencoder_enable(tve);
#endif
break;
}
}
int early_board_init(void)
{
uint8_t val;
/* Disable USB power */
gpio_direction_output(1, 1);
gpio_direction_output(2, 1);
gpio_direction_input(3); /* SD/MMC Write Protect */
gpio_direction_input(2); /* SD/MMC Card Detect */
mdelay(10);
if (PCA953X_DIR_IN != 0)
val = 0xff;
else
val = 0;
/* Make all pins inputs */
pca953x_set_dir(0, 0x20, 0xff, val);
/* Set output GPIOs 0-1, 4-7 */
val = (val & ~(1 << 0)) | PCA953X_DIR_OUT << 0;
val = (val & ~(1 << 1)) | PCA953X_DIR_OUT << 1;
val = (val & ~(1 << 2)) | PCA953X_DIR_IN << 2;
val = (val & ~(1 << 3)) | PCA953X_DIR_IN << 3;
val = (val & ~(1 << 4)) | PCA953X_DIR_OUT << 4;
val = (val & ~(1 << 5)) | PCA953X_DIR_OUT << 5;
val = (val & ~(1 << 6)) | PCA953X_DIR_OUT << 6;
val = (val & ~(1 << 7)) | PCA953X_DIR_OUT << 7;
pca953x_set_dir(0, 0x21, 0xff, val);
/* Put PHYs in reset */
pca953x_set_val(0, 0x21, 1 << 4, 0x00);
mdelay(10);
/* Take PHY out of reset */
pca953x_set_val(0, 0x21, 1 << 4, 1 << 4);
/* Populate global data from eeprom */
octeon_board_get_clock_info(SFF7000_DEF_DRAM_FREQ);
octeon_board_get_descriptor(CVMX_BOARD_TYPE_SFF7000, 1, 0);
/* Enable temperature and fan monitoring */
i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM);
val = i2c_reg_read(CONFIG_SYS_I2C_DTT_ADDR, 0);
/* Invert output, turn on tach, 2-wire analog and enable monitoring */
val |= 0xd;
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 0, val);
val = i2c_reg_read(CONFIG_SYS_I2C_DTT_ADDR, 1);
/* Turn off tach 2 and remote 2 temperature sensor */
val &= ~0x48;
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 1, val);
/* Enable fan filtering for fan 1 */
val = i2c_reg_read(CONFIG_SYS_I2C_DTT_ADDR, 0x23);
val |= 1;
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 0x23, val);
/* 800ms spin-up, 93.5KHz PWM, lowest speed 2647RPM */
val = 0x3b;
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 0x20, val);
val = 0x63; /* CPU fan enable temp 48C, range starts at 40C */
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 0x25, val);
val = 0x52;
/* PWM for fan 1 starts at 14%, 33% for fan 2 */
i2c_reg_write(CONFIG_SYS_I2C_DTT_ADDR, 0x25, val);
/* CN63XX has a fixed 50 MHz reference clock */
gd->arch.ddr_ref_hertz = 50000000;
octeon_board_get_mac_addr();
return 0;
}
int status_init(void)
{
isXM = (get_board_revision() == REVISION_XM);
i2c_set_bus_num(TWL4030_I2C_BUS);
if(isXM) {
/* Set VAUX1 to 3.3V for GTA04E display board */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
udelay(5000);
}
#if !defined(CONFIG_OMAP3_GTA04) // we assume that a GTA04 always has a TCA6507
if(i2c_set_bus_num(TCA6507_BUS))
{
printf ("could not select I2C2\n");
return 1;
}
hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
#endif
if(!hasTCA6507) {
if(isXM) { // XM has scrambled dss assignment with respect to default ball names
MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M4)); /*GPIO */
}
else {
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M4)); /*GPIO */
}
omap_request_gpio(GPIO_LED_AUX_GREEN);
omap_request_gpio(GPIO_LED_AUX_RED);
omap_request_gpio(GPIO_LED_POWER_GREEN);
omap_request_gpio(GPIO_LED_POWER_RED);
omap_request_gpio(GPIO_LED_VIBRA);
omap_request_gpio(GPIO_LED_UNUSED);
if(GPIO_POWER >= 0)
omap_request_gpio(GPIO_POWER);
}
else {
// initialize I2C controller
}
if(GPIO_AUX >= 0)
omap_request_gpio(GPIO_AUX);
if(GPIO_POWER >= 0)
omap_request_gpio(GPIO_POWER);
if(GPIO_GPSEXT >= 0)
omap_request_gpio(GPIO_GPSEXT);
if(GPIO_PENIRQ >= 0)
omap_request_gpio(GPIO_PENIRQ);
if(GPIO_KEYIRQ >= 0)
omap_request_gpio(GPIO_KEYIRQ);
if(!hasTCA6507) {
omap_set_gpio_direction(GPIO_LED_AUX_GREEN, 0); // output
omap_set_gpio_direction(GPIO_LED_AUX_RED, 0); // output
omap_set_gpio_direction(GPIO_LED_POWER_GREEN, 0); // output
omap_set_gpio_direction(GPIO_LED_POWER_RED, 0); // output
omap_set_gpio_direction(GPIO_LED_VIBRA, 0); // output
omap_set_gpio_direction(GPIO_LED_UNUSED, 0); // output
}
if(GPIO_AUX >= 0)
omap_set_gpio_direction(GPIO_AUX, 1); // input
if(GPIO_POWER >= 0)
omap_set_gpio_direction(GPIO_POWER, 1); // input
if(GPIO_GPSEXT >= 0)
omap_set_gpio_direction(GPIO_GPSEXT, 1); // input
if(GPIO_PENIRQ >= 0)
omap_set_gpio_direction(GPIO_PENIRQ, 1); // input
if(GPIO_KEYIRQ >= 0)
omap_set_gpio_direction(GPIO_KEYIRQ, 1); // input
// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
return 0;
}
int status_init(void)
{
extern int isXM(void);
i2c_set_bus_num(TWL4030_I2C_BUS);
thisIsXM = isXM();
if(thisIsXM) {
/* Set VAUX1 to 3.3V for GTA04E display board */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
udelay(5000);
}
#if CHECK_TCA6507
if(i2c_set_bus_num(TCA6507_BUS))
{ // check if we have a tca
printf ("could not select I2C2 to probe for TCA6507\n");
return 1;
}
hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
#endif
if(!hasTCA6507) { // reuse DSS pins
if(thisIsXM) { // XM has scrambled dss assignment with respect to default ball names
MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M4)); /*GPIO */
}
else {
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M4)); /*GPIO */
}
gpio_request(GPIO_LED_AUX_GREEN, "green-aux");
gpio_request(GPIO_LED_AUX_RED, "red-aux");
gpio_request(GPIO_LED_POWER_GREEN, "green-power");
gpio_request(GPIO_LED_POWER_RED, "red-power");
gpio_request(GPIO_LED_VIBRA, "vibra");
gpio_request(GPIO_LED_UNUSED, "unused");
if(GPIO_POWER >= 0)
gpio_request(GPIO_POWER, "power");
}
else {
// initialize I2C controller
}
if(GPIO_AUX >= 0)
gpio_request(GPIO_AUX, "aus");
if(GPIO_POWER >= 0)
gpio_request(GPIO_POWER, "power");
if(GPIO_GPSEXT >= 0)
gpio_request(GPIO_GPSEXT, "ext-gps");
if(GPIO_PENIRQ >= 0)
gpio_request(GPIO_PENIRQ, "penirq");
if(GPIO_KEYIRQ >= 0)
gpio_request(GPIO_KEYIRQ, "keyirq");
if(!hasTCA6507) {
gpio_direction_output(GPIO_LED_AUX_GREEN, 0); // output
gpio_direction_output(GPIO_LED_AUX_RED, 0); // output
gpio_direction_output(GPIO_LED_POWER_GREEN, 0); // output
gpio_direction_output(GPIO_LED_POWER_RED, 0); // output
gpio_direction_output(GPIO_LED_VIBRA, 0); // output
gpio_direction_output(GPIO_LED_UNUSED, 0); // output
}
if(GPIO_AUX >= 0)
gpio_direction_input(GPIO_AUX); // input
if(GPIO_POWER >= 0)
gpio_direction_input(GPIO_POWER); // input
if(GPIO_GPSEXT >= 0)
gpio_direction_input(GPIO_GPSEXT); // input
if(GPIO_PENIRQ >= 0)
gpio_direction_input(GPIO_PENIRQ); // input
if(GPIO_KEYIRQ >= 0)
gpio_direction_input(GPIO_KEYIRQ); // input
// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
return 0;
}
int pib_init(void)
{
u8 val8;
u8 orig_i2c_bus;
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
/* Assign PIB PMC slot to desired PCI bus */
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(CONFIG_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
eieio();
#if defined(CONFIG_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x20, 0x2, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x20, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x21, 0x6, 1, &val8, 1);
i2c_write(0x21, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x21, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x21, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC1\n");
#endif
#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
}
/**
* anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
*
* This function will init an anx9804 parallel lcd to dp bridge chip
* using the passed in parameters.
*
* @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
* @lanes: Number of displayport lanes to use
* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
* @bpp: Bits per pixel, must be 18 or 24
*/
void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
unsigned int orig_i2c_bus = i2c_get_bus_num();
u8 c, colordepth;
int i;
i2c_set_bus_num(i2c_bus);
if (bpp == 18)
colordepth = 0x00; /* 6 bit */
else
colordepth = 0x10; /* 8 bit */
/* Reset */
i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
mdelay(100);
i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
/* Write 0 to the powerdown reg (powerup everything) */
i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
if (c != 0x98) {
printf("Error anx9804 chipid mismatch\n");
i2c_set_bus_num(orig_i2c_bus);
return;
}
for (i = 0; i < 100; i++) {
c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
break;
mdelay(5);
}
if (i == 100)
printf("Error anx9804 clock is not stable\n");
i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
/* Set a bunch of analog related register values */
i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
/* Force HPD */
i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
/* Power up and configure lanes */
i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
/* Reset AUX CH */
i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
ANX9804_RST_CTRL2_AC_MODE);
/* Powerdown audio and some other unused bits */
i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
i2c_reg_write(0x38, 0xa7, 0x00);
/* Set data-rate / lanes */
i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
/* Link training */
i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
ANX9804_LINK_TRAINING_CTRL_EN);
mdelay(5);
for (i = 0; i < 100; i++) {
c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
if ((c & 0x01) == 0)
break;
mdelay(5);
}
if(i == 100) {
printf("Error anx9804 link training timeout\n");
i2c_set_bus_num(orig_i2c_bus);
return;
}
/* Enable */
i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */
i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
i2c_set_bus_num(orig_i2c_bus);
}
int misc_init_r(void)
{
u32 keys;
char *s;
int want_recovery;
/* we use bus I2C-0 for the on-board eeprom */
i2c_set_bus_num(0);
/* setup GPIO directions and initial values */
gpio_configure();
/*
* enforce the start of the recovery system when
* - the appropriate keys were pressed
* - "some" external software told us to
* - a previous installation was aborted or has failed
*/
want_recovery = 0;
keys = gpio_querykbd();
if (gpio_diag)
printf("GPIO keyboard status [0x%02X]\n", keys);
if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
printf("detected recovery request (keyboard)\n");
want_recovery = 1;
}
s = getenv("want_recovery");
if ((s != NULL) && (*s != '\0')) {
printf("detected recovery request (environment)\n");
want_recovery = 1;
}
s = getenv("install_in_progress");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation has not completed\n");
want_recovery = 1;
}
s = getenv("install_failed");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation has failed\n");
want_recovery = 1;
}
if (want_recovery) {
printf("enforced start of the recovery system\n");
setenv("bootcmd", "run recovery");
}
/*
* boot the recovery system without waiting; boot the
* production system without waiting by default, only
* insert a pause (to provide a chance to get a prompt)
* when GPIO keys were pressed during power on
*/
if (want_recovery)
setenv("bootdelay", "0");
else if (!keys)
setenv("bootdelay", "0");
else
setenv("bootdelay", "2");
/* get the ethernet MAC from I2C EEPROM */
mac_read_from_eeprom();
return 0;
}
int misc_init_r(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
/*
* Re-configure flash setup using auto-detected info
*/
if (flash_info[1].size > 0) {
out_be32(&im->sysconf.lpcs1aw,
CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
flash_info[1].size));
sync_law(&im->sysconf.lpcs1aw);
/*
* Re-check to get correct base address
*/
flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
} else {
/* Disable Bank 1 */
out_be32(&im->sysconf.lpcs1aw, 0x01000100);
sync_law(&im->sysconf.lpcs1aw);
}
out_be32(&im->sysconf.lpcs0aw,
CSAW_START(gd->bd->bi_flashstart) |
CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
sync_law(&im->sysconf.lpcs0aw);
/*
* Re-check to get correct base address
*/
flash_get_size (gd->bd->bi_flashstart, 0);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[0]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[0]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#ifdef CONFIG_ENV_ADDR_REDUND
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
#ifdef CONFIG_FSL_DIU_FB
set_lcd_brightness(0);
/* Switch LCD-Backlight and LVDS-Interface on */
setbits_be32(&im->gpio.gpdir, 0x01040000);
clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
#endif
#if defined(CONFIG_HARD_I2C)
if (!getenv("ethaddr")) {
uchar buf[6];
uchar ifm_oui[3] = { 0, 2, 1, };
int ret;
/* I2C-0 for on-board eeprom */
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
/* Read ethaddr from EEPROM */
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
if (ret != 0) {
printf("Error: Unable to read MAC from I2C"
" EEPROM at address %02X:%02X\n",
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
return 1;
}
/* Owned by IFM ? */
if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
printf("Illegal MAC address in EEPROM: %pM\n", buf);
return 1;
}
eth_setenv_enetaddr("ethaddr", buf);
}
#endif /* defined(CONFIG_HARD_I2C) */
return 0;
}
long int spd_sdram(int(read_spd)(uint addr))
{
int tmp,row,col;
int total_size,bank_size,bank_code;
int mode;
int bank_cnt;
int sdram0_pmit=0x07c00000;
int sdram0_b0cr;
int sdram0_b1cr = 0;
#ifndef CONFIG_405EP /* not on PPC405EP */
int sdram0_b2cr = 0;
int sdram0_b3cr = 0;
int sdram0_besr0 = -1;
int sdram0_besr1 = -1;
int sdram0_eccesr = -1;
int sdram0_ecccfg;
int ecc_on;
#endif
int sdram0_rtr=0;
int sdram0_tr=0;
int sdram0_cfg=0;
int t_rp;
int t_rcd;
int t_ras;
int t_rc;
int min_cas;
PPC4xx_SYS_INFO sys_info;
unsigned long bus_period_x_10;
/*
* get the board info
*/
get_sys_info(&sys_info);
bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
if (read_spd == 0){
read_spd=spd_read;
/*
* Make sure I2C controller is initialized
* before continuing.
*/
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
}
/* Make shure we are using SDRAM */
if (read_spd(2) != 0x04) {
SPD_ERR("SDRAM - non SDRAM memory module found\n");
}
/* ------------------------------------------------------------------
* configure memory timing register
*
* data from DIMM:
* 27 IN Row Precharge Time ( t RP)
* 29 MIN RAS to CAS Delay ( t RCD)
* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
* -------------------------------------------------------------------*/
/*
* first figure out which cas latency mode to use
* use the min supported mode
*/
tmp = read_spd(127) & 0x6;
if (tmp == 0x02) { /* only cas = 2 supported */
min_cas = 2;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
} else if (tmp == 0x04) { /* only cas = 3 supported */
min_cas = 3;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
min_cas = 2;
/* t_ck = read_spd(23); */
/* t_ac = read_spd(24); */
} else {
SPD_ERR("SDRAM - unsupported CAS latency \n");
}
/* get some timing values, t_rp,t_rcd,t_ras,t_rc
*/
t_rp = read_spd(27);
t_rcd = read_spd(29);
t_ras = read_spd(30);
t_rc = t_ras + t_rp;
/* The following timing calcs subtract 1 before deviding.
* this has effect of using ceiling instead of floor rounding,
* and also subtracting 1 to convert number to reg value
*/
/* set up CASL */
sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
/* set up PTA */
sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
/* set up CTP */
tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
if (tmp < 1)
tmp = 1;
sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
/* set LDF = 2 cycles, reg value = 1 */
sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
if (tmp < 0)
tmp = 0;
if (tmp > 6)
tmp = 6;
sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
/* set RCD = t_rcd/bus_period*/
sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
/*------------------------------------------------------------------
* configure RTR register
* -------------------------------------------------------------------*/
row = read_spd(3);
col = read_spd(4);
tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
switch (tmp) {
case 0x00:
tmp = 15625;
break;
case 0x01:
tmp = 15625 / 4;
break;
case 0x02:
tmp = 15625 / 2;
break;
case 0x03:
tmp = 15625 * 2;
break;
case 0x04:
tmp = 15625 * 4;
break;
case 0x05:
tmp = 15625 * 8;
break;
default:
SPD_ERR("SDRAM - Bad refresh period \n");
}
/* convert from nsec to bus cycles */
tmp = (tmp * 10) / bus_period_x_10;
sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
/*------------------------------------------------------------------
* determine the number of banks used
* -------------------------------------------------------------------*/
/* byte 7:6 is module data width */
if (read_spd(7) != 0)
SPD_ERR("SDRAM - unsupported module width\n");
tmp = read_spd(6);
if (tmp < 32)
SPD_ERR("SDRAM - unsupported module width\n");
else if (tmp < 64)
bank_cnt = 1; /* one bank per sdram side */
else if (tmp < 73)
bank_cnt = 2; /* need two banks per side */
else if (tmp < 161)
bank_cnt = 4; /* need four banks per side */
else
SPD_ERR("SDRAM - unsupported module width\n");
/* byte 5 is the module row count (refered to as dimm "sides") */
tmp = read_spd(5);
if (tmp == 1)
;
else if (tmp==2)
bank_cnt *= 2;
else if (tmp==4)
bank_cnt *= 4;
else
bank_cnt = 8; /* 8 is an error code */
if (bank_cnt > 4) /* we only have 4 banks to work with */
SPD_ERR("SDRAM - unsupported module rows for this width\n");
#ifndef CONFIG_405EP /* not on PPC405EP */
/* now check for ECC ability of module. We only support ECC
* on 32 bit wide devices with 8 bit ECC.
*/
if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
ecc_on = 1;
} else {
sdram0_ecccfg = 0;
ecc_on = 0;
}
#endif
/*------------------------------------------------------------------
* calculate total size
* -------------------------------------------------------------------*/
/* calculate total size and do sanity check */
tmp = read_spd(31);
total_size = 1 << 22; /* total_size = 4MB */
/* now multiply 4M by the smallest device row density */
/* note that we don't support asymetric rows */
while (((tmp & 0x0001) == 0) && (tmp != 0)) {
total_size = total_size << 1;
tmp = tmp >> 1;
}
total_size *= read_spd(5); /* mult by module rows (dimm sides) */
/*------------------------------------------------------------------
* map rows * cols * banks to a mode
* -------------------------------------------------------------------*/
switch (row) {
case 11:
switch (col) {
case 8:
mode=4; /* mode 5 */
break;
case 9:
case 10:
mode=0; /* mode 1 */
break;
default:
SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 12:
switch (col) {
case 8:
mode=3; /* mode 4 */
break;
case 9:
case 10:
mode=1; /* mode 2 */
break;
default:
SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 13:
switch (col) {
case 8:
mode=5; /* mode 6 */
break;
case 9:
case 10:
if (read_spd(17) == 2)
mode = 6; /* mode 7 */
else
mode = 2; /* mode 3 */
break;
case 11:
mode = 2; /* mode 3 */
break;
default:
SPD_ERR("SDRAM - unsupported mode\n");
}
break;
default:
SPD_ERR("SDRAM - unsupported mode\n");
}
/*------------------------------------------------------------------
* using the calculated values, compute the bank
* config register values.
* -------------------------------------------------------------------*/
/* compute the size of each bank */
bank_size = total_size / bank_cnt;
/* convert bank size to bank size code for ppc4xx
by takeing log2(bank_size) - 22 */
tmp = bank_size; /* start with tmp = bank_size */
bank_code = 0; /* and bank_code = 0 */
while (tmp > 1) { /* this takes log2 of tmp */
bank_code++; /* and stores result in bank_code */
tmp = tmp >> 1;
} /* bank_code is now log2(bank_size) */
bank_code -= 22; /* subtract 22 to get the code */
tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
sdram0_b0cr = (bank_size * 0) | tmp;
#ifndef CONFIG_405EP /* not on PPC405EP */
if (bank_cnt > 1)
sdram0_b2cr = (bank_size * 1) | tmp;
if (bank_cnt > 2)
sdram0_b1cr = (bank_size * 2) | tmp;
if (bank_cnt > 3)
sdram0_b3cr = (bank_size * 3) | tmp;
#else
/* PPC405EP chip only supports two SDRAM banks */
if (bank_cnt > 1)
sdram0_b1cr = (bank_size * 1) | tmp;
if (bank_cnt > 2)
total_size = 2 * bank_size;
#endif
/*
* enable sdram controller DCE=1
* enable burst read prefetch to 32 bytes BRPF=2
* leave other functions off
*/
/*------------------------------------------------------------------
* now that we've done our calculations, we are ready to
* program all the registers.
* -------------------------------------------------------------------*/
/* disable memcontroller so updates work */
mtsdram(SDRAM0_CFG, 0);
#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram(SDRAM0_BESR0, sdram0_besr0);
mtsdram(SDRAM0_BESR1, sdram0_besr1);
mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
#endif
mtsdram(SDRAM0_RTR, sdram0_rtr);
mtsdram(SDRAM0_PMIT, sdram0_pmit);
mtsdram(SDRAM0_B0CR, sdram0_b0cr);
mtsdram(SDRAM0_B1CR, sdram0_b1cr);
#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram(SDRAM0_B2CR, sdram0_b2cr);
mtsdram(SDRAM0_B3CR, sdram0_b3cr);
#endif
mtsdram(SDRAM0_TR, sdram0_tr);
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
#ifndef CONFIG_405EP /* not on PPC405EP */
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
#endif
mtsdram(SDRAM0_CFG, sdram0_cfg);
return (total_size);
}
int max77686_enable_32khz_cp(void)
{
i2c_set_bus_num(0);
return max77686_enablereg(PMIC_EN32KHZ_CP, REG_ENABLE);
}
static int detect_i2c(struct display_info_t const *dev)
{
return ((0 == i2c_set_bus_num(dev->bus))
&&
(0 == i2c_probe(dev->addr)));
}
static int setup_pmic_voltages(void)
{
unsigned char value, rev_id = 0;
i2c_set_bus_num(0);
if (!i2c_probe(0x8)) {
if (i2c_read(0x8, 0, 1, &value, 1)) {
printf("Read device ID error!\n");
return -1;
}
if (i2c_read(0x8, 3, 1, &rev_id, 1)) {
printf("Read Rev ID error!\n");
return -1;
}
printf("Found PFUZE%s deviceid=%x,revid=%x\n",
((value & 0xf) == 0) ? "100" : "200", value, rev_id);
if (setup_pmic_mode(value & 0xf)) {
printf("setup pmic mode error!\n");
return -1;
}
/* set SW1AB staby volatage 0.975V */
if (i2c_read(0x8, 0x21, 1, &value, 1)) {
printf("Read SW1ABSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= 0x1b;
if (i2c_write(0x8, 0x21, 1, &value, 1)) {
printf("Set SW1ABSTBY error!\n");
return -1;
}
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
if (i2c_read(0x8, 0x24, 1, &value, 1)) {
printf("Read SW1ABCONFIG error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(0x8, 0x24, 1, &value, 1)) {
printf("Set SW1ABCONFIG error!\n");
return -1;
}
/* set SW1C staby volatage 0.975V */
if (i2c_read(0x8, 0x2f, 1, &value, 1)) {
printf("Read SW1CSTBY error!\n");
return -1;
}
value &= ~0x3f;
value |= 0x1b;
if (i2c_write(0x8, 0x2f, 1, &value, 1)) {
printf("Set SW1CSTBY error!\n");
return -1;
}
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
if (i2c_read(0x8, 0x32, 1, &value, 1)) {
printf("Read SW1CCONFIG error!\n");
return -1;
}
value &= ~0xc0;
value |= 0x40;
if (i2c_write(0x8, 0x32, 1, &value, 1)) {
printf("Set SW1CCONFIG error!\n");
return -1;
}
}
return 0;
}