int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
got_hcirq = 0;
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
irq_install_handler(IRQ0_FPGA,
(interrupt_handler_t *)fpga_interrupt,
fpga);
FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
while (!got_hcirq) {
/* Abort if ctrl-c was pressed */
if (ctrlc()) {
puts("\nAbort\n");
break;
}
}
if (got_hcirq)
printf("Got interrupt!\n");
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
irq_free_handler(IRQ0_FPGA);
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_usb_exit(void)
{
//int i;
if(sunxi_udc_source.dma_send_channal)
{
sunxi_dma_release(sunxi_udc_source.dma_send_channal);
}
if(sunxi_udc_source.dma_recv_channal)
{
sunxi_dma_release(sunxi_udc_source.dma_recv_channal);
}
if(sunxi_ubuf.rx_base_buffer)
{
free(sunxi_ubuf.rx_base_buffer);
}
USBC_close_otg(sunxi_udc_source.usbc_hd);
irq_disable(AW_IRQ_USB_OTG);
irq_free_handler(AW_IRQ_USB_OTG);
usb_close_clock();
sunxi_udev_active->state_exit();
memset(&sunxi_ubuf, 0, sizeof(sunxi_ubuf_t));
return 0;
}
void sunxi_dma_exit(void)
{
int i;
uint hdma;
sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
//free dma channal if other module not free it
for(i=0;i<SUNXI_DMA_MAX;i++)
{
if(dma_channal_source[i].used == 1)
{
hdma = (uint)&dma_channal_source[i];
sunxi_dma_disable_int(hdma);
sunxi_dma_free_int(hdma);
dma_channal_source[i].channal->enable = 0;
dma_channal_source[i].used = 0;
}
}
//irp disable
dma_int->irq_en0 = 0;
dma_int->irq_en1 = 0;
dma_int->irq_pending0 = 0xffffffff;
dma_int->irq_pending1 = 0xffffffff;
irq_free_handler(AW_IRQ_DMA);
//close dma clock when dma exit
sunxi_disable_dma_clock();
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
void sunxi_dma_exit(void)
{
sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
dma_int->irq_en0 = 0;
dma_int->irq_pending0 = 0xffffffff;
irq_free_handler(AW_IRQ_DMA);
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_usb_exit(void)
{
irq_disable(AW_IRQ_USB_OTG);
irq_free_handler(AW_IRQ_USB_OTG);
if(sunxi_ubuf.rx_req_buffer)
{
free(sunxi_ubuf.rx_req_buffer);
}
usb_close_clock();
sunxi_udev_active->state_exit();
__usb_release_mem();
memset(&sunxi_ubuf, 0, sizeof(sunxi_ubuf_t));
return 0;
}
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
int i;
int n = 0;
u32 ctrl, data, f;
char str[] = "\\|/-";
int abort = 0;
int count = 0;
int count2 = 0;
switch (argc) {
case 1:
/* print all fifos status information */
printf("fifo level status\n");
printf("______________________________\n");
for (i=0; i<FIFO_COUNT; i++) {
ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
printf(" %d %3d %s%s%s %s\n",
i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
ctrl & FIFO_FULL ? "FULL " : "",
ctrl & FIFO_EMPTY ? "EMPTY " : "",
ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
}
break;
case 2:
/* completely read out fifo 'n' */
if (!strcmp(argv[1],"read")) {
printf(" # fifo level data\n");
printf("______________________________\n");
for (i=0; i<FIFO_COUNT; i++)
dump_fifo(fpga, i, &n);
} else if (!strcmp(argv[1],"wait")) {
got_fifoirq = 0;
irq_install_handler(IRQ0_FPGA,
(interrupt_handler_t *)fpga_interrupt,
fpga);
printf(" # fifo level data\n");
printf("______________________________\n");
/* enable all fifo interrupts */
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
for (i=0; i<FIFO_COUNT; i++) {
/* enable interrupts from all fifos */
FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
}
while (1) {
/* wait loop */
while (!got_fifoirq) {
count++;
if (!(count % 100)) {
count2++;
putc(0x08); /* backspace */
putc(str[count2 % 4]);
}
/* Abort if ctrl-c was pressed */
if ((abort = ctrlc())) {
puts("\nAbort\n");
break;
}
udelay(1000);
}
if (abort)
break;
/* simple fifo backend */
if (got_fifoirq) {
for (i=0; i<FIFO_COUNT; i++)
dump_fifo(fpga, i, &n);
got_fifoirq = 0;
/* unmask global fifo irq */
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_FIFOIE_GATE |
HOSTCTRL_FIFOIE_FLAG);
}
}
/* disable all fifo interrupts */
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
for (i=0; i<FIFO_COUNT; i++)
FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
irq_free_handler(IRQ0_FPGA);
} else {
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
break;
case 4:
case 5:
if (!strcmp(argv[1],"write")) {
/* get fifo number or fifo address */
f = simple_strtoul(argv[2], NULL, 16);
/* data paramter */
data = simple_strtoul(argv[3], NULL, 16);
/* get optional count parameter */
n = 1;
if (argc >= 5)
n = (int)simple_strtoul(argv[4], NULL, 10);
if (f < FIFO_COUNT) {
printf("writing %d x %08x to fifo %d\n",
n, data, f);
for (i=0; i<n; i++)
FPGA_OUT32(&fpga->fifo[f].data, data);
} else {
printf("writing %d x %08x to fifo port at "
"address %08x\n",
n, data, f);
for (i=0; i<n; i++)
out_be32((void *)f, data);
}
} else {
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
break;
default:
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
return 0;
}