/** This function is called when mali GPU device is to be resumed
*/
static int mali_pm_resume(struct device *dev)
{
int err = 0;
_mali_osk_lock_wait(lock, _MALI_OSK_LOCKMODE_RW);
#ifdef CONFIG_REGULATOR
mali_regulator_enable();
#endif
if (mali_device_state == _MALI_DEVICE_RESUME)
{
_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
return err;
}
err = mali_device_resume(MALI_PMM_EVENT_OS_POWER_UP, &pm_thread);
mali_device_state = _MALI_DEVICE_RESUME;
mali_dvfs_device_state = _MALI_DEVICE_RESUME;
_mali_osk_lock_signal(lock, _MALI_OSK_LOCKMODE_RW);
return err;
}
static int mali_os_resume(struct device *device)
{
int ret = 0;
MALI_DEBUG_PRINT(4, ("mali_os_resume() called\n"));
#ifdef CONFIG_REGULATOR
mali_regulator_enable();
g3d_power_domain_control(1);
#endif
mali_platform_power_mode_change(device, MALI_POWER_MODE_ON);
if (NULL != device &&
NULL != device->driver &&
NULL != device->driver->pm &&
NULL != device->driver->pm->resume)
{
/* Need to notify Mali driver about this event */
ret = device->driver->pm->resume(device);
}
return ret;
}
/*****************************************************************************
function name : init_mali_clock_regulator
description : mali clk and regulator init
input vars : void
output vars : NA
return value : mali_bool
calls : mali_clk_get
called : mali_platform_init
history :
1.data : 04/03/2014
author : s00250033
modify : new
*****************************************************************************/
static mali_bool init_mali_clock_regulator(struct platform_device *pdev)
{
mali_bool ret = MALI_TRUE;
g_swGpuPowerState = MALI_TRUE;
/* regulator init */
mali_regulator = regulator_get(&pdev->dev, "G3D_PD_VDD");
if (IS_ERR(mali_regulator))
{
MALI_PRINT( ("MALI Error : failed to get G3D_PD_VDD\n"));
return MALI_FALSE;
}
mali_regulator_enable();
/* clk init */
if (mali_clock != 0)
{
return ret;
}
if (!mali_clk_get(pdev))
{
MALI_PRINT(("MALI Error: Failed to get Mali clock\n"));
return MALI_FALSE;
}
/*使能媒体外设时钟*/
ret = phy_reg_readl(SOC_PERI_SCTRL_BASE_ADDR, SOC_PERI_SCTRL_SC_PERIPH_CLKSTAT12_ADDR(0), 10, 10);
if(1 != ret)
{
phy_reg_writel(SOC_PERI_SCTRL_BASE_ADDR,SOC_PERI_SCTRL_SC_PERIPH_CLKEN12_ADDR(0),10,10,1);
ret = phy_reg_readl(SOC_PERI_SCTRL_BASE_ADDR, SOC_PERI_SCTRL_SC_PERIPH_CLKSTAT12_ADDR(0), 10, 10);
if(1 != ret)
{
MALI_DEBUG_PRINT(2, (" error: SET SC_PERIPH_CLKEN12 failed!\n"));
}
}
/* CLK on and set rate */
mali_clock_on();
MALI_DEBUG_PRINT(2, (" init mali clock regulator ok\n"));
/*时钟有效指示*/
phy_reg_writel(SOC_MEDIA_SCTRL_BASE_ADDR,SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0),15,15,1);
ret = phy_reg_readl(SOC_MEDIA_SCTRL_BASE_ADDR, SOC_MEDIA_SCTRL_SC_MEDIA_CLKCFG2_ADDR(0), 15, 15);
if(1 != ret)
{
MALI_DEBUG_PRINT(2, (" error: SET SC_MEDIA_CLKCFG2 failed!\n"));
}
mali_domain_powerup_finish();
return MALI_TRUE;
}