static int ni_tio_input_cmd(struct ni_gpct *counter, struct comedi_async *async) { struct ni_gpct_device *counter_dev = counter->counter_dev; unsigned cidx = counter->counter_index; struct comedi_cmd *cmd = &async->cmd; int retval = 0; /* write alloc the entire buffer */ comedi_buf_write_alloc(async, async->prealloc_bufsz); counter->mite_chan->dir = COMEDI_INPUT; switch (counter_dev->variant) { case ni_gpct_variant_m_series: case ni_gpct_variant_660x: mite_prep_dma(counter->mite_chan, 32, 32); break; case ni_gpct_variant_e_series: mite_prep_dma(counter->mite_chan, 16, 32); break; default: BUG(); break; } ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), Gi_Save_Trace_Bit, 0); ni_tio_configure_dma(counter, 1, 1); switch (cmd->start_src) { case TRIG_NOW: async->inttrig = NULL; mite_dma_arm(counter->mite_chan); retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); break; case TRIG_INT: async->inttrig = &ni_tio_input_inttrig; break; case TRIG_EXT: async->inttrig = NULL; mite_dma_arm(counter->mite_chan); retval = ni_tio_arm(counter, 1, cmd->start_arg); break; case TRIG_OTHER: async->inttrig = NULL; mite_dma_arm(counter->mite_chan); break; default: BUG(); break; } return retval; }
static int ni_tio_input_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int trig_num) { struct ni_gpct *counter = s->private; struct comedi_cmd *cmd = &s->async->cmd; unsigned long flags; int ret = 0; if (trig_num != cmd->start_arg) return -EINVAL; spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) mite_dma_arm(counter->mite_chan); else ret = -EIO; spin_unlock_irqrestore(&counter->lock, flags); if (ret < 0) return ret; ret = ni_tio_arm(counter, true, NI_GPCT_ARM_IMMEDIATE); s->async->inttrig = NULL; return ret; }
static int ni_tio_input_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int trignum) { unsigned long flags; int retval = 0; struct ni_gpct *counter = s->private; BUG_ON(counter == NULL); if (trignum != 0) return -EINVAL; spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) mite_dma_arm(counter->mite_chan); else retval = -EIO; spin_unlock_irqrestore(&counter->lock, flags); if (retval < 0) return retval; retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); s->async->inttrig = NULL; return retval; }
int ni_tio_insn_config(struct ni_gpct *counter, comedi_insn * insn, lsampl_t * data) { switch (data[0]) { case INSN_CONFIG_SET_COUNTER_MODE: return ni_tio_set_counter_mode(counter, data[1]); break; case INSN_CONFIG_ARM: return ni_tio_arm(counter, 1, data[1]); break; case INSN_CONFIG_DISARM: ni_tio_arm(counter, 0, 0); return 0; break; case INSN_CONFIG_GET_COUNTER_STATUS: data[1] = ni_tio_counter_status(counter); data[2] = counter_status_mask; return 0; break; case INSN_CONFIG_SET_CLOCK_SRC: return ni_tio_set_clock_src(counter, data[1], data[2]); break; case INSN_CONFIG_GET_CLOCK_SRC: ni_tio_get_clock_src(counter, &data[1], &data[2]); return 0; break; case INSN_CONFIG_SET_GATE_SRC: return ni_tio_set_gate_src(counter, data[1], data[2]); break; case INSN_CONFIG_GET_GATE_SRC: return ni_tio_get_gate_src(counter, data[1], &data[2]); break; case INSN_CONFIG_SET_OTHER_SRC: return ni_tio_set_other_src(counter, data[1], data[2]); break; case INSN_CONFIG_RESET: ni_tio_reset_count_and_disarm(counter); return 0; break; default: break; } return -EINVAL; }
static int ni_tio_output_cmd(struct ni_gpct *counter, comedi_async * async) { rt_printk("ni_tio: output commands not yet implemented.\n"); return -ENOTSUPP; counter->mite_chan->dir = COMEDI_OUTPUT; mite_prep_dma(counter->mite_chan, 32, 32); ni_tio_configure_dma(counter, 1, 0); mite_dma_arm(counter->mite_chan); return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); }
static int ni_tio_input_cmd(struct comedi_subdevice *s) { struct ni_gpct *counter = s->private; struct ni_gpct_device *counter_dev = counter->counter_dev; unsigned cidx = counter->counter_index; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; int ret = 0; /* write alloc the entire buffer */ comedi_buf_write_alloc(s, async->prealloc_bufsz); counter->mite_chan->dir = COMEDI_INPUT; switch (counter_dev->variant) { case ni_gpct_variant_m_series: case ni_gpct_variant_660x: mite_prep_dma(counter->mite_chan, 32, 32); break; case ni_gpct_variant_e_series: mite_prep_dma(counter->mite_chan, 16, 32); break; default: BUG(); break; } ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); ni_tio_configure_dma(counter, true, true); if (cmd->start_src == TRIG_INT) { async->inttrig = &ni_tio_input_inttrig; } else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */ async->inttrig = NULL; mite_dma_arm(counter->mite_chan); if (cmd->start_src == TRIG_NOW) ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); else if (cmd->start_src == TRIG_EXT) ret = ni_tio_arm(counter, 1, cmd->start_arg); } return ret; }
static int ni_tio_output_cmd(struct comedi_subdevice *s) { struct ni_gpct *counter = s->private; dev_err(counter->counter_dev->dev->class_dev, "output commands not yet implemented.\n"); return -ENOTSUPP; counter->mite_chan->dir = COMEDI_OUTPUT; mite_prep_dma(counter->mite_chan, 32, 32); ni_tio_configure_dma(counter, true, false); mite_dma_arm(counter->mite_chan); return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE); }
int ni_tio_cancel(struct ni_gpct *counter) { unsigned int cidx = counter->counter_index; unsigned long flags; ni_tio_arm(counter, false, 0); spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) mite_dma_disarm(counter->mite_chan); spin_unlock_irqrestore(&counter->lock, flags); ni_tio_configure_dma(counter, false, false); ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), GI_GATE_INTERRUPT_ENABLE(cidx), 0x0); return 0; }
int ni_tio_cancel(struct ni_gpct *counter) { unsigned cidx = counter->counter_index; unsigned long flags; ni_tio_arm(counter, 0, 0); spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) mite_dma_disarm(counter->mite_chan); spin_unlock_irqrestore(&counter->lock, flags); ni_tio_configure_dma(counter, 0, 0); ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), Gi_Gate_Interrupt_Enable_Bit(cidx), 0x0); return 0; }
int ni_tio_cancel(struct ni_gpct *counter) { unsigned long flags; ni_tio_arm(counter, 0, 0); comedi_spin_lock_irqsave(&counter->lock, flags); if (counter->mite_chan) { mite_dma_disarm(counter->mite_chan); } comedi_spin_unlock_irqrestore(&counter->lock, flags); ni_tio_configure_dma(counter, 0, 0); ni_tio_set_bits(counter, NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), Gi_Gate_Interrupt_Enable_Bit(counter->counter_index), 0x0); return 0; }