unsigned int adjust_dg_dac_routing(struct oxygen *chip, unsigned int play_routing) { struct dg *data = chip->model_data; switch (data->output_sel) { case PLAYBACK_DST_HP: case PLAYBACK_DST_HP_FP: oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK); break; case PLAYBACK_DST_MULTICH: oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK); break; } return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC2_SOURCE_SHIFT, OXYGEN_PLAY_DAC1_SOURCE_SHIFT, OXYGEN_PLAY_DAC1_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC1_SOURCE_SHIFT, OXYGEN_PLAY_DAC2_SOURCE_SHIFT, OXYGEN_PLAY_DAC2_SOURCE_MASK) | shift_bits(play_routing, OXYGEN_PLAY_DAC0_SOURCE_SHIFT, OXYGEN_PLAY_DAC3_SOURCE_SHIFT, OXYGEN_PLAY_DAC3_SOURCE_MASK); }
static int oxygen_multich_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; mutex_lock(&chip->mutex); spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS, oxygen_play_channels(hw_params), OXYGEN_PLAY_CHANNELS_MASK); oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT, oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT, OXYGEN_MULTICH_FORMAT_MASK); oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT, oxygen_rate(hw_params) | chip->model.dac_i2s_format | get_mclk(chip, PCM_MULTICH, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); oxygen_update_spdif_source(chip); spin_unlock_irq(&chip->reg_lock); chip->model.set_dac_params(chip, hw_params); oxygen_update_dac_routing(chip); mutex_unlock(&chip->mutex); return 0; }
static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; mutex_lock(&chip->mutex); spin_lock_irq(&chip->reg_lock); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE); oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT, oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT, OXYGEN_SPDIF_FORMAT_MASK); oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT, OXYGEN_SPDIF_OUT_RATE_MASK); oxygen_update_spdif_source(chip); spin_unlock_irq(&chip->reg_lock); mutex_unlock(&chip->mutex); return 0; }
static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT, OXYGEN_REC_FORMAT_A_MASK); oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, oxygen_rate(hw_params) | chip->model.adc_i2s_format | get_mclk(chip, PCM_A, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); spin_unlock_irq(&chip->reg_lock); mutex_lock(&chip->mutex); chip->model.set_adc_params(chip, hw_params); mutex_unlock(&chip->mutex); return 0; }
static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT, OXYGEN_REC_FORMAT_C_MASK); spin_unlock_irq(&chip->reg_lock); return 0; }
static int output_switch_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) { struct oxygen *chip = ctl->private_data; struct dg *data = chip->model_data; u8 reg; int changed; if (value->value.enumerated.item[0] > 2) return -EINVAL; mutex_lock(&chip->mutex); changed = value->value.enumerated.item[0] != data->output_sel; if (changed) { data->output_sel = value->value.enumerated.item[0]; reg = data->cs4245_regs[CS4245_SIGNAL_SEL] & ~CS4245_A_OUT_SEL_MASK; reg |= data->output_sel == 2 ? CS4245_A_OUT_SEL_DAC : CS4245_A_OUT_SEL_HIZ; cs4245_write_cached(chip, CS4245_SIGNAL_SEL, reg); cs4245_write_cached(chip, CS4245_DAC_A_CTRL, data->output_sel ? data->hp_vol_att : 0); cs4245_write_cached(chip, CS4245_DAC_B_CTRL, data->output_sel ? data->hp_vol_att : 0); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, data->output_sel == 1 ? GPIO_HP_REAR : 0, GPIO_HP_REAR); oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING, data->output_sel == 0 ? OXYGEN_PLAY_MUTE01 : OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67); } mutex_unlock(&chip->mutex); return changed; }
static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) { struct oxygen *chip = snd_pcm_substream_chip(substream); int is_ac97; int err; err = oxygen_hw_params(substream, hw_params); if (err < 0) return err; is_ac97 = chip->has_ac97_1 && (chip->model.device_config & CAPTURE_2_FROM_AC97_1); spin_lock_irq(&chip->reg_lock); oxygen_write8_masked(chip, OXYGEN_REC_FORMAT, oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT, OXYGEN_REC_FORMAT_B_MASK); if (!is_ac97) oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT, oxygen_rate(hw_params) | chip->model.adc_i2s_format | get_mclk(chip, PCM_B, hw_params) | oxygen_i2s_bits(hw_params), OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK | OXYGEN_I2S_MCLK_MASK | OXYGEN_I2S_BITS_MASK); spin_unlock_irq(&chip->reg_lock); if (!is_ac97) { mutex_lock(&chip->mutex); chip->model.set_adc_params(chip, hw_params); mutex_unlock(&chip->mutex); } return 0; }
static void oxygen_init(struct oxygen *chip) { unsigned int i; chip->dac_routing = 1; for (i = 0; i < 8; ++i) chip->dac_volume[i] = chip->model.dac_volume_min; chip->dac_mute = 1; chip->spdif_playback_enable = 1; chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); chip->spdif_pcm_bits = chip->spdif_bits; if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2) chip->revision = 2; else chip->revision = 1; if (chip->revision == 1) oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_PCI_MEM_W_1_CLOCK); i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; oxygen_write8_masked(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC | chip->model.function_flags, OXYGEN_FUNCTION_RESET_CODEC | OXYGEN_FUNCTION_2WIRE_SPI_MASK | OXYGEN_FUNCTION_ENABLE_SPI_4_5); oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, OXYGEN_PLAY_CHANNELS_2 | OXYGEN_DMA_A_BURST_8 | OXYGEN_DMA_MULTICH_BURST_8); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); oxygen_write8_masked(chip, OXYGEN_MISC, chip->model.misc_flags, OXYGEN_MISC_WRITE_PCI_SUBID | OXYGEN_MISC_REC_C_FROM_SPDIF | OXYGEN_MISC_REC_B_FROM_AC97 | OXYGEN_MISC_REC_A_FROM_MULTICH | OXYGEN_MISC_MIDI); oxygen_write8(chip, OXYGEN_REC_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); oxygen_write8(chip, OXYGEN_PLAY_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, OXYGEN_RATE_48000 | chip->model.dac_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | CAPTURE_2_FROM_I2S_2)) oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE | OXYGEN_SPDIF_LOOPBACK); if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_96, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_SENSE_PAR | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_MASK); else oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK); oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_STANDARD); oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF | (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); oxygen_write8(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_A_ROUTE_I2S_ADC_1 | OXYGEN_REC_B_ROUTE_I2S_ADC_2 | OXYGEN_REC_C_ROUTE_SPDIF); oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); if (chip->has_ac97_0 | chip->has_ac97_1) oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, OXYGEN_AC97_INT_READ_DONE | OXYGEN_AC97_INT_WRITE_DONE); else oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); if (!(chip->has_ac97_0 | chip->has_ac97_1)) oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_CLOCK_DISABLE); if (!chip->has_ac97_0) { oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_NO_CODEC_0); } else { oxygen_write_ac97(chip, 0, AC97_RESET, 0); msleep(1); oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, CM9780_GPIO0IO | CM9780_GPIO1IO); oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, CM9780_BSTSEL | CM9780_STRO_MIC | CM9780_MIX2FR | CM9780_PCBSW); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_RSOE | CM9780_CBOE | CM9780_SSOE | CM9780_FROE | CM9780_MIC2MIC | CM9780_LI2LI); oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, CM9780_GPO0); /* power down unused ADCs and DACs */ oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, AC97_PD_PR0 | AC97_PD_PR1); oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); } if (chip->has_ac97_1) { oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, OXYGEN_AC97_CODEC1_SLOT3 | OXYGEN_AC97_CODEC1_SLOT4); oxygen_write_ac97(chip, 1, AC97_RESET, 0); msleep(1); oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); } }
int oxygen_pcm_init(struct oxygen *chip) { struct snd_pcm *pcm; int outs, ins; int err; outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S); ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 | CAPTURE_0_FROM_I2S_2)); if (outs | ins) { err = snd_pcm_new(chip->card, "Multichannel", 0, outs, ins, &pcm); if (err < 0) return err; if (outs) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops); if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_a_ops); else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_b_ops); pcm->private_data = chip; pcm->private_free = oxygen_pcm_free; strcpy(pcm->name, "Multichannel"); if (outs) snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), DEFAULT_BUFFER_BYTES_MULTICH, BUFFER_BYTES_MAX_MULTICH); if (ins) snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF); ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF); if (outs | ins) { err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm); if (err < 0) return err; if (outs) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_spdif_ops); if (ins) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops); pcm->private_data = chip; pcm->private_free = oxygen_pcm_free; strcpy(pcm->name, "Digital"); snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } if (chip->has_ac97_1) { outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1); ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1); } else { outs = 0; ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2); } if (outs | ins) { err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2", 2, outs, ins, &pcm); if (err < 0) return err; if (outs) { snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_ac97_ops); oxygen_write8_masked(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_B_ROUTE_AC97_1, OXYGEN_REC_B_ROUTE_MASK); } if (ins) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_b_ops); pcm->private_data = chip; pcm->private_free = oxygen_pcm_free; strcpy(pcm->name, outs ? "Front Panel" : "Analog 2"); snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), DEFAULT_BUFFER_BYTES, BUFFER_BYTES_MAX); } return 0; }