static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr) { struct amdgpu_device *adev = hwmgr->adev; uint32_t reg; reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); phm_wait_for_register_unequal(hwmgr, reg, 0, MP1_C2PMSG_90__CONTENT_MASK); return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); }
int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr, uint32_t indirect_port, uint32_t index, uint32_t value, uint32_t mask) { if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; cgs_write_register(hwmgr->device, indirect_port, index); return phm_wait_for_register_unequal(hwmgr, indirect_port + 1, value, mask); }
void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr, uint32_t indirect_port, uint32_t index, uint32_t value, uint32_t mask) { if (hwmgr == NULL || hwmgr->device == NULL) { printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!"); return; } cgs_write_register(hwmgr->device, indirect_port, index); phm_wait_for_register_unequal(hwmgr, indirect_port + 1, value, mask); }
/* * Check if SMC has responded to previous message. * * @param smumgr the address of the powerplay hardware manager. * @return TRUE SMC has responded, FALSE otherwise. */ static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr) { uint32_t reg; if (!vega10_is_smc_ram_running(hwmgr)) return -EINVAL; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); phm_wait_for_register_unequal(hwmgr, reg, 0, MP1_C2PMSG_90__CONTENT_MASK); return cgs_read_register(hwmgr->device, reg); }