int tegra_sor_precharge_lanes(struct udevice *dev,
const struct tegra_dp_link_config *cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 val = 0;
switch (cfg->lane_count) {
case 4:
val |= (DP_PADCTL_PD_TXD_3_NO |
DP_PADCTL_PD_TXD_2_NO);
/* fall through */
case 2:
val |= DP_PADCTL_PD_TXD_1_NO;
/* fall through */
case 1:
val |= DP_PADCTL_PD_TXD_0_NO;
break;
default:
debug("dp: invalid lane number %d\n", cfg->lane_count);
return -EINVAL;
}
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
(0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
(val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
udelay(100);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
(0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
0);
return 0;
}
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg)
{
tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, NV_SOR_LVDS, 0);
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0x0);
}
static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg)
{
u32 reg_val;
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
reg_val |= link_cfg->watermark;
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
reg_val |= (link_cfg->active_count <<
NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
reg_val |= (link_cfg->active_frac <<
NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
if (link_cfg->activepolarity)
reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
else
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
/* program h/vblank sym */
tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym);
tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym);
}
void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)
{
const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
u32 val = 0;
switch (cfg->lane_count) {
case 4:
val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
NV_SOR_DP_PADCTL_PD_TXD_2_NO);
/* fall through */
case 2:
val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
/* fall through */
case 1:
val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
break;
default:
printk(BIOS_ERR,
"dp: invalid lane number %d\n", cfg->lane_count);
return;
}
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
(0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
(val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
udelay(100);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
(0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0);
}
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, LVDS, 0);
tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_ENABLE |
DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
DP_PADCTL_TX_PU_ENABLE |
2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
}
void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
{
const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg;
tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
tegra_sor_write_field(sor, NV_SOR_PLL3,
NV_SOR_PLL3_PLLVDD_MODE_MASK,
NV_SOR_PLL3_PLLVDD_MODE_V3_3);
tegra_sor_writel(sor, NV_SOR_PLL0,
0xf << NV_SOR_PLL0_ICHPMP_SHFIT |
0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
NV_SOR_PLL0_PLLREG_LEVEL_V45 |
NV_SOR_PLL0_RESISTORSEL_EXT |
NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
tegra_sor_writel(sor, NV_SOR_PLL1,
NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE);
if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
printk(BIOS_ERR, "DP failed to lock PLL\n");
return;
}
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
tegra_dc_sor_power_up(sor, 0);
/* re-enable SOR clock */
tegra_sor_enable_edp_clock(sor); // select pll_dp as clock source
/* Power up lanes */
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
tegra_dc_sor_set_dp_mode(sor, link_cfg);
}
void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
u32 vs_reg, u32 pc_reg, u8 pc_supported)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
if (pc_supported) {
tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,
pc_reg);
}
}
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported)
{
tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum),
mask, pe_reg);
tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum),
mask, vs_reg);
if (pc_supported) {
tegra_sor_write_field(
sor, NV_SOR_POSTCURSOR(sor->portnum),
mask, pc_reg);
}
}
void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
{
tegra_sor_write_field(sor,
NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_MASK,
NV_SOR_DP_PADCTL_TX_PU_DISABLE);
}
void tegra_dp_disable_tx_pu(struct udevice *dev)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
}
void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, CLK_CNTRL,
CLK_CNTRL_DP_LINK_SPEED_MASK,
link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
}
void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu)
{
u32 d_cur;
u32 p_emp;
d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum));
p_emp = tegra_sor_readl(sor, NV_SOR_PR(sor->portnum));
switch (lane) {
case 0:
p_emp &= ~NV_SOR_PR_LANE2_DP_LANE0_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE2_DP_LANE0_SHIFT);
d_cur &= ~NV_SOR_DC_LANE2_DP_LANE0_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE2_DP_LANE0_SHIFT);
break;
case 1:
p_emp &= ~NV_SOR_PR_LANE1_DP_LANE1_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE1_DP_LANE1_SHIFT);
d_cur &= ~NV_SOR_DC_LANE1_DP_LANE1_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE1_DP_LANE1_SHIFT);
break;
case 2:
p_emp &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE0_DP_LANE2_SHIFT);
d_cur &= ~NV_SOR_DC_LANE0_DP_LANE2_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE0_DP_LANE2_SHIFT);
break;
case 3:
p_emp &= ~NV_SOR_PR_LANE3_DP_LANE3_MASK;
p_emp |= (pre_emphasis <<
NV_SOR_PR_LANE3_DP_LANE3_SHIFT);
d_cur &= ~NV_SOR_DC_LANE3_DP_LANE3_MASK;
d_cur |= (drive_current <<
NV_SOR_DC_LANE3_DP_LANE3_SHIFT);
break;
default:
printk(BIOS_SPEW, "dp: sor lane count %d is invalid\n", lane);
}
tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
tx_pu << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), d_cur);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), p_emp);
}
/* 5 0 0 0 0 0 0 1 */
static void tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor,
int is_lvds)
{
if (sor->power_is_up)
return;
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(sor,
is_lvds ? NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS :
NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
/* step 1 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
tegra_sor_write_field(sor, NV_SOR_PLL0,
NV_SOR_PLL0_PWR_MASK | /* PDPLL */
NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
NV_SOR_PLL0_PWR_OFF |
NV_SOR_PLL0_VCOPD_ASSERT);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN);
/* step 2 */
tegra_dc_sor_io_set_dpd(sor, 1);
udelay(15);
/* step 3 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
/* step 4 */
tegra_sor_write_field(sor, NV_SOR_PLL0,
NV_SOR_PLL0_PWR_MASK | /* PDPLL */
NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
udelay(225);
/* step 5 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
sor->power_is_up = 1;
}
void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
{
tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
}
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
int is_lvds,
const struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing)
{
const int head_num = 0;
u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num;
u32 vtotal, htotal;
u32 vsync_end, hsync_end;
u32 vblank_end, hblank_end;
u32 vblank_start, hblank_start;
reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
STATE1_ASY_PROTOCOL_DP_A;
reg_val |= STATE1_ASY_SUBOWNER_NONE |
STATE1_ASY_CRCMODE_COMPLETE_RASTER;
reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
reg_val |= (link_cfg->bits_per_pixel > 18) ?
STATE1_ASY_PIXELDEPTH_BPP_24_444 :
STATE1_ASY_PIXELDEPTH_BPP_18_444;
tegra_sor_writel(sor, STATE1, reg_val);
/*
* Skipping programming NV_HEAD_STATE0, assuming:
* interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
*/
vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
timing->vactive.typ + timing->vfront_porch.typ;
htotal = timing->hsync_len.typ + timing->hback_porch.typ +
timing->hactive.typ + timing->hfront_porch.typ;
tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
vsync_end = timing->vsync_len.typ - 1;
hsync_end = timing->hsync_len.typ - 1;
tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
vblank_end = vsync_end + timing->vback_porch.typ;
hblank_end = hsync_end + timing->hback_porch.typ;
tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
vblank_start = vblank_end + timing->vactive.typ;
hblank_start = hblank_end + timing->hactive.typ;
tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
/* TODO: adding interlace mode support */
tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
tegra_sor_write_field(sor, CSTM,
CSTM_ROTCLK_DEFAULT_MASK |
CSTM_LVDS_EN_ENABLE,
2 << CSTM_ROTCLK_SHIFT |
is_lvds ? CSTM_LVDS_EN_ENABLE :
CSTM_LVDS_EN_DISABLE);
tegra_dc_sor_config_pwm(sor, 1024, 1024);
}
int tegra_dc_sor_enable_dp(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int ret;
tegra_sor_write_field(sor, CLK_CNTRL,
CLK_CNTRL_DP_CLK_SEL_MASK,
CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
tegra_sor_write_field(sor, PLL2,
PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
tegra_sor_write_field(sor, PLL3,
PLL3_PLLVDD_MODE_MASK,
PLL3_PLLVDD_MODE_V3_3);
tegra_sor_writel(sor, PLL0,
0xf << PLL0_ICHPMP_SHFIT |
0x3 << PLL0_VCOCAP_SHIFT |
PLL0_PLLREG_LEVEL_V45 |
PLL0_RESISTORSEL_EXT |
PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
tegra_sor_write_field(sor, PLL2,
PLL2_AUX1_SEQ_MASK |
PLL2_AUX9_LVDSEN_OVERRIDE |
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
PLL2_AUX9_LVDSEN_OVERRIDE |
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
PLL1_TMDS_TERM_ENABLE);
if (tegra_dc_sor_poll_register(sor, PLL2,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
100, TEGRA_SOR_TIMEOUT_MS)) {
printf("DP failed to lock PLL\n");
return -EIO;
}
tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
PLL2_AUX7_PORT_POWERDOWN_MASK,
PLL2_AUX2_OVERRIDE_POWERDOWN |
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
ret = tegra_dc_sor_power_up(dev, 0);
if (ret) {
debug("DP failed to power up\n");
return ret;
}
/* re-enable SOR clock */
clock_sor_enable_edp_clock();
/* Power up lanes */
tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1);
tegra_dc_sor_set_dp_mode(dev, link_cfg);
debug("%s ret\n", __func__);
return 0;
}
/*
* The SOR power sequencer does not work for t124 so SW has to
* go through the power sequence manually
* Power up steps from spec:
* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
* 1 1 1 1 1 1 1 1
* 2 1 1 1 1 1 0 1
* 3 1 1 0 1 1 0 1
* 4 1 0 0 0 0 0 1
* 5 0 0 0 0 0 0 1
*/
static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg;
int ret;
if (sor->power_is_up)
return 0;
/*
* If for some reason it is already powered up, don't do it again.
* This can happen if U-Boot is the secondary boot loader.
*/
reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
if (reg & DP_PADCTL_PD_TXD_0_NO)
return 0;
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
CLK_CNTRL_DP_LINK_SPEED_LVDS :
CLK_CNTRL_DP_LINK_SPEED_G1_62);
/* step 1 */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
PLL2_AUX7_PORT_POWERDOWN_ENABLE |
PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
PLL0_VCOPD_MASK, /* PLLVCOPD */
PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
DP_PADCTL_PAD_CAL_PD_POWERDOWN);
/* step 2 */
ret = tegra_dc_sor_io_set_dpd(sor, 1);
if (ret)
return ret;
udelay(15);
/* step 3 */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
/* step 4 */
tegra_sor_write_field(sor, PLL0,
PLL0_PWR_MASK | /* PDPLL */
PLL0_VCOPD_MASK, /* PLLVCOPD */
PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
/* PLLCAPD */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
udelay(225);
/* step 5 PDPORT */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX7_PORT_POWERDOWN_MASK,
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
sor->power_is_up = 1;
return 0;
}
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
int is_lvds)
{
const struct tegra_dc *dc = sor->dc;
const struct tegra_dc_dp_data *dp = dc->out;
const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg;
const struct soc_nvidia_tegra124_config *config = dc->config;
const int head_num = 0; // based on kernel dc driver
u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
u32 vtotal, htotal;
u32 vsync_end, hsync_end;
u32 vblank_end, hblank_end;
u32 vblank_start, hblank_start;
reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
reg_val |= (link_cfg->bits_per_pixel > 18) ?
NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
/* Skipping programming NV_HEAD_STATE0, assuming:
interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
vtotal = config->vsync_width + config->vback_porch +
config->yres + config->vfront_porch;
htotal = config->hsync_width + config->hback_porch +
config->xres + config->hfront_porch;
tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
vsync_end = config->vsync_width - 1;
hsync_end = config->hsync_width - 1;
tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
vblank_end = vsync_end + config->vback_porch;
hblank_end = hsync_end + config->hback_porch;
tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
vblank_start = vblank_end + config->yres;
hblank_start = hblank_end + config->xres;
tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
/* TODO: adding interlace mode support */
tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
tegra_sor_write_field(sor, NV_SOR_CSTM,
NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
NV_SOR_CSTM_LVDS_EN_ENABLE,
2 << NV_SOR_CSTM_ROTCLK_SHIFT |
(is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
NV_SOR_CSTM_LVDS_EN_DISABLE));
tegra_dc_sor_config_pwm(sor, 1024, 1024);
}