void uart_rx_notify(uint8_t port)
{
UNUSED(port);
/* Transmit first data */
ui_com_rx_start();
usart_enable_callback(&usart_module_edbg, USART_CALLBACK_BUFFER_TRANSMITTED);
tx_data = udi_cdc_getc();
usart_write_buffer_job(&usart_module_edbg, &tx_data, 1);
}
/**
* \internal
* \brief USART interrupt callback function
*
* Called by USART driver when transmit is complete.
*
* * \param module USART module causing the interrupt (not used)
*/
static void usart_tx_callback(struct usart_module *const module)
{
/* Data ready to be sent */
if (udi_cdc_is_rx_ready()) {
/* Transmit next data */
ui_com_rx_start();
tx_data = udi_cdc_getc();
usart_write_buffer_job(&usart_module_edbg, &tx_data, 1);
} else {
/* Fifo empty then Stop UART transmission */
usart_disable_callback(&usart_module_edbg, USART_CALLBACK_BUFFER_TRANSMITTED);
ui_com_rx_stop();
}
}
static void usart_handler(uint8_t port)
{
Usart* usart = get_usart(port);
uint32_t sr = usart_get_status(usart);
if (sr & US_CSR_RXRDY) {
// Data received
ui_com_tx_start();
uint32_t value;
bool b_error = usart_read(usart, &value) ||
(sr & (US_CSR_FRAME | US_CSR_TIMEOUT | US_CSR_PARE));
if (b_error) {
usart_reset_rx(usart);
usart_enable_rx(usart);
udi_cdc_multi_signal_framing_error(port);
ui_com_error();
}
// Transfer UART RX fifo to CDC TX
if (!udi_cdc_multi_is_tx_ready(port)) {
// Fifo full
udi_cdc_multi_signal_overrun(port);
ui_com_overflow();
} else {
udi_cdc_multi_putc(port, value);
}
ui_com_tx_stop();
return;
}
if (sr & US_CSR_TXRDY) {
// Data send
if (udi_cdc_multi_is_rx_ready(port)) {
// Transmit next data
ui_com_rx_start();
int c = udi_cdc_multi_getc(port);
usart_write(usart, c);
} else {
// Fifo empty then Stop UART transmission
usart_disable_tx(usart);
usart_disable_interrupt(usart, US_IDR_TXRDY);
ui_com_rx_stop();
}
}
}