/* Set up and initialize hardware prior to call to main */
void Chip_SetupIrcClocking(void)
{
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(5, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
void initClock()
{
sysctlPowerUp(SYSCTL_POWERDOWN_SYSOSC_PD); // Enable system oscillator
for (volatile int i = 0; i < 1000; i++) { }
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
sysctlPowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/*
* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
* MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
* FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
* FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range)
*/
Chip_Clock_SetupSystemPLL(3, 1);
sysctlPowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
while (!Chip_Clock_IsSystemPLLLocked()) { }
Chip_Clock_SetSysClockDiv(1);
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
SystemCoreClock = Chip_Clock_GetSystemClockRate();
while (SystemCoreClock != 48000000) { } // Loop forever if the clock failed to initialize properly
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
volatile int i;
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait 200us for OSC to be stablized, no status
indication, dummy wait. */
for (i = 0; i < 0x100; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Set USB PLL input to main oscillator */
Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupUSBPLL(3, 1);
/* Powerup USB PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
volatile int i;
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait for at least 580uS for osc to stabilize */
for (i = 0; i < 2500; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup FLASH access to 2 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetMainOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* Setup system clocking */
STATIC void Board_SetupXtalClocking(void)
{
#if USE_CLKIN_IN
uint32_t i;
#endif
/* A library"pmu_library.lib) has been created to facilitate the power management
operation. The user needs to enter the desired frequency the application wants to
run, the set_voltage() will set the internal voltage regulators automatically. */
set_voltage( SYSCTL_IRC_FREQ * PLL_MULTIPLIER );
/* Select the PLL input in the IRC */
#if USE_CLKIN_IN
/* IOCON clock left on, this is needed is CLKIN is used. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 22, IOCON_MODE_PULLUP | IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF);
/* Delay to wait until CLKIN stablized */
for ( i = 0; i < 500; i++ ) {}
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_CLKIN);
/* Wait State setting TBD */
/* Setup FLASH access to 2 clocks (up to 20MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
#else
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Wait State setting TBD */
/* Setup FLASH access to 5 clocks (up to 72MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
#endif
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(PDRUNCFG_PD_SYS_PLL0);
/* First parameter is the multiplier, the second parameter is the input frequency in MHz */
#if USE_CLKIN_IN
Chip_Clock_SetupSystemPLL(PLL_MULTIPLIER, ExtRateIn);
#else
Chip_Clock_SetupSystemPLL(PLL_MULTIPLIER, SYSCTL_IRC_FREQ);
#endif
/* Turn on the PLL by clearing the power down bit */
Chip_SYSCTL_PowerUp(PDRUNCFG_PD_SYS_PLL0);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
STATIC void Board_SetupIRCClocking(void)
{
/* Wait State setting TBD */
/* Setup FLASH access to 2 clocks (up to 20MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_20MHZ_CPU);
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_IRC);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
#ifdef SUPPORT_NXP_MAIN_OSC
volatile uint32_t i;
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
Chip_Clock_SetPLLBypass(0, 0);
for (i = 0; i < 200; i++) __NOP();
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
#else
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
#endif
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
#ifdef SUPPORT_NXP_MAIN_OSC
Chip_Clock_SetupSystemPLL(3, 2);
#else
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
#endif
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
}
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(void)
{
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Turn on the IRC by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
/* Select the PLL input in the IRC */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Setup FLASH access */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetIntOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Configure the PLL M and P dividers */
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Turn on the PLL by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* Clock and PLL initialization based on the external clock input */
void Chip_SetupExtInClocking(uint32_t iFreq)
{
PLL_CONFIG_T pllConfig;
PLL_SETUP_T pllSetup;
PLL_ERROR_T pllError;
/* IOCON clock left on, this is needed is CLKIN is used. */
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_IOCON);
/* Select external clock input pin */
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 22, (IOCON_MODE_PULLUP |
IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF));
/* Select the PLL input to the EXT clock input */
Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_CLKIN);
/* Setup FLASH access */
setupFlashClocks(iFreq);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL);
/* Setup PLL configuration */
pllConfig.desiredRate = iFreq;
pllConfig.InputRate = 0;
pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT;
pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup);
if (pllError == PLL_ERROR_SUCCESS) {
pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT;
pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup);
}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT);
/* ASYSNC SYSCON needs to be on or all serial peripheral won't work.
Be careful if PLL is used or not, ASYNC_SYSCON source needs to be
selected carefully. */
Chip_SYSCON_Enable_ASYNC_Syscon(true);
Chip_Clock_SetAsyncSysconClockDiv(1);
Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_IRC);
}
void ReinvokeISP(void)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
if(ISP_Request == 0x12345678)
{
ISP_Request = 0;
//ReinvokeISP(); //Jump to USB ISP bootloader
//}
/* make sure USB clock is turned on before calling ISP */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
/* make sure 32-bit Timer 1 is turned on before calling ISP */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_CT32B1);
/* make sure GPIO clock is turned on before calling ISP */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
/* make sure IO configuration clock is turned on before calling ISP */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
/* make sure AHB clock divider is 1:1 */
Chip_Clock_SetSysClockDiv(1);
/* Send Reinvoke ISP command to ISP entry point*/
IAP_Command[0] = IAP_REINVOKE_ISP; //Reinvoke bootloader command (57)
init_msdstate(); /* Initialize Storage state machine */
/* Set stack pointer to ROM value (reset default) This must be the last
piece of code executed before calling ISP, because most C expressions
and function returns will fail after the stack pointer is changed. */
__set_MSP(*((uint32_t *)0x00000000));
/* Enter ISP. We call "iap_entry" to enter ISP because the ISP entry is done
through the same command interface as IAP. */
iap_entry(IAP_Command, IAP_Result);
// Not supposed to come back!
//vPortExitCritical();
}
}
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(uint32_t iFreq)
{
PLL_CONFIG_T pllConfig;
PLL_SETUP_T pllSetup;
PLL_ERROR_T pllError;
/* Turn on the IRC by clearing the power down bit */
Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_IRC_OSC | SYSCON_PDRUNCFG_PD_IRC);
/* Select the PLL input to the IRC */
Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC);
/* Setup FLASH access */
setupFlashClocks(iFreq);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL);
/* Setup PLL configuration */
pllConfig.desiredRate = iFreq;
pllConfig.InputRate = 0;
pllConfig.flags = PLL_CONFIGFLAG_FORCENOFRACT;
pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup);
if (pllError == PLL_ERROR_SUCCESS) {
pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT;
pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup);
}
Chip_Clock_SetSysClockDiv(1);
Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT);
//Chip_Clock_SetCLKOUTSource(SYSCON_CLKOUTSRC_MAINCLK, 1);
/* ASYSNC SYSCON needs to be on or all serial peripheral won't work.
Be careful if PLL is used or not, ASYNC_SYSCON source needs to be
selected carefully. */
Chip_SYSCON_Enable_ASYNC_Syscon(true);
Chip_Clock_SetAsyncSysconClockDiv(4);
Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_MAINCLK);//SYSCON_ASYNC_IRC);//SYSCON_ASYNC_SYSPLLOUT
}
