static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg) { unsigned ctrl = 0; if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) { if (dpot->feat & F_RDACS_WONLY) return dpot->rdac_cache[reg & DPOT_RDAC_MASK]; if (dpot->uid == DPOT_UID(AD5291_ID) || dpot->uid == DPOT_UID(AD5292_ID) || dpot->uid == DPOT_UID(AD5293_ID)) return dpot_read_r8d8(dpot, DPOT_AD5291_READ_RDAC << 2); ctrl = DPOT_SPI_READ_RDAC; } else if (reg & DPOT_ADDR_EEPROM) { ctrl = DPOT_SPI_READ_EEPROM; } if (dpot->feat & F_SPI_16BIT) return dpot_read_r8d8(dpot, ctrl); else if (dpot->feat & F_SPI_24BIT) return dpot_read_r8d16(dpot, ctrl); return -EFAULT; }
static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg) { unsigned ctrl = 0; int value; if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) { if (dpot->feat & F_RDACS_WONLY) return dpot->rdac_cache[reg & DPOT_RDAC_MASK]; if (dpot->uid == DPOT_UID(AD5291_ID) || dpot->uid == DPOT_UID(AD5292_ID) || dpot->uid == DPOT_UID(AD5293_ID)) { value = dpot_read_r8d8(dpot, DPOT_AD5291_READ_RDAC << 2); if (dpot->uid == DPOT_UID(AD5291_ID)) value = value >> 2; return value; } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg) { unsigned ctrl = 0; switch (dpot->uid) { case DPOT_UID(AD5246_ID): case DPOT_UID(AD5247_ID): return dpot_read_d8(dpot); case DPOT_UID(AD5245_ID): case DPOT_UID(AD5241_ID): case DPOT_UID(AD5242_ID): case DPOT_UID(AD5243_ID): case DPOT_UID(AD5248_ID): case DPOT_UID(AD5280_ID): case DPOT_UID(AD5282_ID): ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? 0 : DPOT_AD5291_RDAC_AB; return dpot_read_r8d8(dpot, ctrl); case DPOT_UID(AD5170_ID): case DPOT_UID(AD5171_ID): case DPOT_UID(AD5273_ID): return dpot_read_d8(dpot); case DPOT_UID(AD5172_ID): case DPOT_UID(AD5173_ID): ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? 0 : DPOT_AD5272_3_A0; return dpot_read_r8d8(dpot, ctrl); default: if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256)) return dpot_read_r8d16(dpot, (reg & 0xF8) | ((reg & 0x7) << 1)); else return dpot_read_r8d8(dpot, reg); } }