int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; DSP_ISA_SLAVE_CONTROL rSlaveControl; PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n"); rSlaveControl.ClockControl = 0; rSlaveControl.SoftReset = TRUE; rSlaveControl.ConfigMode = FALSE; rSlaveControl.Reserved = 0; spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); udelay(5); rSlaveControl.ClockControl = 1; OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); spin_unlock_irqrestore(&dsp_lock, flags); udelay(5); PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n"); return 0; }
void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO, unsigned long ulMsaAddr, unsigned short usValue) { PRINTK_4(TRACE_3780I, "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n", usDspBaseIO, ulMsaAddr, usValue); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); OutWordDsp(DSP_MsaDataDSISHigh, usValue); spin_unlock_irqrestore(&dsp_lock, flags); }
int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned uCount, unsigned long ulDSPAddr) { unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; PRINTK_5(TRACE_3780I, "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", usDspBaseIO, pusBuffer, uCount, ulDSPAddr); /* * Set the initial MSA address. To convert from an instruction store * address to an MSA address * shift the address two bits to the left and set bit 22 */ ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); spin_unlock_irqrestore(&dsp_lock, flags); /* Transfer the memory block */ while (uCount-- != 0) { unsigned short val_lo, val_hi; if(get_user(val_lo, pusBuffer++)) return -EFAULT; if(get_user(val_hi, pusBuffer++)) return -EFAULT; spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaDataISLow, val_lo); OutWordDsp(DSP_MsaDataDSISHigh, val_hi); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_4(TRACE_3780I, "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", uCount, val_lo, val_hi); PaceMsaAccess(usDspBaseIO); } PRINTK_1(TRACE_3780I, "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n"); return 0; }
int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned uCount, unsigned long ulDSPAddr) { unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; PRINTK_5(TRACE_3780I, "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", usDspBaseIO, pusBuffer, uCount, ulDSPAddr); ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); spin_unlock_irqrestore(&dsp_lock, flags); while (uCount-- != 0) { unsigned short val_lo, val_hi; if(get_user(val_lo, pusBuffer++)) return -EFAULT; if(get_user(val_hi, pusBuffer++)) return -EFAULT; spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaDataISLow, val_lo); OutWordDsp(DSP_MsaDataDSISHigh, val_hi); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_4(TRACE_3780I, "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", uCount, val_lo, val_hi); PaceMsaAccess(usDspBaseIO); } PRINTK_1(TRACE_3780I, "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n"); return 0; }
int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, unsigned short *pusIPCSource) { unsigned long flags; DSP_HBRIDGE_CONTROL rHBridgeControl; unsigned short temp; PRINTK_3(TRACE_3780I, "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n", usDspBaseIO, pusIPCSource); /* * Disable DSP to PC interrupts, read the interrupt register, * clear the pending IPC bits, and reenable DSP to PC interrupts */ spin_lock_irqsave(&dsp_lock, flags); MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); rHBridgeControl.EnableDspInt = FALSE; OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); *pusIPCSource = InWordDsp(DSP_Interrupt); temp = (unsigned short) ~(*pusIPCSource); PRINTK_3(TRACE_3780I, "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n", *pusIPCSource, temp); OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource)); rHBridgeControl.EnableDspInt = TRUE; OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_2(TRACE_3780I, "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n", *pusIPCSource); return 0; }
int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned uCount, unsigned long ulDSPAddr) { unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; PRINTK_5(TRACE_3780I, "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", usDspBaseIO, pusBuffer, uCount, ulDSPAddr); /* Set the initial MSA address. No adjustments need to be made to data store addresses */ spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); spin_unlock_irqrestore(&dsp_lock, flags); /* Transfer the memory block */ while (uCount-- != 0) { unsigned short val; if(get_user(val, pusBuffer++)) return -EFAULT; spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaDataDSISHigh, val); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_3(TRACE_3780I, "3780I::dsp3780I_WriteDStore uCount %x val %x\n", uCount, val); PaceMsaAccess(usDspBaseIO); } PRINTK_1(TRACE_3780I, "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n"); return 0; }
int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; DSP_BOOT_DOMAIN rBootDomain; DSP_HBRIDGE_CONTROL rHBridgeControl; PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n"); /* Transition the core to a running state */ rBootDomain.ResetCore = TRUE; rBootDomain.Halt = FALSE; rBootDomain.NMI = TRUE; rBootDomain.Reserved = 0; WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); udelay(5); rBootDomain.ResetCore = FALSE; WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); udelay(5); rBootDomain.NMI = FALSE; WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); udelay(5); /* Enable DSP to PC interrupt */ spin_lock_irqsave(&dsp_lock, flags); MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); rHBridgeControl.EnableDspInt = TRUE; PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n", MKWORD(rHBridgeControl)); OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n"); return 0; }
int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; DSP_BOOT_DOMAIN rBootDomain; DSP_HBRIDGE_CONTROL rHBridgeControl; PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n"); spin_lock_irqsave(&dsp_lock, flags); /* Mask DSP to PC interrupt */ MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n", MKWORD(rHBridgeControl)); rHBridgeControl.EnableDspInt = FALSE; OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); /* Reset the core via the boot domain register */ rBootDomain.ResetCore = TRUE; rBootDomain.Halt = TRUE; rBootDomain.NMI = TRUE; rBootDomain.Reserved = 0; PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n", MKWORD(rBootDomain)); WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); /* Reset all the chiplets and then reactivate them */ WriteMsaCfg(DSP_ChipReset, 0xFFFF); udelay(5); WriteMsaCfg(DSP_ChipReset, (unsigned short) (~pSettings->usChipletEnable)); PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n"); return 0; }
unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO, unsigned long ulMsaAddr) { unsigned short val; PRINTK_3(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n", usDspBaseIO, ulMsaAddr); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); val = InWordDsp(DSP_MsaDataDSISHigh); spin_unlock_irqrestore(&dsp_lock, flags); PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); return val; }
int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, void __user *pvBuffer, unsigned uCount, unsigned long ulDSPAddr) { unsigned long flags; unsigned short __user *pusBuffer = pvBuffer; unsigned short val; PRINTK_5(TRACE_3780I, "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", usDspBaseIO, pusBuffer, uCount, ulDSPAddr); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); spin_unlock_irqrestore(&dsp_lock, flags); while (uCount-- != 0) { spin_lock_irqsave(&dsp_lock, flags); val = InWordDsp(DSP_ReadAndClear); spin_unlock_irqrestore(&dsp_lock, flags); if(put_user(val, pusBuffer++)) return -EFAULT; PRINTK_3(TRACE_3780I, "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n", uCount, val); PaceMsaAccess(usDspBaseIO); } PRINTK_1(TRACE_3780I, "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n"); return 0; }
int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, unsigned short *pIrqMap, unsigned short *pDmaMap) { unsigned long flags; unsigned short usDspBaseIO = pSettings->usDspBaseIO; int i; DSP_UART_CFG_1 rUartCfg1; DSP_UART_CFG_2 rUartCfg2; DSP_HBRIDGE_CFG_1 rHBridgeCfg1; DSP_HBRIDGE_CFG_2 rHBridgeCfg2; DSP_BUSMASTER_CFG_1 rBusmasterCfg1; DSP_BUSMASTER_CFG_2 rBusmasterCfg2; DSP_ISA_PROT_CFG rIsaProtCfg; DSP_POWER_MGMT_CFG rPowerMgmtCfg; DSP_HBUS_TIMER_CFG rHBusTimerCfg; DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable; DSP_CHIP_RESET rChipReset; DSP_CLOCK_CONTROL_1 rClockControl1; DSP_CLOCK_CONTROL_2 rClockControl2; DSP_ISA_SLAVE_CONTROL rSlaveControl; DSP_HBRIDGE_CONTROL rHBridgeControl; unsigned short ChipID = 0; unsigned short tval; PRINTK_2(TRACE_3780I, "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n", pSettings->bDSPEnabled); if (!pSettings->bDSPEnabled) { PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); return -EIO; } PRINTK_2(TRACE_3780I, "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n", pSettings->bModemEnabled); if (pSettings->bModemEnabled) { rUartCfg1.Reserved = rUartCfg2.Reserved = 0; rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow; rUartCfg1.IrqPulse = pSettings->bUartIrqPulse; rUartCfg1.Irq = (unsigned char) pIrqMap[pSettings->usUartIrq]; switch (pSettings->usUartBaseIO) { case 0x03F8: rUartCfg1.BaseIO = 0; break; case 0x02F8: rUartCfg1.BaseIO = 1; break; case 0x03E8: rUartCfg1.BaseIO = 2; break; case 0x02E8: rUartCfg1.BaseIO = 3; break; } rUartCfg2.Enable = TRUE; } rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0; rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow; rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse; rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq]; rHBridgeCfg1.AccessMode = 1; rHBridgeCfg2.Enable = TRUE; rBusmasterCfg2.Reserved = 0; rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma]; rBusmasterCfg1.NumTransfers = (unsigned char) pSettings->usNumTransfers; rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest; rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16; rBusmasterCfg2.IsaMemCmdWidth = (unsigned char) pSettings->usIsaMemCmdWidth; rIsaProtCfg.Reserved = 0; rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY; rPowerMgmtCfg.Reserved = 0; rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt; rHBusTimerCfg.LoadValue = (unsigned char) pSettings->usHBusTimerLoadValue; rLBusTimeoutDisable.Reserved = 0; rLBusTimeoutDisable.DisableTimeout = pSettings->bDisableLBusTimeout; MKWORD(rChipReset) = ~pSettings->usChipletEnable; rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0; rClockControl1.N_Divisor = pSettings->usN_Divisor; rClockControl1.M_Multiplier = pSettings->usM_Multiplier; rClockControl2.Reserved = 0; rClockControl2.PllBypass = pSettings->bPllBypass; /* Issue a soft reset to the chip */ /* Note: Since we may be coming in with 3780i clocks suspended, we must keep * soft-reset active for 10ms. */ rSlaveControl.ClockControl = 0; rSlaveControl.SoftReset = TRUE; rSlaveControl.ConfigMode = FALSE; rSlaveControl.Reserved = 0; PRINTK_4(TRACE_3780I, "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n", usDspBaseIO, DSP_IsaSlaveControl, usDspBaseIO + DSP_IsaSlaveControl); PRINTK_2(TRACE_3780I, "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n", MKWORD(rSlaveControl)); spin_lock_irqsave(&dsp_lock, flags); OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); PRINTK_2(TRACE_3780I, "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval); for (i = 0; i < 11; i++) udelay(2000); rSlaveControl.SoftReset = FALSE; OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); PRINTK_2(TRACE_3780I, "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval); /* Program our general configuration registers */ WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1)); WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2)); WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1)); WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2)); WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg)); WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg)); WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg)); if (pSettings->bModemEnabled) { WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1)); WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2)); } rHBridgeControl.EnableDspInt = FALSE; rHBridgeControl.MemAutoInc = TRUE; rHBridgeControl.IoAutoInc = FALSE; rHBridgeControl.DiagnosticMode = FALSE; PRINTK_3(TRACE_3780I, "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n", DSP_HBridgeControl, MKWORD(rHBridgeControl)); OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); spin_unlock_irqrestore(&dsp_lock, flags); WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable)); WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1)); WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2)); WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset)); ChipID = ReadMsaCfg(DSP_ChipID); PRINTK_2(TRACE_3780I, "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n", ChipID); return 0; }